CN220795674U - Low-power consumption timer of MCU - Google Patents
Low-power consumption timer of MCU Download PDFInfo
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- CN220795674U CN220795674U CN202322444387.7U CN202322444387U CN220795674U CN 220795674 U CN220795674 U CN 220795674U CN 202322444387 U CN202322444387 U CN 202322444387U CN 220795674 U CN220795674 U CN 220795674U
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Abstract
The utility model relates to a low-power-consumption timer of an MCU. The low power consumption timer of the MCU comprises a time base unit, a synchronous signal unit and a capturing/comparing unit, and further comprises: a register unit, a first control circuit and a second control circuit; the register unit outputs a signal source selection signal to the first control circuit, and the first control circuit outputs a corresponding activation enabling signal or a sleep enabling signal to the synchronous signal unit according to the signal source selection signal so as to enable the corresponding signal source included in the synchronous signal unit to activate or sleep; the register unit outputs a channel selection signal to a second control circuit, which outputs a corresponding activation enable signal or sleep enable signal to the capture/compare unit according to the channel selection signal to activate or sleep a corresponding channel included in the capture/compare unit. The low-power-consumption timer of the MCU can reduce the power consumption consumed by the chip under the condition that the working efficiency of the timer is unchanged.
Description
Technical Field
The utility model relates to the technical field of electronics, in particular to a low-power-consumption timer of an MCU.
Background
In the MCU, the timer is the module with the highest frequency of use. With the rapid development of the MCU, the timer plays a role in the MCU not only in realizing the basic counting function, but also in realizing multiple working modes. Today's timers, like the heart of an MCU, provide a well-ordered time base and other advanced functions for an MCU. Thus, the research of the timer is a key step in the development of the MCU.
With the continuous development of integrated circuit manufacturing processes, the number of transistors that a single chip can accommodate can reach hundreds of millions, and the power consumption problem caused by the single chip has become a necessary factor to be considered in chip design. As the aggregate size of semiconductors becomes smaller, the supply voltage becomes lower, the cell threshold voltage becomes smaller, the circuit scale becomes larger, and the power consumption density of the chip becomes higher and the leakage current becomes larger. For chips of the micron-scale process, the power consumption can directly influence the performances of the circuit, such as the working speed, the working time length and the like, and when the power consumption is overlarge, the heat generated during working reaches a certain degree, so that the circuit cannot work. Low power consumption designs have therefore become one of the main bottlenecks in chip design.
The existing timer can realize multiple functions of timing, control, measurement and the like. The internal structure of the timer mainly comprises a time base unit, a synchronous signal unit, a capturing/comparing unit and the like; wherein the time base unit is a core unit of the timer for providing a count signal; the synchronous signal unit is used for providing various clocks such as an internal clock source, an external clock mode and the like as the selection of the timer; the capture/compare unit is used for providing input capture and output comparison functions for processing the signal of the input timer and the signal of the output timer, respectively.
Disclosure of Invention
Therefore, the utility model aims to provide the low-power-consumption timer of the MCU, which reduces the power consumption of the timer of the MCU.
In order to achieve the above object, the present utility model provides a low power consumption timer of an MCU, including a time base unit, a synchronization signal unit, and a capturing/comparing unit, further including: a register unit, a first control circuit and a second control circuit; the register unit outputs a signal source selection signal to the first control circuit, and the first control circuit outputs a corresponding activation enabling signal or a sleep enabling signal to the synchronous signal unit according to the signal source selection signal so as to enable the corresponding signal source included in the synchronous signal unit to activate or sleep; the register unit outputs a channel selection signal to a second control circuit, which outputs a corresponding activation enable signal or sleep enable signal to the capture/compare unit according to the channel selection signal to activate or sleep a corresponding channel included in the capture/compare unit.
The synchronous signal unit comprises an internal clock source and an external clock mode.
Wherein the capture/compare unit comprises four capture/compare channels.
The MCU further comprises a gating clock circuit, wherein the gating clock circuit is connected with a proper register in a low-power-consumption timer of the MCU so as to avoid invalid clock signal overturning.
The gating clock circuit consists of a low-level enabling latch and an AND gate.
The low-power consumption timer also comprises an operand isolation circuit, wherein the operand isolation circuit is connected with a proper counter in the low-power consumption timer of the MCU to avoid invalid rollover.
In summary, the low-power-consumption timer of the MCU can reduce the power consumption consumed by the chip under the condition that the working efficiency of the timer is unchanged.
Drawings
The technical solution and other advantageous effects of the present utility model will be made apparent by the following detailed description of the specific embodiments of the present utility model with reference to the accompanying drawings.
In the drawings of which there are shown,
FIG. 1 is a schematic circuit diagram of a low power timer of the MCU of the present utility model;
FIG. 2a is a schematic diagram of a register without a gating clock circuit in a preferred embodiment of the low power consumption timer of the MCU of the present utility model;
FIG. 2b is a schematic diagram of a register with a clock gating circuit according to a preferred embodiment of the low power timer of the MCU of the present utility model;
FIG. 3a is a schematic diagram of a counter without an operand isolation circuit according to a preferred embodiment of the low power timer of the MCU of the present utility model;
FIG. 3b is a schematic diagram of a counter with an operand isolation circuit according to a preferred embodiment of the low power timer of the MCU of the present utility model.
Detailed Description
Referring to FIG. 1, a schematic block diagram of a low power timer of the MCU of the present utility model is shown. Firstly, the utility model provides a system design of a timer, the low-power-consumption timer can control various working modes through a simple control circuit by depending on the configuration of a register, and the power consumption is reduced flexibly. The utility model relates to a low-power consumption timer of an MCU, which mainly comprises a time base unit, a synchronous signal unit and a capturing/comparing unit, wherein the time base unit is a core unit of the timer and is used for providing a counting signal; the synchronous signal unit is used for providing various clocks such as an internal clock source, an external clock mode and the like as the selection of the timer; the capture/comparison unit is used for providing input capture and output comparison functions and is used for processing signals of the input timer and signals of the output timer respectively; it can be understood by those skilled in the art that the present utility model aims to realize low power consumption design of the timer, so that other parts of the timer are not described herein, and in order to realize low power consumption design, the timer of the present utility model further comprises: a register unit, a first control circuit and a second control circuit; the register unit outputs a signal source selection signal SMS/ECE to a first control circuit, and the first control circuit outputs a corresponding activation enabling signal A or a sleep enabling signal S to the synchronous signal unit according to the signal source selection signal SMS/ECE so as to enable corresponding signal sources included in the synchronous signal unit to activate or sleep; the register unit outputs a channel selection signal CCxS to a second control circuit, which outputs a corresponding activation enable signal a or sleep enable signal S to the capture/compare unit according to the channel selection signal CCxS to activate or sleep a corresponding channel included in the capture/compare unit.
In the preferred embodiment, the synchronization signal unit includes an internal clock source, and an external clock mode 1 and an external clock mode 2. The capture/compare unit comprises four capture/compare channels 1-4. Those skilled in the art will appreciate that the number of clock sources and capture/compare channels may be other numbers depending on the timer.
Referring to fig. 1, the present utility model performs circuit module division on different functional units to perform low power consumption management. The specific measures are to divide the functional units which participate in the work and the functional units which do not participate in the work, and the functional units which do not participate in the work are controlled by a control circuit and enter a sleep state. The low power design at the system level mainly considers the synchronization signal unit and the acquisition/comparison unit, and the time base unit is the core unit of the low power timer, and any working mode needs the support of the time base unit, so that the low power control at the system level is not considered.
Furthermore, the low-power-consumption timer of the MCU also adopts a design structure of a gating clock, and a certain part of the timer is added with a large number of NAND gates and other parts, so that a plurality of meaningless overturns can be omitted, and a chip can omit certain power consumption. Since the timer design of the MCU originally comprises a plurality of registers, the utility model adopts a gating clock circuit to connect the proper registers in the low-power-consumption timer of the MCU so as to avoid invalid clock signal inversion.
Referring to fig. 2a and 2b, fig. 2a is a schematic circuit diagram of a register to which a gating clock circuit is not added in a preferred embodiment of the low power consumption timer of the MCU of the present utility model, and fig. 2b is a schematic circuit diagram of a register to which a gating clock circuit is added in a preferred embodiment of the low power consumption timer of the MCU of the present utility model.
The dynamic power consumption can be reduced by inserting the gating clock circuit in the design, and the effect is obvious. The clock signal is directly connected to a plurality of registers, and no matter whether the registers work or not, the inversion of the clock signal can bring about the increase of power consumption, thereby influencing the power consumption of the whole system. Before the register is inserted into the gating clock, when some modules do not work, the clock signal is not turned off, so that the power consumption caused by invalid inversion of the clock signal is increased.
In the circuit design of the MCU low-power-consumption timer, a large amount of gating clocks are inserted to reduce the power consumption caused by invalid turnover of clock signals under the condition of meeting the design requirement. For the gated clock technique, there are mainly three implementation methods, namely a separate and gate, a distributed Latch-and-gate and an integrated Latch-and-gate. Fig. 2a and 2b are diagrams of the circuit before and after the insertion of the gating clock technique according to the preferred embodiment of the present utility model, in which the implementation is a low-level enabled Latch plus and gate structure.
Furthermore, the low-power-consumption timer of the MCU also adopts the design structure of an operand isolation technology, and in the design of each counter, a method of operand isolation can bring great power consumption benefits. Since the timer design of the MCU originally comprises a plurality of counters, the utility model adopts an operand isolation circuit to connect the proper counters in the low-power-consumption timer of the MCU so as to avoid invalid turnover.
Referring to fig. 3a and fig. 3b, fig. 3a is a schematic circuit diagram of a counter without an operand isolation circuit in a preferred embodiment of the low power consumption timer of the MCU of the present utility model, and fig. 3b is a schematic circuit diagram of a counter with an operand isolation circuit in a preferred embodiment of the low power consumption timer of the MCU of the present utility model.
In the digital design process, if the operand isolation method is not used, a part of meaningless power consumption is increased. If operand isolation is added, select devices are added, which are not selected if not needed and do not perform the operations previously needed to calculate the operand. For example, when performing an alternative operation, the alternative paths have a and B, if the a path is selected, then a large amount of computation before the B path is unnecessary, and using operand isolation can effectively avoid invalid computation of the B path.
As shown in fig. 3a and 3b, before the operand isolation technique is adopted, when cnt_sel is not equal to 0 and ug_reg is not equal to 0, the counter will return to 0 (here ug_reg is the event generating register update generating bit UG), then the 1-up operation before the counter is invalid, and the invalid flip will bring useless power consumption burden; after the operand isolation technology is adopted, when the output of the add 1 operation is not needed, the data transmission to the add operation is stopped, the cnt_psc is stopped in the fixed value of the last state, invalid turnover is not generated any more, and the power consumption is reduced. When the counter needs to be incremented by 1, the enable logic releases the stalled state of the adder.
By adopting the design of the low-power-consumption timer of the MCU, the power consumption consumed by the chip can be obviously reduced under the condition of unchanged working efficiency. In order to verify the power consumption benefits brought by the gating clock technology and the operand isolation technology, firstly, performing power consumption analysis on an RTL netlist without the gating clock and operand isolation inserted, wherein the total power consumption of the design is 0.6767mW; and then inserting gating and operand isolation into the RTL netlist and performing power consumption analysis, wherein the total power consumption of the design is 0.3602mW. Through evaluation, the gating clock and operand isolation are inserted in the design, so that 46.8% of total power consumption benefit can be obtained.
In summary, the low-power-consumption timer of the MCU can reduce the power consumption consumed by the chip under the condition that the working efficiency of the timer is unchanged.
In the above, it is obvious to those skilled in the art that various other corresponding changes and modifications can be made according to the technical scheme and the technical idea of the present utility model, and all such changes and modifications are intended to fall within the scope of the appended claims.
Claims (6)
1. A low power consumption timer of an MCU, comprising a time base unit, a synchronization signal unit and a capturing/comparing unit, further comprising: a register unit, a first control circuit and a second control circuit; the register unit outputs a signal source selection signal to the first control circuit, and the first control circuit outputs a corresponding activation enabling signal or a sleep enabling signal to the synchronous signal unit according to the signal source selection signal so as to enable the corresponding signal source included in the synchronous signal unit to activate or sleep; the register unit outputs a channel selection signal to a second control circuit, which outputs a corresponding activation enable signal or sleep enable signal to the capture/compare unit according to the channel selection signal to activate or sleep a corresponding channel included in the capture/compare unit.
2. The low power timer of the MCU of claim 1, wherein the synchronization signal unit includes an internal clock source, and an external clock mode.
3. The low power timer of the MCU of claim 1, wherein the capture/compare unit comprises four capture/compare channels.
4. The MCU low power timer of claim 1, further comprising a gating clock circuit that interfaces with a suitable register in the MCU low power timer to avoid invalid clock signal toggling.
5. The MCU low power timer of claim 4, wherein the gating clock circuit is comprised of a low level enable latch and an and gate.
6. The low power timer for the MCU of claim 1, further comprising an operand isolation circuit connected to a suitable counter in the low power timer for the MCU to avoid invalid flip.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202322444387.7U CN220795674U (en) | 2023-09-08 | 2023-09-08 | Low-power consumption timer of MCU |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202322444387.7U CN220795674U (en) | 2023-09-08 | 2023-09-08 | Low-power consumption timer of MCU |
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