CN114188389B - TFT array substrate, manufacturing method thereof and OLED display panel - Google Patents
TFT array substrate, manufacturing method thereof and OLED display panel Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/122—Pixel-defining structures or layers, e.g. banks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
- H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
Abstract
The application provides a TFT array substrate, a manufacturing method thereof and an OLED display panel. The TFT array substrate comprises a substrate, a first electrode layer, a first insulating layer, a second electrode layer, a second insulating layer and a third electrode layer. The first electrode layer comprises a first electrode wire arranged on the substrate. The first insulating layer is provided with a first via hole exposing the first electrode wire. The second electrode layer comprises a first lap electrode arranged in the first via hole and a first protection electrode arranged on the first lap electrode. The second insulating layer is provided with a second via hole exposing the first protective electrode. The third electrode layer comprises a second electrode wire arranged in the second via hole. The overlap joint distance of the second electrode wire and the first electrode wire can be shortened, the first protection electrode can avoid the first overlap joint electrode from being etched, and the second through holes can be etched uniformly, so that the second electrode wire and the first electrode wire are prevented from being overlapped abnormally.
Description
Technical Field
The application relates to the technical field of display devices, in particular to a TFT array substrate, a manufacturing method thereof and an OLED display panel.
Background
The electroluminescent diode (OLED) has advantages of simple manufacturing process, low cost, high luminous efficiency, easy formation of flexible structure, low power consumption, high color saturation, wide viewing angle, etc., and the display technology using the electroluminescent diode has become an important display technology.
An OLED is a current-type light emitting device that mainly includes an anode, a cathode, and an organic material functional layer. The main working principle of the OLED is as follows: the organic material functional layer emits light by carrier injection and recombination under the drive of an electric field formed by the anode and the cathode.
In order to be applied to the driving display of the high-resolution OLED display panel and reduce the charge-discharge delay time, the electrodes (i.e., traces) in the TFT (thin film transistor) array substrate in the prior art need to use thicker metal materials to reduce the resistance of the electrodes. However, when the electrodes are thickened, insulating layers between the multi-layer electrodes are correspondingly thickened, via holes overlapped by the multi-layer electrodes are also deepened, abnormal overlapped among the multi-layer electrodes is easily caused, and in the process of etching the via holes, uneven etching of the thicker insulating layers is easily caused, so that the display effect is affected.
Disclosure of Invention
The application provides a TFT array substrate, a manufacturing method thereof and an OLED display panel, and aims to solve the problems of uneven etching of a via hole and abnormal overlapping among multiple layers of electrodes caused by deepening of the via hole overlapped by the multiple layers of electrodes in the TFT array substrate in the prior art.
In one aspect, the present application provides a TFT array substrate, including:
a substrate;
the first electrode layer comprises a first electrode wire arranged on the substrate;
the first insulating layer is arranged on the substrate and the first electrode layer, and a first via hole exposing the first electrode wiring is formed in the first insulating layer;
the second electrode layer comprises a first lap joint electrode which is arranged in the first via hole and connected with the first electrode wire, and a first protection electrode which is arranged on the first lap joint electrode;
the second insulating layer is arranged on the second electrode layer and the first insulating layer, and a second via hole exposing the first protection electrode is formed in the second insulating layer;
and the third electrode layer comprises a second electrode wire which is arranged in the second via hole and connected with the first protection electrode.
In some possible implementations, the first electrode layer further includes a light shielding layer disposed on the substrate;
the first insulating layer is also provided with a third via hole exposing the shading layer;
the second electrode layer also comprises a second lap electrode which is arranged in the third via hole and connected with the shading layer, and a second protection electrode which is arranged on the second lap electrode;
the second insulating layer is provided with a fourth via hole exposing the second protective electrode;
the third electrode layer further comprises a source electrode which is arranged in the fourth via hole and connected with the second protection electrode.
In some possible implementations, the second electrode layer further includes an active layer disposed on the first insulating layer, and a third guard electrode disposed on the active layer;
the second insulating layer is also provided with a fifth via hole exposing the third protective electrode;
the third electrode layer further comprises a source electrode which is arranged in the fifth via hole and connected with the third protection electrode.
In some possible implementations, the second electrode layer further includes a fourth guard electrode disposed on the active layer, the fourth guard electrode being spaced apart from the third guard electrode;
the second insulating layer is also provided with a sixth via hole exposing the fourth protective electrode;
the third electrode layer further comprises a drain electrode which is arranged in the sixth via hole and connected with the fourth protection electrode.
In some possible implementations, the TFT array substrate further includes a third insulating layer disposed between the active layer and the second insulating layer, and a gate electrode disposed between the third insulating layer and the second insulating layer.
On the other hand, the application also provides an OLED display panel, which comprises the TFT array substrate.
In still another aspect, the present application further provides a method for manufacturing a TFT array substrate, including:
providing a substrate, and manufacturing a first electrode layer on the substrate, wherein the first electrode layer comprises a first electrode wiring arranged on the substrate;
manufacturing a first insulating layer on the substrate and the first electrode layer, and etching the first insulating layer to form a first via hole exposing the first electrode wiring;
manufacturing a second electrode layer on the first insulating layer, wherein the second electrode layer comprises a first lap joint electrode which is arranged in the first via hole and connected with the first electrode wire, and a first protection electrode which is arranged on the first lap joint electrode;
manufacturing a second insulating layer on the second electrode layer and the first insulating layer, and etching the second insulating layer to form a second via hole exposing the first protection electrode;
and manufacturing a third electrode layer on the second insulating layer, wherein the third electrode layer comprises a second electrode wire which is arranged in the second via hole and connected with the first protection electrode.
In some possible implementations, the first electrode layer further includes a light shielding layer disposed on the substrate;
the first insulating layer is also provided with a third via hole exposing the shading layer;
the second electrode layer also comprises a second lap electrode which is arranged in the third via hole and connected with the shading layer, and a second protection electrode which is arranged on the second lap electrode;
the second insulating layer is provided with a fourth via hole exposing the second protective electrode;
the third electrode layer further comprises a source electrode which is arranged in the fourth via hole and connected with the second protection electrode.
In some possible implementations, the second electrode layer further includes an active layer disposed on the first insulating layer, and a third guard electrode disposed on the active layer;
the second insulating layer is also provided with a fifth via hole exposing the third protective electrode;
the third electrode layer further comprises a source electrode which is arranged in the fifth via hole and connected with the third protection electrode.
In some possible implementations, the second electrode layer further includes a fourth guard electrode disposed on the active layer, the fourth guard electrode being spaced apart from the third guard electrode;
the second insulating layer is also provided with a sixth via hole exposing the fourth protective electrode;
the third electrode layer further comprises a drain electrode which is arranged in the sixth via hole and connected with the fourth protection electrode.
The TFT array substrate comprises a substrate, a first electrode layer, a first insulating layer, a second electrode layer, a second insulating layer and a third electrode layer. The first electrode layer comprises a first electrode wire arranged on the substrate. The first insulating layer is arranged on the substrate and the first electrode layer, and the first insulating layer is provided with a first via hole exposing the first electrode wiring. The second electrode layer comprises a first lap-joint electrode arranged in the first via hole and connected with the first electrode wire, and a first protection electrode arranged on the first lap-joint electrode. The second insulating layer is arranged on the second electrode layer and the first insulating layer, and a second through hole exposing the first protection electrode is formed in the second insulating layer. The third electrode layer comprises a second electrode wire which is arranged in the second via hole and connected with the first protection electrode. That is, the first protection electrode and the first overlap electrode are connected through the first electrode wire, the first protection electrode is connected through the second electrode wire, the overlap joint of the second electrode wire and the first electrode wire is realized, and compared with the prior art, the overlap joint of the second electrode wire and the first electrode wire is directly realized, so that the overlap joint distance between the second electrode wire and the first electrode wire can be shortened. And the first protection electrode can be corrosion-resistant material, and in the process of forming the second through hole on the second insulating layer, the first protection electrode can not only prevent over etching and avoid the first overlap electrode from being etched, but also can enable the second through hole to be etched uniformly, ensure that the second through hole can expose the first protection electrode so as to ensure the overlap joint of the second electrode wiring and the first protection electrode, and avoid the abnormal overlap joint of the second electrode wiring and the first electrode wiring.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic view of a TFT array substrate according to an embodiment of the present application;
FIG. 2 is a flowchart of a method for fabricating a TFT array substrate according to an embodiment of the disclosure;
fig. 3 is a schematic diagram of a method for manufacturing a TFT array substrate according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the description of the present application, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," etc. indicate or are based on the orientation or positional relationship shown in the drawings, merely for convenience of description and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically connected, electrically connected or can be communicated with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.
In this application, unless expressly stated or limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, and may also include the first and second features not being in direct contact but being in contact with each other by way of additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is less level than the second feature.
The following disclosure provides many different embodiments or examples for implementing different structures of the present application. In order to simplify the disclosure of the present application, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. Furthermore, the present application may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not in themselves indicate the relationship between the various embodiments-and/or arrangements discussed. In addition, the present application provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize the application of other processes and/or the use of other materials.
Referring to fig. 1 to 3, an embodiment of the present application provides a TFT array substrate, including:
a substrate 1;
a first electrode layer 2, the first electrode layer 2 including a first electrode trace 21 provided on the substrate 1;
a first insulating layer 3, wherein the first insulating layer 3 is disposed on the substrate 1 and the first electrode layer 2, and the first insulating layer 3 has a first via hole 31 exposing the first electrode trace 21;
the second electrode layer 4, the second electrode layer 4 includes a first lap joint electrode 41 disposed in the first via hole 31 and connected with the first electrode wire 21, and a first protection electrode 42 disposed on the first lap joint electrode 41;
a second insulating layer 5, the second insulating layer 5 being disposed on the second electrode layer 4 and the first insulating layer 3, the second insulating layer 5 having a second via hole 51 therein exposing the first guard electrode 42;
the third electrode layer 6, the third electrode layer 6 includes a second electrode trace 61 disposed in the second via hole 51 and connected to the first guard electrode 42.
It should be noted that, in the present application, the first electrode wire 21 is connected to the first guard electrode 42 and the first overlap electrode 41, and the second electrode wire 61 is connected to the first guard electrode 42, so as to implement overlap joint between the second electrode wire 61 and the first electrode wire 21, and compared with the prior art, the overlap joint distance between the second electrode wire 61 and the first electrode wire 21 can be reduced by directly overlapping the second electrode wire 61 and the first electrode wire 21. That is, in the prior art, the second electrode trace 61 is directly overlapped with the first electrode trace 21 by passing through the first via hole 31 and the second via hole 51, and then the overlapping distance between the second electrode trace 61 and the first electrode trace 21 is the sum of the depths of the first via hole 31 and the second via hole 51. The first lap joint electrode 41 passes through the first via hole 31 to lap joint the first electrode wire 21, the subsequent second electrode wire 61 passes through the second via hole 51 to lap joint the first lap joint electrode 41, the lap joint distance between the second electrode wire 61 and the first electrode wire 21 is equal to the depth of the second via hole 51, so that the lap joint distance between the second electrode wire 61 and the first electrode wire 21 is shortened, and the lap joint abnormality of the second electrode wire 61 and the first electrode wire 21 is avoided.
In addition, the first protection electrode 42 may be made of a corrosion-resistant material, so that the first overlap electrode 41 may be protected, and in the process of forming the second via hole 51 by the second insulating layer 5, the first protection electrode 42 may not only prevent over etching, i.e. the etching process of the second insulating layer 5 may stop at the first protection electrode 42, so as to avoid the first overlap electrode 41 from being etched, but also enable the second via hole 51 to be etched uniformly, so as to ensure that the second via hole 51 can expose the first protection electrode 42, and ensure overlap of the second electrode trace 61 and the first protection electrode 42, so as to further avoid abnormal overlap of the second electrode trace 61 and the first electrode trace 21.
In addition, the second electrode trace 61, the first protection electrode 42, the first overlap electrode 41 and the first electrode trace 21 are all connected, so that the resistance of the second electrode trace 61 and the first electrode trace 21 can be further reduced, and the electrical performance of the TFT array substrate can be improved.
In some embodiments, the first via 31 and the second via 51 are each less deep than
In some embodiments, referring to fig. 1, the first electrode layer 2 further includes a light shielding layer 22 disposed on the substrate 1. The first insulating layer 3 further has a third via hole 32 exposing the light shielding layer 22. The second electrode layer 4 further includes a second landing electrode 43 disposed in the third via hole 32 and connected to the light shielding layer 22, and a second guard electrode 44 disposed on the second landing electrode 43. The second insulating layer 5 has a fourth via 52 therein exposing the second guard electrode 44. The third electrode layer 6 further includes a source electrode 62 disposed in the fourth via 52 and connected to the second guard electrode 44.
That is, the second overlap electrode 43 passes through the third via hole 32 to overlap the light shielding layer 22, the subsequent source electrode 62 passes through the fourth via hole 52 to overlap the second overlap electrode 43, which is equivalent to the overlapping distance between the source electrode 62 and the light shielding layer 22 being the depth of the fourth via hole 52, compared with the case that the source electrode 62 passes through the third via hole 32 and the fourth via hole 52 directly to overlap the light shielding layer 22, the overlapping distance between the source electrode 62 and the light shielding layer 22 is the sum of the depths of the third via hole 32 and the fourth via hole 52, which can reduce the overlapping distance between the source electrode 62 and the light shielding layer 22, thereby avoiding the abnormal overlapping between the source electrode 62 and the light shielding layer 22. And the second guard electrode 44 may be made of a corrosion-resistant material, so as to protect the second overlap electrode 43, and in the process of forming the fourth via hole 52 by the second insulating layer 5, the second guard electrode 44 not only can prevent over-etching, i.e. the etching process of the second insulating layer 5 will stop at the second guard electrode 44, so as to avoid the second overlap electrode 43 from being etched, but also can make the fourth via hole 52 etched uniformly, so as to ensure that the fourth via hole 52 can expose the second guard electrode 44, and ensure the overlap of the source electrode 62 and the second guard electrode 44, so as to further avoid the abnormal overlap of the source electrode 62 and the light shielding layer 22.
In addition, the light shielding layer 22 is disposed below the active layer 45 to generate a floating gate effect, i.e. the light shielding layer 22 is equivalent to a bottom gate, and the light shielding layer 22 is easily affected by voltages on other charged structure layers, so as to carry various voltages, so that the light shielding layer 22 has variable voltages, which causes the threshold voltage of the TFT array substrate to be continuously changed during operation, and causes the TFT array substrate to be unstable in operation. Therefore, the source electrode 62 is lapped with the light shielding layer 22, so that stable voltage can be generated on the light shielding layer 22, and floating gate effect is avoided, thereby effectively improving the working stability of the TFT array substrate.
In some embodiments, referring to fig. 1, the second electrode layer 4 further includes an active layer 45 disposed on the first insulating layer 3, and a third protection electrode 46 disposed on the active layer 45. The second insulating layer 5 further has a fifth via 53 therein exposing the third guard electrode 46. The third electrode layer 6 further includes a source electrode 62 disposed in the fifth via 53 and connected to the third guard electrode 46.
That is, the third protection electrode 46 may be made of a corrosion-resistant material, so that the active layer 45 may be protected, and in the process of forming the fifth via hole 53 in the second insulating layer 5, the third protection electrode 46 may not only prevent over-etching, that is, the etching process of the second insulating layer 5 may stop at the third protection electrode 46, so as to avoid the active layer 45 being etched, but also enable the fifth via hole 53 to be etched uniformly, so as to ensure that the fifth via hole 53 can expose the third protection electrode 46, so as to ensure that the source 62 and the active layer 45 overlap, and further avoid the source 62 and the active layer 45 from abnormal overlap.
In some embodiments, referring to fig. 1, the second electrode layer 4 further includes a fourth guard electrode 47 disposed on the active layer 45, and the fourth guard electrode 47 is spaced apart from the third guard electrode 46. The second insulating layer 5 further has a sixth via 54 therein exposing the fourth guard electrode 47. The third electrode layer 6 further includes a drain electrode 63 disposed in the sixth via 54 and connected to the fourth guard electrode 47.
That is, the fourth protection electrode 47 may be made of a corrosion-resistant material, so that the active layer 45 may be protected, and in the process of forming the sixth via hole 54 in the second insulating layer 5, the fourth protection electrode 47 may not only prevent over-etching, that is, the etching process of the second insulating layer 5 may stop at the fourth protection electrode 47, so as to avoid the active layer 45 being etched, but also enable the sixth via hole 54 to be etched uniformly, so as to ensure that the sixth via hole 54 can expose the fourth protection electrode 47, so as to ensure overlap of the drain electrode 63 and the active layer 45, and further avoid abnormal overlap of the drain electrode 63 and the active layer 45.
In this embodiment, the active layer 45 includes a channel region and source and drain contact regions located at both sides of the channel region, respectively. The third guard electrode 46 is located directly above the source contact region and the fourth guard electrode 47 is located directly above the drain contact region.
In this embodiment, referring to fig. 1, the tft array substrate further includes a third insulating layer 7 disposed between the active layer 45 and the second insulating layer 5, and a gate electrode 8 disposed between the third insulating layer 7 and the second insulating layer 5. That is, the third insulating layer 7 is located between the third guard electrode 46 and the fourth guard electrode 47, and the active layer 45, the gate electrode 8, the source electrode 62, and the drain electrode 63 constitute a TFT. The TFT is a top gate structure, and the gate electrode 8 may be located directly above the channel region of the active layer 45, so that the gate electrode 8 may block a portion of doped ions from entering the channel region of the active layer 45 during the conducting (i.e. ion doping) process of the active layer 45, so as to save the process.
In this embodiment, the light shielding layer 22 is located below the active layer 45, and the orthographic projection of the active layer 45 on the first insulating layer 3 is located in the orthographic projection of the light shielding layer 22 on the first insulating layer 3, so that the light shielding layer 22 completely shields the active layer 45, preventing the active layer 45 from being irradiated by external ambient light, avoiding the drift phenomenon of the threshold voltage of the TFT, and significantly improving the light stability of the TFT.
In addition, the area of the light shielding layer 22 may be larger than that of the active layer 45 to further improve the light shielding effect.
In this embodiment, the light shielding layer 22 may be a metal or alloy such as silver, molybdenum, aluminum, copper, chromium, tungsten, titanium, and tantalum, which can reflect light.
In some embodiments, the first guard electrode 42, the second guard electrode 44, the third guard electrode 46, and the fourth guard electrode 47 may each be molybdenum titanate (MoTi) or a molybdenum titanium alloy. Of course, the first guard electrode 42, the second guard electrode 44, the third guard electrode 46 and the fourth guard electrode 47 may be made of other corrosion-resistant materials, which are not limited herein.
In some embodiments, the active layer 45, the first landing electrode 41, and the second landing electrode 43 may be all Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), or Indium Gallium Zinc Oxide (IGZO). The first landing electrode 41 and the second landing electrode 43 may also be electrically conductive (i.e., ion doped) in order to improve the electrical properties of the first landing electrode 41 and the second landing electrode 43.
In some embodiments, the gate electrode 8, the first electrode trace 21, the second electrode trace 61, the source electrode 62, and the drain electrode 63 may be a combination of one or more of aluminum, aluminum alloy, copper alloy, titanium, and titanium alloy.
In some embodiments, the first electrode trace 21 and the second electrode trace 61 may be scan lines. Of course, the first electrode trace 21 and the second electrode trace 61 may be set as other signal traces, such as data lines, according to practical requirements, which is not limited herein.
Based on the TFT array substrate, the embodiment of the present application further provides an OLED display panel, including the TFT array substrate.
It should be noted that, the TFT array substrate connects the first guard electrode 42 and the first overlap electrode 41 through the first electrode trace 21, and then connects the first guard electrode 42 through the second electrode trace 61, so as to realize overlap joint between the second electrode trace 61 and the first electrode trace 21, and reduce the overlap joint distance between the second electrode trace 61 and the first electrode trace 21, thereby avoiding abnormal overlap joint between the second electrode trace 61 and the first electrode trace 21. In addition, the first protection electrode 42 may be made of a corrosion-resistant material, so that the first overlap electrode 41 may be protected, in the process of forming the second via hole 51 by the second insulating layer 5, the first protection electrode 42 may not only prevent over etching, i.e. the etching process of the second insulating layer 5 may stop at the first protection electrode 42, so as to avoid the first overlap electrode 41 from being etched, but also enable the second via hole 51 to be etched uniformly, so as to ensure that the second via hole 51 can expose the first protection electrode 42, so as to ensure overlap between the second electrode trace 61 and the first protection electrode 42, further avoid abnormal overlap between the second electrode trace 61 and the first electrode trace 21, and further improve the display effect of the OLED display panel.
The application of the OLED display panel in the embodiment of the present application is not particularly limited, and the OLED display panel may be any product or component with a display function, such as a television, a notebook computer, a tablet computer, a wearable display device (e.g., a smart bracelet, a smart watch, etc.), a mobile phone, a virtual reality device, an augmented reality device, a vehicle-mounted display, an advertisement light box, etc.
Referring to fig. 2 and fig. 3, based on the TFT array substrate described above, the embodiment of the present application further provides a method for manufacturing a TFT array substrate, including:
step S1, providing a substrate 1, and manufacturing a first electrode layer 2 on the substrate 1, wherein the first electrode layer 2 comprises a first electrode wire 21 arranged on the substrate 1;
step S2, manufacturing a first insulating layer 3 on the substrate 1 and the first electrode layer 2, and etching the first insulating layer 3 to form a first via hole 31 exposing the first electrode trace 21;
step S3, manufacturing a second electrode layer 4 on the first insulating layer 3, wherein the second electrode layer 4 comprises a first lap joint electrode 41 arranged in the first via hole 31 and connected with the first electrode wire 21, and a first protection electrode 42 arranged on the first lap joint electrode 41;
step S4, manufacturing a second insulating layer 5 on the second electrode layer 4 and the first insulating layer 3, and etching the second insulating layer 5 to form a second via hole 51 exposing the first protection electrode 42;
in step S5, a third electrode layer 6 is fabricated on the second insulating layer 5, where the third electrode layer 6 includes a second electrode trace 61 disposed in the second via 51 and connected to the first guard electrode 42.
It should be noted that, in the present application, the first electrode wire 21 is connected to the first guard electrode 42 and the first overlap electrode 41, and the second electrode wire 61 is connected to the first guard electrode 42, so as to implement overlap joint between the second electrode wire 61 and the first electrode wire 21, and compared with the prior art, the overlap joint distance between the second electrode wire 61 and the first electrode wire 21 can be reduced by directly overlapping the second electrode wire 61 and the first electrode wire 21. That is, in the prior art, the second electrode trace 61 is directly overlapped with the first electrode trace 21 by passing through the first via hole 31 and the second via hole 51, and then the overlapping distance between the second electrode trace 61 and the first electrode trace 21 is the sum of the depths of the first via hole 31 and the second via hole 51. The first lap joint electrode 41 passes through the first via hole 31 to lap joint the first electrode wire 21, the subsequent second electrode wire 61 passes through the second via hole 51 to lap joint the first lap joint electrode 41, the lap joint distance between the second electrode wire 61 and the first electrode wire 21 is equal to the depth of the second via hole 51, so that the lap joint distance between the second electrode wire 61 and the first electrode wire 21 is shortened, and the lap joint abnormality of the second electrode wire 61 and the first electrode wire 21 is avoided.
In addition, the first protection electrode 42 may be made of a corrosion-resistant material, so that the first overlap electrode 41 may be protected, and in the process of forming the second via hole 51 by the second insulating layer 5, the first protection electrode 42 may not only prevent over etching, i.e. the etching process of the second insulating layer 5 may stop at the first protection electrode 42, so as to avoid the first overlap electrode 41 from being etched, but also enable the second via hole 51 to be etched uniformly, so as to ensure that the second via hole 51 can expose the first protection electrode 42, and ensure overlap of the second electrode trace 61 and the first protection electrode 42, so as to further avoid abnormal overlap of the second electrode trace 61 and the first electrode trace 21.
In addition, the second electrode trace 61, the first protection electrode 42, the first overlap electrode 41 and the first electrode trace 21 are all connected, so that the resistance of the second electrode trace 61 and the first electrode trace 21 can be further reduced, and the electrical performance of the TFT array substrate can be improved.
In some embodiments, referring to fig. 3, the first electrode layer 2 further includes a light shielding layer 22 disposed on the substrate 1. The first insulating layer 3 further has a third via hole 32 exposing the light shielding layer 22. The second electrode layer 4 further includes a second landing electrode 43 disposed in the third via hole 32 and connected to the light shielding layer 22, and a second guard electrode 44 disposed on the second landing electrode 43. The second insulating layer 5 has a fourth via 52 therein exposing the second guard electrode 44. The third electrode layer 6 further includes a source electrode 62 disposed in the fourth via 52 and connected to the second guard electrode 44.
That is, the second overlap electrode 43 passes through the third via hole 32 to overlap the light shielding layer 22, the subsequent source electrode 62 passes through the fourth via hole 52 to overlap the second overlap electrode 43, which is equivalent to the overlapping distance between the source electrode 62 and the light shielding layer 22 being the depth of the fourth via hole 52, compared with the case that the source electrode 62 passes through the third via hole 32 and the fourth via hole 52 directly to overlap the light shielding layer 22, the overlapping distance between the source electrode 62 and the light shielding layer 22 is the sum of the depths of the third via hole 32 and the fourth via hole 52, which can reduce the overlapping distance between the source electrode 62 and the light shielding layer 22, thereby avoiding the abnormal overlapping between the source electrode 62 and the light shielding layer 22. And the second guard electrode 44 may be made of a corrosion-resistant material, so as to protect the second overlap electrode 43, and in the process of forming the fourth via hole 52 by the second insulating layer 5, the second guard electrode 44 not only can prevent over-etching, i.e. the etching process of the second insulating layer 5 will stop at the second guard electrode 44, so as to avoid the second overlap electrode 43 from being etched, but also can make the fourth via hole 52 etched uniformly, so as to ensure that the fourth via hole 52 can expose the second guard electrode 44, and ensure the overlap of the source electrode 62 and the second guard electrode 44, so as to further avoid the abnormal overlap of the source electrode 62 and the light shielding layer 22.
In addition, the light shielding layer 22 is disposed below the active layer 45 to generate a floating gate effect, i.e. the light shielding layer 22 is equivalent to a bottom gate, and the light shielding layer 22 is easily affected by voltages on other charged structure layers, so as to carry various voltages, so that the light shielding layer 22 has variable voltages, which causes the threshold voltage of the TFT array substrate to be continuously changed during operation, and causes the TFT array substrate to be unstable in operation. Therefore, the source electrode 62 is lapped with the light shielding layer 22, so that stable voltage can be generated on the light shielding layer 22, and floating gate effect is avoided, thereby effectively improving the working stability of the TFT array substrate.
In this embodiment, referring to fig. 3, in step S2, the first insulating layer 3 is etched, and a first via hole 31 exposing the first electrode trace 21 and a third via hole 32 exposing the light shielding layer 22 are formed.
In some embodiments, referring to fig. 3, the second electrode layer 4 further includes an active layer 45 disposed on the first insulating layer 3, and a third protection electrode 46 disposed on the active layer 45. The second insulating layer 5 further has a fifth via 53 therein exposing the third guard electrode 46. The third electrode layer 6 further includes a source electrode 62 disposed in the fifth via 53 and connected to the third guard electrode 46.
That is, the third protection electrode 46 may be made of a corrosion-resistant material, so that the active layer 45 may be protected, and in the process of forming the fifth via hole 53 in the second insulating layer 5, the third protection electrode 46 may not only prevent over-etching, that is, the etching process of the second insulating layer 5 may stop at the third protection electrode 46, so as to avoid the active layer 45 being etched, but also enable the fifth via hole 53 to be etched uniformly, so as to ensure that the fifth via hole 53 can expose the third protection electrode 46, so as to ensure that the source 62 and the active layer 45 overlap, and further avoid the source 62 and the active layer 45 from abnormal overlap.
In some embodiments, referring to fig. 3, the second electrode layer 4 further includes a fourth guard electrode 47 disposed on the active layer 45, and the fourth guard electrode 47 is spaced apart from the third guard electrode 46. The second insulating layer 5 further has a sixth via 54 therein exposing the fourth guard electrode 47. The third electrode layer 6 further includes a drain electrode 63 disposed in the sixth via 54 and connected to the fourth guard electrode 47.
That is, the fourth protection electrode 47 may be made of a corrosion-resistant material, so that the active layer 45 may be protected, and in the process of forming the sixth via hole 54 in the second insulating layer 5, the fourth protection electrode 47 may not only prevent over-etching, that is, the etching process of the second insulating layer 5 may stop at the fourth protection electrode 47, so as to avoid the active layer 45 being etched, but also enable the sixth via hole 54 to be etched uniformly, so as to ensure that the sixth via hole 54 can expose the fourth protection electrode 47, so as to ensure overlap of the drain electrode 63 and the active layer 45, and further avoid abnormal overlap of the drain electrode 63 and the active layer 45.
In this embodiment, referring to fig. 3, in step S4, the second insulating layer 5 is etched, and a second via 51 exposing the first guard electrode 42, a fourth via 52 exposing the second guard electrode 44, a fifth via 53 exposing the third guard electrode 46, and a sixth via 54 exposing the fourth guard electrode 47 are simultaneously formed.
In some embodiments, referring to fig. 3, in step S3, the second electrode layer 4 is fabricated on the first insulating layer 3, including:
depositing a first material layer on the first insulating layer 3 and in the first and third vias 31 and 32, and patterning and electrically conducting the first material layer to form an active layer 45, a first landing electrode 41 and a second landing electrode 43;
a second material layer is deposited on the first insulating layer 3 and the first material layer, and the second material layer is patterned to form a first guard electrode 42, a second guard electrode 44, a third guard electrode 46, and a fourth guard electrode 47, so as to complete the fabrication of the second electrode layer 4.
In this embodiment, the first material layer may be indium tin oxide, indium zinc oxide, or indium gallium zinc oxide. The second material layer may be molybdenum titanate or molybdenum titanium alloy.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments. In the implementation, each unit or structure may be implemented as an independent entity, or may be implemented as the same entity or several entities in any combination, and the implementation of each unit or structure may be referred to the foregoing method embodiments and will not be repeated herein.
The TFT array substrate, the method for manufacturing the TFT array substrate, and the OLED display panel provided in the embodiments of the present application are described in detail above, and specific examples are applied to illustrate principles and implementations of the embodiments of the present application, where the description of the above embodiments is only for helping to understand the technical solutions and core ideas of the embodiments of the present application; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.
Claims (10)
1. A TFT array substrate, comprising:
a substrate;
the first electrode layer comprises a first electrode wire arranged on the substrate;
the first insulating layer is arranged on the substrate and the first electrode layer, and a first via hole exposing the first electrode wiring is formed in the first insulating layer;
the second electrode layer comprises a first lap joint electrode which is arranged in the first via hole and connected with the first electrode wire, and a first protection electrode which is arranged on the first lap joint electrode;
the second insulating layer is arranged on the second electrode layer and the first insulating layer, and a second via hole exposing the first protection electrode is formed in the second insulating layer;
the third electrode layer comprises a second electrode wire which is arranged in the second via hole and connected with the first protection electrode;
the first electrode wire and the shading layer are integrally formed, and the first electrode wire and the shading layer are made of opaque metal materials; the second electrode layer further comprises an active layer, the first lap joint electrode and the active layer are integrally formed, and are subjected to conductor treatment, and the material filling the first via hole is the same as the material of the active layer; and a third protection electrode and a fourth protection electrode are respectively arranged on the source electrode contact area and the drain electrode contact area of the active layer, and the third protection electrode, the fourth protection electrode and the first protection electrode are integrally formed and are all made of corrosion-resistant materials.
2. The TFT array substrate of claim 1, wherein,
the first insulating layer is also provided with a third via hole exposing the shading layer;
the second electrode layer also comprises a second lap electrode which is arranged in the third via hole and connected with the shading layer, and a second protection electrode which is arranged on the second lap electrode;
the second insulating layer is provided with a fourth via hole exposing the second protective electrode;
the third electrode layer further comprises a source electrode which is arranged in the fourth via hole and connected with the second protection electrode.
3. The TFT array substrate of claim 1, wherein,
the second insulating layer is also provided with a fifth via hole exposing the third protective electrode;
the third electrode layer further comprises a source electrode which is arranged in the fifth via hole and connected with the third protection electrode.
4. The TFT array substrate as set forth in claim 3, wherein the second insulating layer further has a sixth via hole therein exposing the fourth guard electrode;
the third electrode layer further comprises a drain electrode which is arranged in the sixth via hole and connected with the fourth protection electrode.
5. The TFT array substrate as set forth in claim 3 further comprising a third insulating layer disposed between the active layer and the second insulating layer, and a gate electrode disposed between the third insulating layer and the second insulating layer.
6. An OLED display panel, comprising: the TFT array substrate as set forth in any one of claims 1 to 5.
7. The manufacturing method of the TFT array substrate is characterized by comprising the following steps:
providing a substrate, and manufacturing a first electrode layer on the substrate, wherein the first electrode layer comprises a first electrode wiring arranged on the substrate;
manufacturing a first insulating layer on the substrate and the first electrode layer, and etching the first insulating layer to form a first via hole exposing the first electrode wiring;
manufacturing a second electrode layer on the first insulating layer, wherein the second electrode layer comprises a first lap joint electrode which is arranged in the first via hole and connected with the first electrode wire, and a first protection electrode which is arranged on the first lap joint electrode;
manufacturing a second insulating layer on the second electrode layer and the first insulating layer, and etching the second insulating layer to form a second via hole exposing the first protection electrode;
manufacturing a third electrode layer on the second insulating layer, wherein the third electrode layer comprises a second electrode wire which is arranged in the second via hole and connected with the first protection electrode;
the first electrode wire and the shading layer are integrally formed, and the first electrode wire and the shading layer are made of opaque metal materials; the second electrode layer further comprises an active layer, the first lap joint electrode and the active layer are integrally formed, and are subjected to conductor treatment, and the material filling the first via hole is the same as the material of the active layer; and a third protection electrode and a fourth protection electrode are respectively arranged on the source electrode contact area and the drain electrode contact area of the active layer, and the third protection electrode, the fourth protection electrode and the first protection electrode are integrally formed and are all made of corrosion-resistant materials.
8. The method of manufacturing a TFT array substrate as set forth in claim 7, wherein the first insulating layer further has a third via hole therein exposing the light shielding layer;
the second electrode layer also comprises a second lap electrode which is arranged in the third via hole and connected with the shading layer, and a second protection electrode which is arranged on the second lap electrode;
the second insulating layer is provided with a fourth via hole exposing the second protective electrode;
the third electrode layer further comprises a source electrode which is arranged in the fourth via hole and connected with the second protection electrode.
9. The method of manufacturing a TFT array substrate as set forth in claim 7, wherein the second insulating layer further has a fifth via hole exposing the third guard electrode;
the third electrode layer further comprises a source electrode which is arranged in the fifth via hole and connected with the third protection electrode.
10. The method of manufacturing a TFT array substrate as set forth in claim 9, wherein the second insulating layer further has a sixth via hole exposing the fourth guard electrode;
the third electrode layer further comprises a drain electrode which is arranged in the sixth via hole and connected with the fourth protection electrode.
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