CN114173492B - Through blind hole design method for detecting hole filling capability of circuit board - Google Patents
Through blind hole design method for detecting hole filling capability of circuit board Download PDFInfo
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- CN114173492B CN114173492B CN202111215222.1A CN202111215222A CN114173492B CN 114173492 B CN114173492 B CN 114173492B CN 202111215222 A CN202111215222 A CN 202111215222A CN 114173492 B CN114173492 B CN 114173492B
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000013461 design Methods 0.000 title claims abstract description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 41
- 229910052802 copper Inorganic materials 0.000 claims abstract description 41
- 239000010949 copper Substances 0.000 claims abstract description 41
- 238000007747 plating Methods 0.000 claims abstract description 38
- 238000005553 drilling Methods 0.000 claims abstract description 29
- 238000000151 deposition Methods 0.000 claims abstract description 17
- 238000009713 electroplating Methods 0.000 claims abstract description 13
- 238000012360 testing method Methods 0.000 claims abstract description 13
- 239000003292 glue Substances 0.000 claims abstract description 11
- 238000010030 laminating Methods 0.000 claims abstract description 8
- 238000001465 metallisation Methods 0.000 claims abstract description 8
- 230000007547 defect Effects 0.000 claims abstract description 7
- 238000003754 machining Methods 0.000 claims abstract description 6
- 238000012545 processing Methods 0.000 claims abstract description 6
- 230000002950 deficient Effects 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 37
- 238000000227 grinding Methods 0.000 claims description 16
- 239000011159 matrix material Substances 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 15
- 238000003475 lamination Methods 0.000 claims description 11
- 239000012792 core layer Substances 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 238000011161 development Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 239000011347 resin Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- 238000007599 discharging Methods 0.000 claims description 2
- 238000003892 spreading Methods 0.000 claims description 2
- 239000011148 porous material Substances 0.000 description 4
- 230000000737 periodic effect Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000009658 destructive testing Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0008—Apparatus or processes for manufacturing printed circuits for aligning or positioning of tools relative to the circuit board
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
- G01B21/00—Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant
- G01B21/02—Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant for measuring length, width, or thickness
- G01B21/08—Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant for measuring length, width, or thickness for measuring thickness
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
- G01B21/00—Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant
- G01B21/10—Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant for measuring diameters
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N1/00—Sampling; Preparing specimens for investigation
- G01N1/02—Devices for withdrawing samples
- G01N1/04—Devices for withdrawing samples in the solid state, e.g. by cutting
- G01N1/06—Devices for withdrawing samples in the solid state, e.g. by cutting providing a thin slice, e.g. microtome
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N1/00—Sampling; Preparing specimens for investigation
- G01N1/28—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q
- G01N1/286—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q involving mechanical work, e.g. chopping, disintegrating, compacting, homogenising
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
- G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0047—Drilling of holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/421—Blind plated via connections
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N1/00—Sampling; Preparing specimens for investigation
- G01N1/28—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q
- G01N1/286—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q involving mechanical work, e.g. chopping, disintegrating, compacting, homogenising
- G01N2001/2873—Cutting or cleaving
Abstract
The invention discloses a through blind hole design method for detecting hole filling capability of a circuit board, which comprises the steps of selecting a core board layer, making no graph in a unit, and making a target of the next layer; laminating with prepreg, and drilling a target hole; aligning by using a target hole, processing a laser hole, and drilling a mechanical drilling alignment target; machining a mechanical through hole corresponding to the alignment target; removing glue and depositing copper on the plate, flash plating, and plating a copper layer to serve as a bottom layer of hole metallization; electroplating under the same conditions each time using a fixed current density; hole data are manufactured, the blind holes after hole filling are scanned, holes with poor hole filling are found out, and the reject ratio is calculated; slicing the defective blind holes, and counting the defect degree; slicing through holes with different specifications respectively, calculating copper thickness in the holes, and comparing different apertures. The hole filling capability of different blind hole sizes and the capability of through blind hole joint plating can be evaluated at one time when the hole filling capability is evaluated, and the problem of low test recognition degree is solved.
Description
Technical Field
The invention relates to the field of circuit board detection, in particular to a through blind hole design method for detecting hole filling capability of a circuit board.
Background
Currently, circuit boards are classified into three major categories, single-sided boards, double-sided boards, and multi-layer circuit boards, if they are classified by the number of layers. First, a single panel, on the most basic PCB, the parts are concentrated on one side and the wires are concentrated on the other side. Such a PCB is called a single-sided circuit board because the wires are present on only one side thereof. Single panel is generally simple to manufacture and low cost, but has the disadvantage of not being applicable to products that are too complex. The double panel is an extension of a single panel, and is used when a single wiring layer cannot meet the needs of the electronic product. The copper-clad wiring is arranged on both sides, and the wiring between the two layers can be conducted through the via hole so as to form the required network connection. The multi-layer board is a printed board having three or more conductive pattern layers laminated with insulating materials therebetween at a distance, and conductive patterns therebetween being interconnected as required. The multilayer circuit board is a product of electronic information technology which is developed in the directions of high speed, multifunction, large capacity, small volume, thin and light weight. Circuit board testing is becoming increasingly important to manufacturers as an important step in evaluating circuit board performance.
However, the existing test for hole-filling electroplating capability of circuit boards has the following defects:
in the prior art, slices are generally taken through destructive testing after electroplating for production line products, blind hole patterns and through hole copper thicknesses are checked, and whether the blind hole patterns and the through hole copper thicknesses are within a required range is confirmed. Although whether the process meets the requirements can be detected through product monitoring, the specification of the product is stable, the change of the potential process capability cannot be identified, and the test identification degree is low.
Disclosure of Invention
In order to overcome the defects of the prior art, one of the purposes of the invention is to provide a through blind hole design method for detecting the hole filling capability of a circuit board, which can solve the problem of low test recognition degree.
One of the purposes of the invention is realized by adopting the following technical scheme:
a design method for blind via holes for detecting hole filling capability of a circuit board comprises the following steps,
and (3) manufacturing a core plate layer: selecting a core plate layer, wherein no graph is formed in a unit, only laser holes provided for the outer layer are used as a chassis, and a dry film exposure, development and etching mode is adopted on the plate to form a target of the next layer;
and (3) laminating: laminating with a prepreg, and drilling a target hole in the lamination after treatment;
laser drilling: aligning by using a target hole, processing a laser hole, and drilling a mechanical drilling alignment target;
and (3) mechanical drilling: machining a mechanical through hole corresponding to the alignment target;
grinding: grinding the plate to smooth the surface;
removing glue, depositing copper and flash plating: removing glue and depositing copper on the plate, flash plating, and plating a copper layer to serve as a bottom layer of hole metallization;
hole filling electroplating step: electroplating under the same conditions each time using a fixed current density;
AOI scanning: hole data are manufactured, the blind holes after hole filling are scanned, holes with poor hole filling are found out, and the reject ratio is calculated;
the micro-slice manufacturing step comprises the following steps: slicing the defective blind holes, and counting the defect degree; slicing through holes with different specifications respectively, calculating copper thickness in the holes, and comparing different apertures.
Further, processing a through hole in a rectangular area by using a mechanical drill at the first position, and spreading 75um blind holes in the rectangular area according to the rules that the distance between the blind holes and the hole edges of the through hole is 0.2mm and the distance between the blind holes and the hole edges of the blind holes is 0.2 mm;
forming a second position below the first position, wherein the distance is more than 5mm, and arranging a plurality of blind hole BGA matrixes;
and forming a position III below the position II by more than 1.5mm, arranging a matrix of through holes, wherein the distance between the matrix spacing is at least 6mm, the distance between the hole edges of the through holes is 0.45mm, arranging a circle of outer through holes at the periphery of the matrix, wherein the distance between the hole edges of the outer through holes is 3mm, and the distance between the hole edges of the outer through holes to the matrix is at least 3mm, so as to form a complete through hole test unit, and pushing and discharging the matrix with the cutter diameters of 0.2mm,0.25mm,0.3mm,0.35mm and 4 mm.
Further, the first position, the second position and the third position are formed into a complete unit, and similarly, units of blind holes with other specifications are manufactured, and a complete set is formed.
Further, in the core layer manufacturing step, a 50mil thick, 10Z base copper plate was selected as the core layer.
Further, in the lamination step, 1080, 63% resin content prepreg was used for lamination.
Further, in the mechanical drilling step, whether the finish of the mechanical through hole meets the requirement is detected, if yes, a plate grinding step is executed, and if not, reworking is carried out.
Further, in the step of grinding the plate, detecting whether the surface after grinding meets the requirements, if so, executing the step of removing glue and depositing copper flash plating, and if not, reworking.
Further, in the step of removing the photoresist, depositing copper and flash plating, detecting whether the removal of the drilling dirt in the hole meets the requirement, if so, carrying out flash plating, and if not, carrying out reworking treatment.
Further, in the photoresist removing and copper depositing flash plating step, a copper layer of 5um is plated as a bottom layer of hole metallization.
Further, in the hole filling plating step, before plating, it is checked whether the conditions of each plating are the same.
Further, in the AOI scanning step, when scanning the blind hole after hole filling, a scanned image is stored.
Further, in the micro-slice manufacturing step, when the copper thickness in the hole is calculated and different pore diameters are compared, a copper thickness and pore diameter data table is established.
Compared with the prior art, the invention has the beneficial effects that:
making a target of the next layer on the plate by adopting a dry film exposure, development and etching mode; laminating with a prepreg, and drilling a target hole in the lamination after treatment; aligning by using a target hole, processing a laser hole, and drilling a mechanical drilling alignment target; machining a mechanical through hole corresponding to the alignment target; grinding the plate to smooth the surface; removing glue and depositing copper on the plate, flash plating, and plating a copper layer to serve as a bottom layer of hole metallization; electroplating under the same conditions each time using a fixed current density; hole data are manufactured, the blind holes after hole filling are scanned, holes with poor hole filling are found out, and the reject ratio is calculated; slicing the defective blind holes, and counting the defect degree; slicing through holes with different specifications respectively, calculating copper thickness in the holes, and comparing different apertures. Through the method, the hole filling capability of different blind hole sizes under different arrangement densities and the capability of through blind hole joint plating can be evaluated at one time when the hole filling capability is evaluated, the electroplating capability change of blind holes and through holes with different specifications in different periods can be mastered through periodic tests, and the problem of low test recognition degree is solved.
The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention, as well as the preferred embodiments thereof, together with the following detailed description of the invention, given by way of illustration only, together with the accompanying drawings.
Drawings
FIG. 1 is a flow chart of a blind via design method for detecting the hole filling capability of a circuit board according to a preferred embodiment of the present invention.
Detailed Description
The present invention will be further described with reference to the accompanying drawings and detailed description, wherein it is to be understood that, on the premise of no conflict, the following embodiments or technical features may be arbitrarily combined to form new embodiments.
It will be understood that when an element is referred to as being "fixed to" another element, it can be directly on the other element or intervening elements may also be present. When a component is considered to be "connected" to another component, it can be directly connected to the other component or intervening components may also be present. When an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
Referring to fig. 1, a blind via design method for detecting hole filling capability of a circuit board includes the following steps,
and (3) manufacturing a core plate layer: selecting a core plate layer, wherein no graph is formed in a unit, only laser holes provided for the outer layer are used as a chassis, and a dry film exposure, development and etching mode is adopted on the plate to form a target of the next layer; in the core layer manufacturing step, a 50mil thick 10Z base copper plate is selected as the core layer.
And (3) laminating: laminating with a prepreg, and drilling a target hole in the lamination after treatment; in the lamination step, 1080, 63% resin prepreg was used for lamination.
Laser drilling: aligning by using a target hole, processing a laser hole, and drilling a mechanical drilling alignment target;
and (3) mechanical drilling: machining a mechanical through hole corresponding to the alignment target; in the mechanical drilling step, detecting whether the finish of the mechanical through hole meets the requirement, if so, executing the plate grinding step, and if not, reworking.
Grinding: grinding the plate to smooth the surface; in the step of grinding the plate, detecting whether the surface after grinding meets the requirements, if so, executing the step of removing glue and depositing copper flash plating, and if not, reworking.
Removing glue, depositing copper and flash plating: removing glue and depositing copper on the plate, flash plating, and plating a copper layer to serve as a bottom layer of hole metallization; in the step of removing the photoresist, depositing copper and flash plating, detecting whether the removal of the drilling dirt in the hole meets the requirement, if so, carrying out flash plating, and if not, carrying out reworking treatment.
Preferably, in the photoresist removing and copper depositing flash plating step, a copper layer of 5um is plated as a bottom layer of hole metallization.
Hole filling electroplating step: electroplating under the same conditions each time using a fixed current density; in the hole filling plating step, before plating, it is checked whether the conditions of each plating are the same.
AOI scanning: hole data are manufactured, the blind holes after hole filling are scanned, holes with poor hole filling are found out, and the reject ratio is calculated; and in the AOI scanning step, when the blind holes after hole filling are scanned, storing a scanning image.
The micro-slice manufacturing step comprises the following steps: slicing the defective blind holes, and counting the defect degree; slicing through holes with different specifications respectively, calculating copper thickness in the holes, and comparing different apertures. In the micro-slice manufacturing step, when the copper thickness in the hole is calculated and different pore diameters are compared, a copper thickness and pore diameter data table is established. Through the method, the hole filling capability of different blind hole sizes under different arrangement densities and the capability of through blind hole joint plating can be evaluated at one time when the hole filling capability is evaluated, the electroplating capability change of blind holes and through holes with different specifications in different periods can be mastered through periodic tests, and the problem of low test recognition degree is solved.
Specifically, examples are as follows: different blind hole structures and through hole structures are designed on the outer layer of a 4L circuit board, holes and through holes are filled simultaneously during electroplating, and the current hole filling capacity and the through hole joint plating capacity are confirmed by evaluating the blank values of the blind holes with different designs and the copper thickness in the through holes after hole filling is completed. The periodic test can completely evaluate the current state of the production line by comparing the results of different periods. The specific design is as follows:
the core plate layer is fully paved with copper to provide a blind hole chassis for the outer layer, 1080 PP is adopted for lamination, the thickness of about 65um is formed, and laser drilling and mechanical drilling are carried out on the outer layer. Taking a 75um blind hole as an example:
position 1: through holes were drilled at four corners using a 2.1MM diameter mechanical drill in a rectangular area of 65mmx30 MM. Two through holes are drilled in the middle, and the specific positions of the 8 through holes are not limited. Wherein the edge distance of the two middle through holes is 0.5mm. In the rectangular area, blind holes of 75um are paved according to the rule that the distance between the blind holes and the hole edges of the through holes is 0.2mm and the distance between the blind holes and the hole edges of the blind holes is 0.2 mm. Wherein blind holes are required to be paved between the two middle through holes according to the same rule.
Position 2: under the position 1, the distance is more than 5mm, 5 blind hole BGA matrixes are arranged according to 15X15, the blind hole cutter diameter 75um, and the hole edges of the 5 blind hole matrixes are respectively 0.1mm,0.15mm,0.2mm,0.25mm and 0.3mm.
Position 3: a matrix of 5x10 through holes is arranged at a position above 1.5mm below the position 2, the diameter of the drill tip is 0.2mm, and the matrix is arranged according to 3x3 rows, and the matrix spacing is at least 6mm; the hole edge of the through hole is 0.45mm from hole edge to hole edge. And arranging a circle of through holes at the periphery of the 3X3 matrix, wherein the cutter diameter of the through holes is still 0.2mm, the hole edge is 3mm from hole edge to hole edge, and the hole edge is at least 3mm from hole edge to matrix, so as to form a complete through hole test unit. And so on, a matrix of 0.2mm,0.25mm,0.3mm,0.35mm,0.4mm drill tip diameters is discharged.
The above embodiments are only preferred embodiments of the present invention, and the scope of the present invention is not limited thereto, but any insubstantial changes and substitutions made by those skilled in the art on the basis of the present invention are intended to be within the scope of the present invention as claimed.
Claims (9)
1. A through blind hole design method for detecting hole filling capability of a circuit board is characterized by comprising the following steps:
and (3) manufacturing a core plate layer: selecting a core plate layer, wherein no graph is formed in a unit, only laser holes provided for the outer layer are used as a chassis, and a dry film exposure, development and etching mode is adopted on the plate to form a target of the next layer;
and (3) laminating: laminating with a prepreg, and drilling a target hole in the lamination after treatment;
laser drilling: aligning by using a target hole, processing a laser hole, and drilling a mechanical drilling alignment target;
and (3) mechanical drilling: machining a mechanical through hole corresponding to the alignment target;
grinding: grinding the plate to smooth the surface;
removing glue, depositing copper and flash plating: removing glue and depositing copper on the plate, flash plating, and plating a copper layer to serve as a bottom layer of hole metallization;
hole filling electroplating step: electroplating under the same conditions each time using a fixed current density;
AOI scanning: hole data are manufactured, the blind holes after hole filling are scanned, holes with poor hole filling are found out, and the reject ratio is calculated;
the micro-slice manufacturing step comprises the following steps: slicing the defective blind holes, and counting the defect degree; slicing through holes with different specifications respectively, calculating copper thickness in the holes, and comparing different apertures;
machining a through hole in a rectangular area by using a mechanical drill at the first position, and spreading 75um blind holes in the rectangular area according to the rules that the distance between the blind holes and the hole edges of the through hole is 0.2mm and the distance between the blind holes and the hole edges of the blind holes is 0.2 mm;
forming a second position below the first position, wherein the distance is more than 5mm, and arranging a plurality of blind hole BGA matrixes;
and forming a position III below the position II by more than 1.5mm, arranging a matrix of through holes, wherein the distance between the matrix spacing is at least 6mm, the distance between the hole edges of the through holes is 0.45mm, arranging a circle of outer through holes at the periphery of the matrix, wherein the distance between the hole edges of the outer through holes is 3mm, and the distance between the hole edges of the outer through holes to the matrix is at least 3mm, so as to form a complete through hole test unit, and pushing and discharging the matrix with the cutter diameters of 0.2mm,0.25mm,0.3mm,0.35mm and 0.4 mm.
2. The blind via design method for detecting hole filling capability of a circuit board according to claim 1, wherein: and forming a complete unit by the first position, the second position and the third position, and the like, manufacturing units of blind holes with other specifications, and forming a complete set.
3. The blind via design method for detecting hole filling capability of a circuit board according to claim 1, wherein: in the core layer manufacturing step, a 50mil thick 10Z base copper plate is selected as the core layer.
4. The blind via design method for detecting hole filling capability of a circuit board according to claim 1, wherein: in the lamination step, 1080, 63% resin prepreg was used for lamination.
5. The blind via design method for detecting hole filling capability of a circuit board according to claim 1, wherein: in the mechanical drilling step, detecting whether the finish of the mechanical through hole meets the requirement, if so, executing the plate grinding step, and if not, reworking.
6. The blind via design method for detecting hole filling capability of a circuit board according to claim 1, wherein: in the step of grinding the plate, detecting whether the surface after grinding meets the requirements, if so, executing the step of removing glue and depositing copper flash plating, and if not, reworking.
7. The blind via design method for detecting hole filling capability of a circuit board according to claim 1, wherein: in the step of removing the photoresist, depositing copper and flash plating, detecting whether the removal of the drilling dirt in the hole meets the requirement, if so, carrying out flash plating, and if not, carrying out reworking treatment.
8. The blind via design method for detecting hole filling capability of a circuit board according to claim 1, wherein: in the photoresist removing and copper depositing flash plating step, a copper layer with the thickness of 5um is plated as a bottom layer of hole metallization.
9. The blind via design method for detecting hole filling capability of a circuit board according to claim 1, wherein: in the hole filling plating step, before plating, it is checked whether the conditions of each plating are the same.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111215222.1A CN114173492B (en) | 2021-10-19 | 2021-10-19 | Through blind hole design method for detecting hole filling capability of circuit board |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111215222.1A CN114173492B (en) | 2021-10-19 | 2021-10-19 | Through blind hole design method for detecting hole filling capability of circuit board |
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| CN114173492A CN114173492A (en) | 2022-03-11 |
| CN114173492B true CN114173492B (en) | 2024-03-08 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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