CN114164003A - Etchant composition for display panel and etching method of display panel - Google Patents
Etchant composition for display panel and etching method of display panel Download PDFInfo
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- CN114164003A CN114164003A CN202111476051.8A CN202111476051A CN114164003A CN 114164003 A CN114164003 A CN 114164003A CN 202111476051 A CN202111476051 A CN 202111476051A CN 114164003 A CN114164003 A CN 114164003A
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- C—CHEMISTRY; METALLURGY
- C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
- C09K—MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
- C09K13/00—Etching, surface-brightening or pickling compositions
- C09K13/04—Etching, surface-brightening or pickling compositions containing an inorganic acid
- C09K13/08—Etching, surface-brightening or pickling compositions containing an inorganic acid containing a fluorine compound
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- C23F1/00—Etching metallic material by chemical means
- C23F1/02—Local etching
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- C23F1/00—Etching metallic material by chemical means
- C23F1/10—Etching compositions
- C23F1/14—Aqueous compositions
- C23F1/16—Acidic compositions
- C23F1/18—Acidic compositions for etching copper or alloys thereof
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- C23F1/00—Etching metallic material by chemical means
- C23F1/10—Etching compositions
- C23F1/14—Aqueous compositions
- C23F1/16—Acidic compositions
- C23F1/26—Acidic compositions for etching refractory metals
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Abstract
The present disclosure provides an etchant composition for a display panel and an etching method of a display panel. The etchant composition for a display panel includes: an etchant composition for a display panel is characterized by comprising the following raw materials in percentage by weight: 5 to 15 percent of hydrogen peroxide, 0.1 to 1 percent of etching inhibitor, 2 to 10 percent of etching additive, 1 to 5 percent of pH value regulator, 0.01 to 1.0 percent of fluoride and the balance of aqueous medium, and the etching agent composition can be used for simultaneously etching a metal layer in a display panel and a silicon-containing nonmetal layer adjacent to the metal layer.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to an etchant composition for a display panel and an etching method for a display panel.
Background
Displays such as Organic Light-Emitting Diode (OLED) displays and Liquid Crystal Displays (LCD) have been widely used in various electronic products such as personal computers, Liquid Crystal televisions, or mobile phones. In recent years, the demand for displays has increased, and the image quality and manufacturing cost of displays have been required to be higher.
Display panels in liquid crystal displays and organic light emitting diode displays typically include a Thin Film Transistor (TFT) matrix substrate. The TFT matrix substrate is provided with a plurality of scanning lines which are parallel to each other, a plurality of data lines which are parallel to each other, a plurality of thin film transistors and Pixel electrodes, wherein the scanning lines are vertical to the data lines, and a Pixel (Pixel) area can be defined between two adjacent scanning lines and two adjacent data lines. In the process of TFT matrix substrate, a plurality of photomasks and a suitable etching process are needed to perform a photolithography process (Photo-lithography), however, photomasks are expensive, and the larger the number of photomasks, the higher the process cost of TFT process is, and the more the process time and complexity are increased.
Disclosure of Invention
In order to solve the above technical problems, the present disclosure provides an etchant composition for a display panel and an etching method for a display panel, so as to solve the problems of the prior art.
According to some embodiments, the present disclosure provides an etchant composition for a display panel, including: an etchant composition for a display panel is characterized by comprising the following raw materials in percentage by weight: 5 to 15 percent of hydrogen peroxide, 0.1 to 1 percent of etching inhibitor, 2 to 10 percent of etching additive, 1 to 5 percent of pH value regulator, 0.01 to 1.0 percent of fluoride and the balance of aqueous medium, and the etching agent composition can be used for simultaneously etching a metal layer in a display panel and a silicon-containing nonmetal layer adjacent to the metal layer.
In certain embodiments, the aqueous medium is deionized water and the etch inhibitor is a heteroatom-containing species.
In some embodiments, the heteroatom-containing species is selected from the group consisting of thiophene, benzotriazole, hydroxy-benzotriazole, 5-amino-tetrazole, aminotetrazole, indole, purine, pyrimidine, 1, 3-thiazole, pyrrole, and mixtures thereof.
In certain embodiments, the etching additive is a mixture of at least two organic acids or two inorganic acids.
In certain embodiments, the organic acid of the etching additive is selected from the group consisting of malonic acid, succinic acid, tartaric acid, sulfanilic acid, sulfamic acid, succinic acid, malic acid, benzoic acid, citric acid, sulfosalicylic acid, alanine salicylate, glycine, arginine, and mixtures thereof, and the inorganic acid of the etching additive is selected from the group consisting of sulfuric acid, boric acid, phosphoric acid, and mixtures thereof.
In some embodiments, the pH adjusting agent is selected from the group consisting of sodium hydroxide, potassium hydroxide, ammonia, sulfuric acid, nitric acid, hydrochloric acid, and mixtures thereof, and the fluoride is selected from the group consisting of hydrofluoric acid, ammonium bifluoride, sodium fluoride, potassium fluoride, and mixtures thereof.
In certain embodiments, the etchant composition has a pH of 3 to 5.
In some embodiments, the present disclosure further provides a method for etching a display panel, comprising: providing a substrate on which a silicon-containing non-metal layer and a metal layer are sequentially formed; forming a patterned mask layer on the metal layer, wherein part of the silicon-containing nonmetal layer and the metal layer are exposed out of the patterned mask layer; and simultaneously etching the metal layer and the silicon-containing nonmetal layer exposed by the patterned mask layer using the etching solution composition according to any one of claims 1 to 7 using the patterned mask layer as a mask to form a patterned metal layer and a patterned silicon-containing nonmetal layer, wherein the patterned silicon-containing nonmetal layer has a step profile shape.
In some embodiments, the metal layer comprises a stack of a molybdenum metal layer and a copper metal layer, the molybdenum metal layer and the copper metal layer are formed by physical vapor deposition, chemical vapor deposition, electroplating or electroless plating, and the patterned mask layer is a photoresist.
In some embodiments, the metal layer and the silicon-containing nonmetal layer are etched at a temperature in a range of 30 ℃ to 35 ℃.
The beneficial effects of the disclosure are that the etchant composition for the display panel and the etching method of the display panel are provided, through the use of the etchant composition, the patterned semiconductor layer, the ohmic contact layer and the electrode layer in the thin film transistor can be formed by only one wet etching, and the method has the advantages of reducing the manufacturing cost and the manufacturing time of the thin film transistor, and further has the technical efficacy of optimizing the manufacturing process of the TFT matrix substrate.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic cross-sectional view of a display panel according to an embodiment of the disclosure.
Fig. 2 is a flowchart illustrating a method for manufacturing a display panel according to an embodiment of the disclosure.
Fig. 3 is a flowchart illustrating a method for manufacturing a display panel according to another embodiment of the disclosure.
FIG. 4 is a schematic partial cross-sectional view of a display panel etched with the etchant composition of the present disclosure.
Detailed Description
The following description of the various embodiments refers to the accompanying drawings, which illustrate specific embodiments in which the disclosure may be practiced. Directional phrases used in this disclosure, such as [ upper ], [ lower ], [ top ], [ bottom ], [ left ], [ right ], [ inner ], [ outer ], [ side ], etc., refer only to the directions of the attached drawings. Accordingly, the directional terms used are used for the purpose of illustration and understanding of the present disclosure, and are not used to limit the present disclosure. In the drawings, elements having similar structures are denoted by the same reference numerals.
Fig. 1 is a schematic cross-sectional view of a display panel 10 according to an embodiment of the disclosure. The display panel shown in fig. 1 is used in a display such as a liquid crystal display or an organic light emitting diode display, and functions as a Thin Film Transistor (TFT) matrix substrate, for example.
Referring to fig. 1, a display panel 10 includes a substrate 100 and a plurality of patterned films, such as a gate electrode 102, a gate insulating layer 104, a semiconductor layer 106, an ohmic contact layer 108, an electrode layer 110, and a protective layer 112, sequentially formed on the substrate 100. The gate electrode 102, the gate insulating layer 104, the semiconductor layer 106, the ohmic contact layer 108, the electrode layer 110, and the passivation layer 112 are patterned by forming a film, coating, exposing, etching, removing photoresist, and using different photo mask processes, and the gate electrode 102, the gate insulating layer 104, the semiconductor layer 106, the ohmic contact layer 108, and the electrode layer 110 are the main components of the thin film transistor, and the manufacturing method thereof is as follows.
Fig. 2 is a flowchart illustrating a method for manufacturing the display panel 10 according to an embodiment of the disclosure. The following describes the fabrication of the display panel 10 according to an embodiment of the disclosure with reference to fig. 1 and fig. 2.
As shown in fig. 1-2, in step S10, a first photo mask process (not shown) is performed to form a patterned gate 102.
In this step, a conductive layer is formed on the substrate 100. The substrate 100 is, for example, a quartz or glass substrate, the conductive layer is made of, for example, Al, Ag, Cu, Mo, Cr, W, Ta, Ti, metal nitride, or an alloy of any combination thereof, and may have a multi-layer structure of a heat-resistant metal film and a low resistivity film, for example, a double-layer structure of a molybdenum nitride film and an aluminum film. The conductive layer may then be patterned by a photolithography process (first masking process) in combination with a suitable wet etching process to form the patterned gate 102.
As shown in fig. 1-2, in step S20, a second photo mask process is performed to form a patterned photoresist layer (not shown) having different thickness structures and a trench on the gate insulating layer 104, the semiconductor layer 106, the ohmic contact layer 108 and the electrode layer 110.
In this step, a gate insulating layer 104, a semiconductor layer 106, an ohmic contact layer 108, an electrode layer 110 and a photoresist layer (not shown) are sequentially formed on the substrate 100 and the gate electrode 102. The gate insulating layer 104 is made of a silicon-containing non-metal layer such as silicon nitride (SiNx) or silicon oxide (SiOx), which is deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD). The material of the semiconductor layer 106 of the present embodiment is amorphous silicon (a-Si). The material of the ohmic contact layer 108 is formed of, for example, N + amorphous silicon (a-Si) heavily doped with N-type impurities (e.g., phosphorus) or silicide thereof, or is formed by In-situ (In-situ) deposition, for example. The electrode layer 110 is made of a stack of a molybdenum (Mo) metal layer and a copper (Cu) metal layer, wherein the Mo metal layer is formed on the ohmic contact layer 108 and the Cu metal layer is formed on the Mo metal layer. Next, a Multi-Tone Mask (MTM, not shown) is adjusted to form a patterned photoresist layer, so that the second photomask process may have different structure thicknesses and a channel, wherein the channel is formed above the gate electrode 102 and exposes the surface of the electrode layer 110. The multi-step adjusting Mask may be, for example, a Gray Tone Mask (GTM), a Stacked Layer Mask (SLM), or a Half Tone Mask (HTM). After the photolithography process is performed by adjusting the photo mask in the multi-step manner, the patterned photoresist layer forms structures with different thicknesses, and a portion of the photoresist layer above the gate 102 may be removed to form a channel. In the present embodiment, the gate insulating layer 104, the semiconductor layer 106 and the ohmic contact layer 108 are also referred to as a silicon-containing nonmetal layer a.
As shown in fig. 1-2, in step S30, a wet etching process and a dry etching process are sequentially performed to form the patterned semiconductor layer 106, the ohmic contact layer 108 and the electrode layer 110.
In this step, a wet etching process and a dry etching process may be sequentially performed on the semiconductor layer 106, the ohmic contact layer 108 and the electrode layer 110 by using the patterned photoresist layer (not shown) formed in step S20 as a photomask to remove portions of the ohmic contact layer 108 and the electrode layer 110 that are not covered by the ohmic contact layer 108 and the electrode layer 110 (particularly, portions located in the trench), and to remove portions of the surface of the semiconductor layer 106 that are not covered by the patterned photoresist layer (not shown). The wet etching process is used to remove the portion of the electrode layer 110 exposed by the patterned photoresist layer, and the dry etching process is used to remove the portion of the ohmic contact layer 108 and the semiconductor layer 106 exposed by the patterned photoresist layer. After the wet etching process and the dry etching process are completed, the patterned semiconductor layer 106, the ohmic contact layer 108 and the electrode layer 110 are formed, and the patterned electrode layers 110 on the two opposite sides of the channel are respectively used as a drain electrode and a source electrode.
As shown in fig. 1-2, in step S40, a third photo mask process is performed to form a patterned passivation layer 112.
In this step, after removing the patterned photoresist layer remaining in step S30, a passivation layer 112 is formed on the exposed surfaces of the gate insulating layer 104 and the patterned conductive layer 106, the ohmic contact layer 108 and the electrode layer 110, and the passivation layer 112 is patterned by a photolithography process (a third photolithography process) and a suitable dry etching process to form the patterned passivation layer 112. Here, a contact hole is formed in the patterned passivation layer 112, and a portion of the right patterned electrode layer 110 is exposed. The contact holes provide electrical connection paths between the patterned electrode layer 110 and a subsequently formed pixel electrode layer (not shown), thereby completing the fabrication of the thin film transistor on the substrate 100 of the display panel 10 of the present embodiment.
As can be seen from the above embodiments of the present disclosure, at least three photo-mask processes are used in combination with two dry etching processes and two wet etching processes to complete the fabrication of the thin film transistor on the substrate 100 of the display panel 10, which requires relatively high process cost and increased process time and complexity.
In view of this, the present disclosure provides a method for manufacturing a display panel, which, in combination with the use of the etching solution composition of the present disclosure, can omit at least one etching process compared with the method for manufacturing a display panel shown in fig. 2, thereby contributing to reduction of processing time and processing cost.
Referring to fig. 3, a flowchart of a method for manufacturing a display panel according to another embodiment of the disclosure is shown. The steps in the method for manufacturing the display panel of the embodiment shown in fig. 3 are substantially similar to those of the embodiment shown in fig. 2, and only the process differences between the two embodiments and the etchant composition applied in the present disclosure are further described herein.
As shown in fig. 3, after the steps S10 and S20 shown in fig. 2 are completed, a wet etching process is performed only once in step S30' to form the patterned semiconductor layer 106, the ohmic contact layer 108 and the electrode layer 110.
In this step, the patterned photoresist layer (not shown) formed in step S20 may be used as a photomask, and the etching solution composition of the present disclosure is used to perform a wet etching process on the semiconductor layer 106, the ohmic contact layer 108 and the electrode layer 110 only once, so as to remove the portions of the ohmic contact layer 108 and the electrode layer 110 that are not shielded by the ohmic contact layer 108 and the electrode layer 110 (particularly, the portions located in the trenches), and remove the portions of the surface of the semiconductor layer 106 that are not shielded by the patterned photoresist layer (not shown). The wet etching process may be used to remove the exposed portions of the electrode layer 110, the ohmic contact layer 108 and the semiconductor layer 106 from the patterned photoresist layer at one time. After the wet etching process is completed, the patterned semiconductor layer 106, the ohmic contact layer 108 and the electrode layer 110 are formed, and the patterned electrode layers 110 on the two opposite sides of the channel are respectively used as the drain electrode and the source electrode. Then, step S40 shown in fig. 2 may be continued, so that the fabrication of the thin film transistor on the substrate 100 of the display panel 10 shown in fig. 1 is completed by using three photo mask processes in combination with two dry etching operations and one wet etching operation. The manufacturing method of the display panel shown in fig. 3 is relatively economical compared to the manufacturing method of the display panel shown in fig. 2, and is helpful for reducing the complexity of the manufacturing process, and has the advantages of reducing the manufacturing cost and the manufacturing time of the thin film transistor.
In the present embodiment, the wet etching process is performed only once on the semiconductor layer 106, the ohmic contact layer 108 and the electrode layer 110. Since the material of the electrode layer 110 is usually composed of a stack of a molybdenum (Mo) metal layer and a copper (Cu) metal layer, the gate insulating layer 104, the semiconductor layer 106, and the ohmic contact layer 108 constitute the silicon-containing nonmetal layer a. Therefore, the wet etching composition used in the wet etching process is designed to etch the metal material such as molybdenum and copper in the electrode layer 110, and also has an etching capability for the silicon-containing nonmetal layer A.
In one embodiment, the etchant composition for simultaneously etching a metal layer and a silicon-containing nonmetal layer comprises: an etchant composition for a display panel is characterized by comprising the following raw materials in percentage by weight: 5 to 15 percent of hydrogen peroxide, 0.1 to 1 percent of etching inhibitor, 2 to 10 percent of etching additive, 1 to 5 percent of pH value regulator, 0.01 to 1.0 percent of fluoride and the balance of aqueous medium, and the etching agent composition can be used for simultaneously etching a metal layer in a display panel and a silicon-containing nonmetal layer adjacent to the metal layer.
In certain embodiments, the aqueous medium is deionized water and the etch inhibitor is a heteroatom-containing species.
In some embodiments, the heteroatom-containing species is selected from the group consisting of thiophene, benzotriazole, hydroxy-benzotriazole, 5-amino-tetrazole, aminotetrazole, indole, purine, pyrimidine, 1, 3-thiazole, pyrrole, and mixtures thereof.
In certain embodiments, the etching additive is a mixture of at least two organic acids or two inorganic acids.
In certain embodiments, the organic acid of the etching additive is selected from the group consisting of malonic acid, succinic acid, tartaric acid, sulfanilic acid, sulfamic acid, succinic acid, malic acid, benzoic acid, citric acid, sulfosalicylic acid, alanine salicylate, glycine, arginine, and mixtures thereof, and the inorganic acid of the etching additive is selected from the group consisting of sulfuric acid, boric acid, phosphoric acid, and mixtures thereof.
In some embodiments, the pH adjusting agent is selected from the group consisting of sodium hydroxide, potassium hydroxide, ammonia, sulfuric acid, nitric acid, hydrochloric acid, and mixtures thereof, and the fluoride is selected from the group consisting of hydrofluoric acid, ammonium bifluoride, sodium fluoride, potassium fluoride, and mixtures thereof.
In certain embodiments, the etchant composition has a pH of 3 to 5.
In the disclosure, the etching rate of the silicon-containing nonmetal layer of the thin film transistor can be adjusted by adjusting the fluorine content in the etching solution composition. Therefore, the fluorine content in the etching solution is adjusted according to the film thickness requirement of the silicon-containing nonmetal layer designed by the thin film transistor, so as to achieve the intended purpose of wet etching for the electrode layer 110 and dry etching for the silicon-containing nonmetal layer a disclosed in the embodiment of fig. 2 by a single wet etching process.
In brief, fig. 3 also discloses an etching method for a display panel, which includes the following steps: providing a substrate on which a silicon-containing non-metal layer and a metal layer are sequentially formed; forming a patterned mask layer on the metal layer, wherein part of the silicon-containing nonmetal layer and the metal layer are exposed out of the patterned mask layer; and using the patterned mask layer as a mask, and simultaneously etching the metal layer and the silicon-containing nonmetal layer exposed by the patterned mask layer by the etching solution composition to form a patterned metal layer and a patterned silicon-containing nonmetal layer, wherein the patterned silicon-containing nonmetal layer has a step profile shape.
In some embodiments, the metal layer comprises a stack of a molybdenum metal layer and a copper metal layer, the molybdenum metal layer and the copper metal layer are formed by physical vapor deposition, chemical vapor deposition, electroplating or electroless plating, and the patterned mask layer is a photoresist.
In some embodiments, the metal layer and the silicon-containing nonmetal layer are etched at a temperature in a range of 30 ℃ to 35 ℃.
Referring to fig. 4, a partial cross-sectional view of a display panel after etching with the etchant composition of the present disclosure is shown.
As shown in fig. 4, the structure of the non-metal layer a containing silicon, the electrode layer 110 and the patterned photoresist layer 200 substantially located on the substrate 100 adjacent to the gate 102 (not shown) is shown after performing the wet etching process 300 performed by the etching solution composition etching in the step S30' of the method for manufacturing the display panel of fig. 3. It is understood that the etching process 300 performed by the etching solution composition of the present disclosure may simultaneously etch the electrode layer 110 and the silicon-containing nonmetal layer a, wherein the etched silicon-containing nonmetal layer a has a step-like cross-sectional shape, the silicon-containing nonmetal layer a located below the electrode layer 110 has a thickness d, the silicon-containing nonmetal layer a after the wet etching process 300 has a thickness d1, and d1 is less than d.
The present invention will be described in more detail with reference to the following examples. These examples are for illustrative purposes only and do not limit the scope of the present invention.
[ examples 1 to 12]
In the following examples, the base solution was composed of the following raw materials in weight percent: the etching solution compositions of examples 1 to 12 of the present disclosure were prepared by adding different amounts of fluoride and water to the above base solution according to the following table 1 with 10% hydrogen peroxide, 0.2% hydroxybenzotriazole (etching inhibitor), 4% citric acid and 1% malonic acid (etching additive), and 0.2% sulfuric acid (pH adjuster).
TABLE 1
Next, after the test object including the electrode layer of the copper-molybdenum laminate and the silicon-containing nonmetal layer was etched at a temperature of 32 ℃ for 130 seconds using the etching solution compositions shown in the foregoing examples 1 to 12, the results of etching the electrode layer including the copper-molybdenum laminate and the silicon-containing metal layer were observed, as shown in table 2.
TABLE 2
The etch rate for the silicon-containing metal layer is V, as defined by the following formula (1):
(1)V＝(d-d1)/(130-EPD)。
in the etching process, the electrode layer is etched by the etching solution, after the silicon-containing nonmetal layer is exposed, the silicon nonmetal layer is etched, and the time from etching the electrode layer comprising the copper-molybdenum laminated layer to exposing the silicon nonmetal layer is defined as EPD.
Referring to tables 1 and 2, it can be seen that the etching effect of the silicon-containing nonmetal layer is the best when ammonium bifluoride is used as the fluoride in the etching solution composition in examples 1 to 4. In addition, as the fluoride content is increased as in examples 2 and 5-12, the etching rate of the silicon-containing nonmetal layer is increased. In addition, the etching solution compositions of the foregoing examples 1-12 showed good uniformity and stability in etching the electrode layer and the silicon-containing non-metal layer including the copper-molybdenum stack, and the etching deviation, the etching taper angle, and the etching rate of the silicon-containing metal layer shown in table 2 were all suitable for the process, thereby providing excellent step etching profile.
Although the present disclosure has been described with reference to the preferred embodiments, it is to be understood that the above description is not intended to limit the present disclosure, and that various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the present disclosure.
Claims (10)
1. An etchant composition for a display panel is characterized by comprising the following raw materials in percentage by weight: 5-15% of hydrogen peroxide, 0.1-1% of etching inhibitor, 2-10% of etching additive, 1-5% of pH value regulator, 0.01-1.0% of fluoride and the balance of aqueous medium, wherein the etching agent composition can simultaneously etch a metal layer in a display panel and a silicon-containing nonmetal layer adjacent to the metal layer.
2. The etchant composition for display panel according to claim 1, wherein the aqueous medium is deionized water and the etching inhibitor is a heteroatom-containing species.
3. The composition of claim 2, wherein the heteroatom-containing species is selected from the group consisting of thiophene, benzotriazole, hydroxy-benzotriazole, 5-amino-tetrazole, aminotetrazole, indole, purine, pyrimidine, 1, 3-thiazole, pyrrole, and mixtures thereof.
4. The etchant composition for display panel according to claim 1, wherein the etching additive is a mixture of at least two organic acids or two inorganic acids.
5. The etchant composition of claim 1 wherein the organic acid of the etching additive is selected from the group consisting of malonic acid, succinic acid, tartaric acid, sulfanilic acid, sulfamic acid, succinic acid, malic acid, benzoic acid, citric acid, sulfosalicylic acid, alanine salicylate, glycine, arginine and mixtures thereof, and the inorganic acid of the etching additive is selected from the group consisting of sulfuric acid, boric acid, phosphoric acid and mixtures thereof.
6. The etchant composition of claim 1, wherein the pH adjustor is selected from the group consisting of sodium hydroxide, potassium hydroxide, ammonia, sulfuric acid, nitric acid, hydrochloric acid and mixtures thereof, and the fluoride is selected from the group consisting of hydrofluoric acid, ammonium bifluoride, sodium fluoride, potassium fluoride and mixtures thereof.
7. The etchant composition for a display panel according to claim 1, wherein the etchant composition has a pH of 3 to 5.
8. A method for etching a display panel, comprising:
providing a substrate on which a silicon-containing non-metal layer and a metal layer are sequentially formed;
forming a patterned mask layer on the metal layer, wherein a part of the silicon-containing nonmetal layer and the metal layer are exposed out of the patterned mask layer; and
using the patterned mask layer as a mask, simultaneously etching the metal layer and the silicon-containing nonmetal layer exposed by the patterned mask layer by using the etching solution composition according to any one of claims 1 to 7 to form a patterned metal layer and a patterned silicon-containing nonmetal layer, wherein the patterned silicon-containing nonmetal layer has a step profile shape.
9. The method of claim 8, wherein the metal layer comprises a stack of a molybdenum metal layer and a copper metal layer, the molybdenum metal layer and the copper metal layer are formed by physical vapor deposition, chemical vapor deposition, electroplating, or electroless plating, and the patterned mask layer is a photoresist.
10. The etching method of claim 8, wherein the metal layer and the silicon-containing nonmetal layer are etched at a temperature ranging from 30 ℃ to 35 ℃.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024087174A1 (en) * | 2022-10-28 | 2024-05-02 | 京东方科技集团股份有限公司 | Thin film transistor device and manufacturing method therefor, compound etching solution, and array substrate |
Citations (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1884618A (en) * | 2005-06-22 | 2006-12-27 | 三星电子株式会社 | Etchant, method for fabricating interconnection line using the etchant, and method for fabricating thin film transistor substrate using the etchant |
| CN102472938A (en) * | 2009-07-23 | 2012-05-23 | 东友Fine-Chem股份有限公司 | Method for fabricating an array substrate for a liquid crystal display device |
| CN102576170A (en) * | 2009-08-20 | 2012-07-11 | 东友Fine-Chem股份有限公司 | Method of fabricating array substrate for liquid crystal display |
| TW201307972A (en) * | 2011-08-04 | 2013-02-16 | Dongwoo Fine Chem Co Ltd | Manufacturing method of an array substrate for liquid crystal display, method of forming a wiring, etching agent composition used for the multi-layer film and array substrate for liquid crystal display |
| CN103026293A (en) * | 2010-07-30 | 2013-04-03 | 东友Fine-Chem股份有限公司 | Method for producing an array substrate for a liquid crystal display device |
| KR20140082420A (en) * | 2012-12-24 | 2014-07-02 | 동우 화인켐 주식회사 | Method of preparing array of thin film transistor |
| CN103924244A (en) * | 2013-01-14 | 2014-07-16 | 易安爱富科技有限公司 | Etching Liquid Composition Of Copper/molybdenum Film Or Copper/molybdenum Alloy Film |
| CN104018159A (en) * | 2013-02-28 | 2014-09-03 | 东友精细化工有限公司 | Etching solution composition for copper-based metal layer and laminated film of copper-based metal layer and metal oxide layer, and method for preparing metal wiring |
| CN104233299A (en) * | 2013-06-17 | 2014-12-24 | 株式会社Adeka | Etching liquid composition and etching method |
| KR20150053212A (en) * | 2013-11-07 | 2015-05-15 | 솔브레인 주식회사 | Composition for etching, and method for preparing semiconductor device using the same |
| CN104838040A (en) * | 2012-12-18 | 2015-08-12 | 东进世美肯株式会社 | Metal-film etching-solution composition and etching method using same |
| CN105970223A (en) * | 2015-03-12 | 2016-09-28 | 东友精细化工有限公司 | Etchant composition and manufacturing method of array substrate for liquid crystal display |
| KR20160116943A (en) * | 2015-03-31 | 2016-10-10 | 동우 화인켐 주식회사 | Etchant composition for copper-containing metal layer and preparing method of an array substrate for liquid crystal display using same |
| KR20170011585A (en) * | 2015-07-23 | 2017-02-02 | 동우 화인켐 주식회사 | Etchant composition for copper-containing metal layer and preparing method of an array substrate for liquid crystal display using same |
| KR20170011586A (en) * | 2015-07-23 | 2017-02-02 | 동우 화인켐 주식회사 | Etchant composition for copper-containing metal layer and preparing method of an array substrate for liquid crystal display using same |
| KR20170068328A (en) * | 2015-12-09 | 2017-06-19 | 솔브레인 주식회사 | Etchant composition, and method for etching |
| TW202035794A (en) * | 2019-03-20 | 2020-10-01 | 南韓商易安愛富科技有限公司 | Etching composition and etching method using the same |
| CN113278975A (en) * | 2021-05-10 | 2021-08-20 | Tcl华星光电技术有限公司 | Copper-molybdenum etchant composition, etching method of copper-molybdenum film and display panel |
-
2021
- 2021-12-06 CN CN202111476051.8A patent/CN114164003A/en active Pending
Patent Citations (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1884618A (en) * | 2005-06-22 | 2006-12-27 | 三星电子株式会社 | Etchant, method for fabricating interconnection line using the etchant, and method for fabricating thin film transistor substrate using the etchant |
| CN102472938A (en) * | 2009-07-23 | 2012-05-23 | 东友Fine-Chem股份有限公司 | Method for fabricating an array substrate for a liquid crystal display device |
| CN102576170A (en) * | 2009-08-20 | 2012-07-11 | 东友Fine-Chem股份有限公司 | Method of fabricating array substrate for liquid crystal display |
| CN103026293A (en) * | 2010-07-30 | 2013-04-03 | 东友Fine-Chem股份有限公司 | Method for producing an array substrate for a liquid crystal display device |
| TW201307972A (en) * | 2011-08-04 | 2013-02-16 | Dongwoo Fine Chem Co Ltd | Manufacturing method of an array substrate for liquid crystal display, method of forming a wiring, etching agent composition used for the multi-layer film and array substrate for liquid crystal display |
| CN104838040A (en) * | 2012-12-18 | 2015-08-12 | 东进世美肯株式会社 | Metal-film etching-solution composition and etching method using same |
| KR20140082420A (en) * | 2012-12-24 | 2014-07-02 | 동우 화인켐 주식회사 | Method of preparing array of thin film transistor |
| CN103924244A (en) * | 2013-01-14 | 2014-07-16 | 易安爱富科技有限公司 | Etching Liquid Composition Of Copper/molybdenum Film Or Copper/molybdenum Alloy Film |
| CN104018159A (en) * | 2013-02-28 | 2014-09-03 | 东友精细化工有限公司 | Etching solution composition for copper-based metal layer and laminated film of copper-based metal layer and metal oxide layer, and method for preparing metal wiring |
| CN104233299A (en) * | 2013-06-17 | 2014-12-24 | 株式会社Adeka | Etching liquid composition and etching method |
| KR20150053212A (en) * | 2013-11-07 | 2015-05-15 | 솔브레인 주식회사 | Composition for etching, and method for preparing semiconductor device using the same |
| CN105970223A (en) * | 2015-03-12 | 2016-09-28 | 东友精细化工有限公司 | Etchant composition and manufacturing method of array substrate for liquid crystal display |
| KR20160116943A (en) * | 2015-03-31 | 2016-10-10 | 동우 화인켐 주식회사 | Etchant composition for copper-containing metal layer and preparing method of an array substrate for liquid crystal display using same |
| KR20170011585A (en) * | 2015-07-23 | 2017-02-02 | 동우 화인켐 주식회사 | Etchant composition for copper-containing metal layer and preparing method of an array substrate for liquid crystal display using same |
| KR20170011586A (en) * | 2015-07-23 | 2017-02-02 | 동우 화인켐 주식회사 | Etchant composition for copper-containing metal layer and preparing method of an array substrate for liquid crystal display using same |
| KR20170068328A (en) * | 2015-12-09 | 2017-06-19 | 솔브레인 주식회사 | Etchant composition, and method for etching |
| TW202035794A (en) * | 2019-03-20 | 2020-10-01 | 南韓商易安愛富科技有限公司 | Etching composition and etching method using the same |
| CN113278975A (en) * | 2021-05-10 | 2021-08-20 | Tcl华星光电技术有限公司 | Copper-molybdenum etchant composition, etching method of copper-molybdenum film and display panel |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024087174A1 (en) * | 2022-10-28 | 2024-05-02 | 京东方科技集团股份有限公司 | Thin film transistor device and manufacturing method therefor, compound etching solution, and array substrate |
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