CN114141198A

CN114141198A - Scanning driving circuit, maintenance method thereof and display device

Info

Publication number: CN114141198A
Application number: CN202111486039.5A
Authority: CN
Inventors: 冯雪欢; 李永谦
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Priority date: 2021-12-07
Filing date: 2021-12-07
Publication date: 2022-03-04
Anticipated expiration: 2041-12-07
Also published as: CN114141198B

Abstract

The embodiment of the disclosure discloses a scanning driving circuit, a maintenance method thereof and a display device, relates to the technical field of display, and is used for avoiding a display picture of the display device from having periodic horizontal stripes. The scan driving circuit includes: the shift register comprises a plurality of clock signal lines extending along a first direction, a plurality of connecting lines extending along a second direction and a plurality of shift registers. One connecting line is electrically connected with one clock signal line. The shift register includes: and an output circuit. The output circuit is electrically connected with the clock signal terminal. The clock signal end is also electrically connected with the two connecting wires and is electrically connected with the two clock signal wires through the two connecting wires. The clock signals transmitted by the two clock signal lines electrically connected with the same shift register are the same. The sum of the resistances of two connecting lines electrically connected with different shift registers in any two shift registers differs by a first preset value. The scanning driving circuit, the maintenance method thereof and the display device provided by the embodiment of the disclosure are used for image display.

Description

Scanning driving circuit, maintenance method thereof and display device

Technical Field

The disclosure relates to the technical field of display, and in particular to a scan driving circuit, a maintenance method thereof and a display device.

Background

Organic Light Emitting Diodes (OLEDs) have been widely used in the display field because of their advantages of self-luminescence, low driving voltage, high luminous efficiency, fast response speed, flexible display, etc.

The GOA (gate Driver On array) technology is a technology for integrating a gate driving circuit of a display device On a substrate, and the GOA technology can reduce the use amount of ICs, thereby reducing the production cost and power consumption of the display device, and can also realize the narrow frame of the display device.

Disclosure of Invention

An object of the present disclosure is to provide a scan driving circuit, a method for maintaining the same, and a display device, which are used to avoid the occurrence of horizontal stripes in a display screen.

In order to achieve the above purpose, the embodiments of the present disclosure provide the following technical solutions:

in one aspect, a scan driving circuit is provided. The scan driving circuit includes: the shift register includes a plurality of clock signal lines extending in a first direction, a plurality of connection lines extending in a second direction, and a plurality of shift registers. One of the connection lines is electrically connected to one of the clock signal lines. The shift register comprises an output circuit, and the output circuit is electrically connected with a clock signal end. The clock signal end is also electrically connected with the two connecting wires and is electrically connected with the two clock signal wires through the two connecting wires. And the clock signals transmitted by the two clock signal lines electrically connected with the same shift register are the same. In any two of the shift registers, the difference between the sum of the resistances of the two connecting lines electrically connected with different shift registers is a first preset value.

Therefore, in the scan driving circuit provided in some embodiments of the present disclosure, the clock signal end of the output circuit included in each shift register is electrically connected to the two connection lines and is electrically connected to the two clock signal lines through the two connection lines, and the clock signals transmitted by the two clock signal lines electrically connected to the same shift register are the same, so that each shift register can be guaranteed to receive a stable clock signal, and by making the sum of the resistances of the two connection lines electrically connected to different shift registers in any two of the shift registers differ by a first predetermined value, it can be guaranteed that the resistance conditions of the clock signals are substantially the same in the process of transmitting the clock signals to different shift registers, so that the falling edges of the clock signals received by the output circuits of different shift registers are substantially the same, and thus when the output circuits of different shift registers are turned on, the falling edges of the scanning signals output by each row of shift registers can be guaranteed to be basically the same, and further it is guaranteed that when the scanning driving circuit is applied to the display device, the potential variation of the data nodes of the pixel driving circuits of different rows is basically the same, so that the variation of Vgs of the pixel driving circuits of different rows is basically the same, the variation of the driving currents of the pixel driving circuits of different rows is basically the same, further the difference between the light-emitting brightness of the sub-pixels of different rows is smaller, and the display frame of the display device is prevented from generating horizontal stripes (for example, periodic horizontal stripes).

In some embodiments, the sum of the lengths of the two connecting lines electrically connected to different shift registers in any two shift registers differs by a second predetermined value.

In some embodiments, the output circuit is further electrically connected to a scan signal terminal. The scanning driving circuit is applied to a display device, and the display device comprises: a plurality of first gate lines extending along the second direction. The scanning signal terminal is also electrically connected with the end part of one first grid line.

In some embodiments, the shift register comprises: a first sub shift register and a second sub shift register. And the clock signal end of the output circuit of the first sub-shift register is electrically connected with one connecting wire. And the clock signal end of the output circuit of the second sub shift register is electrically connected with one connecting wire.

In some embodiments, the output circuit of the first sub-shift register is further electrically connected to a first scan signal terminal, and the output circuit of the second sub-shift register is further electrically connected to a second scan signal terminal. The scanning driving circuit is applied to a display device, and the display device comprises: a plurality of first gate lines and a plurality of second gate lines. The first scanning signal terminal is electrically connected with the end part of the first grid line. The second scanning signal terminal is electrically connected with the second grid line and is electrically connected with the first grid line at a position except two end parts through the second grid line.

In some embodiments, the second scan signal terminal is electrically connected to a central position of the first gate line through the second gate line.

In some embodiments, the display device includes a plurality of pixel driving circuits, the pixel driving circuits including: a plurality of transistors. The orthographic projection of the second grid lines on the plane where the display device is located and the orthographic projection of the transistors on the plane where the display device is located are not overlapped.

In some embodiments, a length of the connection line electrically connected to the output circuit of the first sub shift register is greater than a length of the connection line electrically connected to the output circuit of the second sub shift register.

In some embodiments, the plurality of clock signal lines comprises: a first clock signal line group and a second clock signal line group. The plurality of shift registers include: a plurality of shift register groups. The shift register group includes at least two shift registers. The two clock signal lines electrically connected with the same shift register are respectively positioned in the first clock signal line group and the second clock signal line group. The arrangement order of the clock signal lines in the first clock signal line group electrically connected with the at least two shift registers is opposite to the arrangement order of the clock signal lines in the second clock signal line group electrically connected with the at least two shift registers.

In some embodiments, the first set of clock signal lines includes six clock signal lines and the second set of clock signal lines includes six clock signal lines. The shift register group includes six shift registers. The first clock signal line and the twelfth clock signal line are electrically connected with the 6n-5 th shift register. And the second clock signal line and the eleventh clock signal line are electrically connected with the 6n-4 th shift register. And the third clock signal line and the tenth clock signal line are electrically connected with the 6n-3 shift registers. And the fourth clock signal line and the ninth clock signal line are electrically connected with the 6n-2 shift register. And the fifth clock signal line and the eighth clock signal line are electrically connected with the 6n-1 th shift register. And the sixth clock signal line and the seventh clock signal line are electrically connected with the 6 nth shift register. n is a positive integer.

In another aspect, a method for maintaining a scan driving circuit is provided, where the method is applied to the scan driving circuit according to any one of the above embodiments, and the scan driving circuit includes a plurality of clock signal lines, a plurality of connection lines, and a plurality of shift registers. The maintenance method comprises the following steps: and detecting the connecting line, and judging whether the connecting line and the clock signal line crossed with the connecting line are short-circuited or not. And under the condition of short circuit between the connecting line and the clock signal line crossed with the connecting line, cutting off a part of the connecting line, which is positioned between the shift register electrically connected with the connecting line and the clock signal line short-circuited with the connecting line, and a part of the connecting line, which is positioned between the clock signal line electrically connected with the connecting line and the clock signal line short-circuited with the connecting line.

In still another aspect, there is provided a display device including: at least one scan driver circuit as described in some of the embodiments above.

The scan driving circuit included in the display device provided in some embodiments of the present disclosure has the same structure and beneficial effects as the scan driving circuit provided in some embodiments described above, and is not described herein again.

In some embodiments, the display device includes: a plurality of first gate lines extending in a second direction. The number of the scanning driving circuits is two. The two scanning driving circuits are respectively positioned at two opposite sides of the plurality of first grid lines and are respectively and electrically connected with the plurality of first grid lines.

Drawings

In order to more clearly illustrate the technical solutions in the present disclosure, the drawings needed to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art according to the drawings. Furthermore, the drawings in the following description may be regarded as schematic diagrams, and do not limit the actual size of products, the actual flow of methods, the actual timing of signals, and the like, involved in the embodiments of the present disclosure.

Fig. 1 is a structural diagram of a scan driving circuit according to a related art;

FIG. 2 is a block diagram of a display device according to some embodiments of the present disclosure;

FIG. 3 is a block diagram of another display device in accordance with some embodiments of the present disclosure;

FIG. 4 is a block diagram of yet another display device in some embodiments according to the present disclosure;

FIG. 5 is a block diagram of a subpixel in some embodiments according to the present disclosure;

FIG. 6 is a timing diagram illustrating operation of a pixel driving circuit corresponding to the sub-pixel of FIG. 5 according to some embodiments of the present disclosure;

FIG. 7 is a block diagram of a scan driver circuit in accordance with some embodiments of the present disclosure;

FIG. 8 is a block diagram of another scan driver circuit in accordance with some embodiments of the present disclosure;

FIG. 9 is a block diagram of still another scan driver circuit in some embodiments according to the present disclosure;

FIG. 10 is a block diagram of still another scan driver circuit in some embodiments according to the present disclosure;

FIG. 11 is a block diagram of yet another display device in some embodiments according to the present disclosure;

FIG. 12 is a block diagram of still another scan driver circuit in some embodiments according to the present disclosure;

FIG. 13 is a block diagram of yet another display device in some embodiments according to the present disclosure;

FIG. 14 is a flow chart of a method of repairing a scan driver circuit according to some embodiments of the present disclosure;

FIG. 15 is a schematic diagram of a maintenance of a scan driver circuit according to some embodiments of the present disclosure;

FIG. 16 is a schematic maintenance diagram of another scan driver circuit according to some embodiments of the present disclosure;

FIG. 17 is a circuit diagram of a shift register according to some embodiments of the present disclosure;

fig. 18 is a circuit diagram of another shift register in some embodiments according to the present disclosure.

Detailed Description

Technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided by the present disclosure belong to the protection scope of the present disclosure.

Throughout the specification and claims, the term "comprising" is to be interpreted in an open, inclusive sense, i.e., as "including, but not limited to," unless the context requires otherwise. In the description herein, the terms "one embodiment," "some embodiments," "an example embodiment," "an example" or "some examples" or the like are intended to indicate that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, "a plurality" means two or more unless otherwise specified.

In describing some embodiments, the expression "connected" and its derivatives may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.

Additionally, the use of "based on" means open and inclusive, as a process, step, calculation, or other action that is "based on" one or more stated conditions or values may in practice be based on additional conditions or values beyond those stated.

Example embodiments are described herein with reference to cross-sectional and/or plan views as idealized example figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

The transistors used in the circuit provided in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics, and the thin film transistors are all taken as examples in the embodiments of the present disclosure for description.

In some embodiments, embodiments of the present disclosure provide circuits employing transistors having a first pole that is one of a source and a drain of the transistor and a second pole that is the other of the source and the drain of the transistor. Since the source and the drain of the transistor may be symmetrical in structure, the source and the drain thereof may not be different in structure, that is, the first and the second poles of the transistor in the embodiment of the present disclosure may not be different in structure. Illustratively, in the case where the transistor is a P-type transistor, the first pole of the transistor is the source and the second pole is the drain; illustratively, in the case where the transistor is an N-type transistor, the first pole of the transistor is the drain and the second pole is the source.

In the circuit provided by the embodiment of the present disclosure, "nodes" do not represent actually existing components, but represent junctions of relevant electrical connections in the circuit diagram, that is, the nodes are nodes equivalent to the junctions of relevant electrical connections in the circuit diagram.

In the circuit provided in the embodiment of the present disclosure, the transistors are all N-type transistors as an example.

Some embodiments of the present disclosure provide a display device 1000, as shown in fig. 2, the display device 1000 may be any device that displays text or images, whether in motion (e.g., video) or stationary (e.g., still images). More particularly, it is contemplated that the embodiments may be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile telephones, wireless devices, Personal Digital Assistants (PDAs), hand-held or portable computers, Global Positioning System (GPS) receivers/navigators, cameras, motion Picture Experts Group (MP 4) video players, video cameras, game consoles, wrist watches, clocks, calculators, television monitors, computer monitors, automobile displays (e.g., odometer display, etc.), navigators, cockpit controls and/or displays, displays of camera views (e.g., displays of rear view cameras in vehicles), electronic photographs, electronic billboards or signs, video game consoles, and the like, Projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images for a piece of jewelry), and the like.

In some examples, as shown in fig. 3 and 4, the display device 1000 has a display area a, and a peripheral area S disposed beside the display area a. Here, the "side" refers to one side, two sides, three sides, or a peripheral side of the display area a, that is, the peripheral area S may be located on one side, two sides, or three sides of the display area a, or the peripheral area S may be disposed around the display area a.

In some examples, as shown in fig. 3, the display apparatus 1000 includes: the display device includes a scan driving circuit 100, a plurality of first gate lines GL1, a plurality of data lines DL, and a plurality of sub-pixels P.

Illustratively, as shown in fig. 7, the scan driving circuit 100 includes: a plurality of shift registers 110. Each shift register 110 may include an output circuit 101, among other things. The output circuit 101 is electrically connected to a clock signal terminal CK and a scanning signal terminal GATE. When the output circuit 101 is turned on, the output circuit 101 may receive the clock signal transmitted from the clock signal terminal CK and output the clock signal as a scan signal from the scan signal terminal GATE.

For example, as shown in fig. 3, a plurality of first gate lines GL1, a plurality of data lines DL and a plurality of sub-pixels P may be located in the display area a, and the plurality of first gate lines GL1 may extend in the second direction X, and the plurality of data lines DL may extend in the first direction Y.

Here, the first direction Y and the second direction X intersect with each other. The included angle between the first direction Y and the second direction X can be set according to actual needs. Illustratively, the included angle between the first direction Y and the second direction X may be 85 °, 88 °, 90 °, 92 °, 95 °, or the like. The present disclosure is described taking an example in which the angle between the first direction Y and the second direction X is 90 °.

For example, as shown in fig. 5, each of the plurality of sub-pixels P may include a pixel driving circuit 200 and a light emitting device Q electrically connected to the pixel driving circuit 200.

For example, the plurality of pixel driving circuits 200 may be arranged in an array, that is, the plurality of pixel driving circuits 200 may be arranged in a plurality of rows along the first direction Y and a plurality of rows along the second direction X. Here, the pixel driving circuits 200 arranged in a row along the second direction X may be referred to as a same row of pixel driving circuits 200, and the pixel driving circuits 200 arranged in a row along the first direction Y may be referred to as a same column of pixel driving circuits 200. The same row of pixel driving circuits 200 may be electrically connected to at least one first gate line GL1, and the same column of pixel driving circuits 200 may be electrically connected to one data line DL. The number of the first gate lines GL1 electrically connected to the pixel driving circuit 200 in the same row may be set according to the structure of the pixel driving circuit 200. The present disclosure will be described by taking an example in which the pixel driving circuits 200 in the same row are electrically connected to a first gate line GL 1.

The structure of the pixel driving circuit 200 may include various structures, and may be selectively arranged according to actual needs. For example, the structure of the pixel driving circuit may include structures such as "3T 1C", "6T 1C", "7T 1C", "6T 2C" or "7T 2C". Here, "T" is represented as a transistor, the number located before "T" is represented as the number of transistors, "C" is represented as a storage capacitor, and the number located before "C" is represented as the number of storage capacitors.

The structure of the pixel driving circuit 200 will be schematically described below, taking as an example the structure of the pixel driving circuit 200 as 3T 1C.

In some examples, as shown in fig. 5, the pixel driving circuit 200 includes: a switching transistor M1, a driving transistor M2, a sensing transistor M3, and a storage capacitor Cst.

Illustratively, as shown in fig. 5, the gate of the switching transistor M1 is electrically connected to the first control signal terminal G1, the first pole of the switching transistor M1 is electrically connected to the DATA signal terminal DATA, and the second pole of the switching transistor M1 is electrically connected to the DATA node G. Wherein the switching transistor M1 is configured to be turned on under the control of the first control signal transmitted from the first control signal terminal G1, and to transmit the DATA signal received at the DATA signal terminal DATA to the DATA node G.

Illustratively, as shown in fig. 5, the gate electrode of the driving transistor M2 is electrically connected to the data node G, the first electrode of the driving transistor M2 is electrically connected to the first voltage signal terminal ELVDD, and the second electrode of the driving transistor M2 is electrically connected to the sensing node S. Wherein the driving transistor M2 is configured to be turned on under the control of the voltage of the data node G to supply the first voltage signal received at the first voltage signal terminal ELVDD to the sensing node S.

Illustratively, as shown in fig. 5, a first pole of the storage capacitor Cst is electrically connected to the data node G, and a second pole of the storage capacitor Cst is electrically connected to the sensing node S. The switching transistor M1 charges the storage capacitor Cst while charging the data node G.

Illustratively, as shown in fig. 5, the gate of the sensing transistor M3 is electrically connected to the second control signal terminal G2, the first pole of the sensing transistor M3 is electrically connected to the sensing signal terminal SENSE, and the second pole of the sensing transistor M3 is electrically connected to the sensing node S. The sensing transistor M3 is configured to detect an electrical characteristic of the sensing node S under control of the second control signal transmitted from the second control signal terminal G2 to implement external compensation, or to turn on under control of the second control signal to transmit a reset signal received at the sensing signal terminal SENSE to the sensing node S to reset the sensing node S. The above electrical characteristics include, for example, the threshold voltage and/or the carrier mobility of the driving transistor M2.

Illustratively, the light emitting device Q may be an OLED light emitting device.

For example, as shown in fig. 5, the anode of the light emitting device Q is electrically connected to the sensing node S, and the cathode of the light emitting device Q is electrically connected to the second voltage signal terminal ELVSS. The light emitting device Q is configured to emit light in cooperation with the first voltage signal from the sensing node S and the second voltage signal transmitted from the second voltage signal terminal ELVSS.

In the display period of one frame, the operation process of the pixel driving circuit 200 may include, for example, a blanking period and a driving period, and the blanking period may be used to obtain the threshold voltage of the driving transistor M2, and the detailed operation process of the blanking period is not described here. As shown in fig. 6, the driving phase may include, for example: a reset and data write phase t1 and a light-up phase t 2.

As shown in fig. 6, the reset and data write phase t1 can be divided into a reset phase (i) and a data write phase (ii).

In the reset phase, the first control signal is at a high level, the second control signal is at a high level, and the data signal is at a low level.

At this time, the switching transistor M1 is turned on under the control of the first control signal, transmits the data signal to the data node G, and resets the data node G. The sensing transistor M3 is turned on under the control of the second control signal, transmits a reset signal to the sensing node S, and resets the sensing node S.

In the second data writing stage, the first control signal is at a high level, the second control signal is at a high level, and the data signal is at a high level.

At this time, the switching transistor M1 is turned on under the control of the first control signal, transmits the data signal to the data node G, makes the voltage of the data node G at a high level, and charges the storage capacitor Cst. The sensing transistor M3 is turned on under the control of the second control signal to continue to reset the sensing node S.

As shown in fig. 6, in the light emitting period t2, the first control signal is at a low level, and the second control signal is at a low level.

At this time, the switching transistor M1 is turned off under the control of the first control signal, so that the storage capacitor Cst starts to discharge, and the potential of the data node G is maintained at a high potential. The driving transistor M2 is turned on under the control of the data node G, transmits the first voltage signal to the sensing node S, and makes the potential of the sensing node S raised, and the potential of the data node G is further raised due to the bootstrap action of the storage capacitor Cst, and maintains a high level for a period of time. In this way, the light emitting device Q is driven to emit light according to the first voltage signal from the sensing node S and the second voltage signal transmitted from the second voltage signal terminal ELVSS.

It should be noted that the driving current I for driving the light emitting device Q to emit light satisfies the formula:

wherein k is a fixed parameter, V_gsRepresenting the voltage difference, V, between the data node G and the sense node S_thRepresenting the threshold voltage of the drive transistor M2. The voltage of the data node G is the data signalThe data signal includes a threshold voltage. The voltage of the sensing node S is the voltage of the reset signal, and is usually constant. Therefore, the magnitude of the driving current I is mainly related to the voltage of the data node G.

Note that, in general, there is an overlapping portion between the first gate line GL1 and the switching transistor M1 in the orthographic projection of the display device 1000, as shown in fig. 5, which may cause a parasitic capacitance Ca between the first gate line GL1 and the switching transistor M1. In the light emission period t2, the potential of the first control signal changes from the high potential to the low potential in the previous period, and the potential change amount is Δ V. Due to the parasitic capacitance Ca, a coupling process exists between the parasitic capacitance Ca and the storage capacitor Cst during the process of changing the potential of the first control signal from a high potential to a low potential, so that the potential of the data node G generates a variation Δ Vp, wherein,

c denotes a capacitance magnitude of the storage capacitor Cst. In addition, the magnitude of Δ Vp is also affected by the falling edge time of the first control signal, and the larger the falling edge time of the first control signal, the larger Δ Vp. Accordingly, the larger the amount of change in the drive current I, the larger the difference between the actual light emission luminance and the expected light emission luminance of the light emitting device. The falling edge time of the first control signal is influenced by the resistance condition and the capacitance condition of the signal in the transmission process.

Illustratively, the scan signal terminal GATE of the output circuit 101 is electrically connected to the first GATE line GL1, and further may be electrically connected to the pixel driving circuit 200 through the first GATE line GL 1. The scan signal output by the output circuit 101 may be used as the first control signal received by the pixel driving circuit 200.

In the related art, as shown in fig. 1, a plurality of clock signal lines in the scan driving circuit 100 ' are disposed in the same layer and sequentially spaced along the second direction X ', so that different shift registers 110 ' and corresponding clock signal lines CLK ' need to be electrically connected through a connection line L '. Due to the different distances between any two adjacent shift registers 110 'and the corresponding clock signal lines CLK', the lengths of the connection lines L 'electrically connected to the any two adjacent shift registers 110' are different, and thus the resistances of the connection lines L 'electrically connected to the any two adjacent shift registers 110' are different. Therefore, the resistance conditions of the clock signals transmitted to the output circuits of any two adjacent shift registers 110 ' are different, which causes the falling edges of the clock signals received by the output circuits of any two adjacent shift registers 110 ' to be different, and further causes the falling edges of the scan signals output by the output circuits of any two adjacent shift registers 110 ' to be different.

In this way, the falling edges of the first control signals received by the pixel driving circuits 200 in any two adjacent rows are different, which causes the voltage change Δ Vp of the data node G of the pixel driving circuits 200 in any two adjacent rows to be inconsistent, so that the voltages of the data nodes G in the pixel driving circuits 200 in any two adjacent rows are different, and further the voltages V of the pixel driving circuits 200 in any two adjacent rows are different_gsIn contrast, the magnitude of the driving current I generated by the pixel driving circuit 200 in any two adjacent rows is different, so that the luminance of the sub-pixels in different rows in the display device is different.

Since the difference between the resistances of the connecting lines L' in different rows is gradually increased, after the difference is accumulated in a plurality of rows, the difference between the luminances of two rows of display frames with excessively large resistance difference is relatively large, and a boundary line caused by the luminance difference is generated at the boundary of the two rows of display frames, which finally causes horizontal streaks (e.g., periodic horizontal streaks) to appear in the display frame of the display device.

Based on this, in some examples of the present disclosure, as shown in fig. 7, in the shift register 110, the clock signal terminal CK of the output circuit 101 is electrically connected to the two connection lines L, and is electrically connected to the two clock signal lines CLK through the two connection lines L.

At this time, one shift register 110 is electrically connected to two connection lines L at the same time, and the two connection lines L transmit clock signals to the output circuits 101 of the shift register 110 at the same time. Further, when the output circuit 101 is turned on, the clock signal can be output as a scan signal.

Illustratively, the clock signals transmitted by the two clock signal lines CLK electrically connected to the same shift register 110 are the same. This ensures that the output circuit 101 of the shift register 110 receives a stable clock signal.

Illustratively, in any two shift registers, the sum of the resistances of two connecting lines L electrically connected to different shift registers 110 differs by a first predetermined value Δ R.

Wherein the first predetermined value Δ R may be 0 to a maximum value Δ R_MAXAny value in between.

For example, the minimum value of the first predetermined value Δ R is 0. That is, the sum of the resistances of the two connection lines L electrically connected to different shift registers 110 is the same.

For example, in the plurality of shift registers 110 included in the scan driver circuit 100, the sum of the resistances of two connection lines L electrically connected to a part of the shift registers 110 is different, where the maximum value is R1, and Δ R in this case_MAXMay be 20% of R1.

Therefore, it can be ensured that, in the process of transmitting the clock signals to different shift registers 110, the resistance conditions faced by the clock signals are substantially the same, so that the falling edges of the clock signals received by the output circuits 101 of different shift registers 110 are substantially the same, and thus, under the condition that the output circuits 101 of different shift registers 110 are turned on, the falling edge times of the scanning signals output by different shift registers 110 are substantially the same. When the scanning signal output by the scanning driving circuit 100 is used as the first control signal, it is ensured that the voltage variation Δ Vp of the data node G in the pixel driving circuits 200 in different rows is substantially the same, so that the variation of Vgs of the pixel driving circuits 200 in different rows is substantially the same, and further the variation of the driving current I of the pixel driving circuits 200 in different rows is substantially the same, and thus, a large difference between the light-emitting luminances of the sub-pixels P in different rows in the display device 1000 is avoided, and a horizontal stripe (for example, a periodic horizontal stripe) is avoided in a display screen of the display device 1000.

Thus, in the scan driving circuit 100 provided in some embodiments of the present disclosure, the clock signal terminal CK of the output circuit 101 included in each shift register 110 is electrically connected to two connection lines L and electrically connected to two clock signal lines CLK through the two connection lines L, and the clock signals transmitted by the two clock signal lines CLK electrically connected to the same shift register 110 are the same, so that each shift register 110 can receive a stable clock signal, and by making the sum of the resistances of the two connection lines L electrically connected to different shift registers 110 in any two shift registers 110 differ by the first predetermined value Δ R, it can be ensured that the resistance conditions encountered by the clock signals are substantially the same during the transmission of the clock signals to different shift registers 110, so that the falling edges of the clock signals received by the output circuits 101 of different shift registers 110 are substantially the same, therefore, when the output circuits 101 of different shift registers 110 are turned on, it is ensured that the falling edges of the scan signals output by each row of shift registers 110 are substantially the same, and further, when the scan driving circuit 100 is applied to the display device 1000, the potential variation of the data nodes G of the pixel driving circuits 200 in different rows is substantially the same, so that the variation of Vgs of the pixel driving circuits 200 in different rows is substantially the same, the variation Δ Vp of the driving current I of the pixel driving circuits 200 in different rows is substantially the same, and further, the difference between the light-emitting luminances of the sub-pixels P in different rows is small, thereby preventing horizontal stripes (e.g., periodic horizontal stripes) from appearing in the display screen of the display device 1000.

It will be appreciated that the resistance of the link line L is related to the resistivity of the material used for the link line L, the cross-sectional area S of the link line L and the length of the link line L. In the manufacturing process of the scan driving circuit 100, the plurality of connecting lines L are generally made of the same material and have the same cross-sectional area, so that the manufacturing process can be simplified.

Based on this, in some examples, the sum of the lengths of the two connection lines L electrically connected to different shift registers 110 in any two shift registers 110 differs by a second predetermined value Δ x.

Wherein the second predetermined value Δ x may be 0 to the maximumValue Δ x_MAXAny value in between.

For example, the minimum value of the second predetermined value Δ x is 0. That is, the sum of the lengths of the two connection lines L electrically connected to different shift registers 110 is the same.

For example, in the plurality of shift registers 110 included in the scan driver circuit 100, the sum of the lengths of two connection lines L electrically connected to a part of the shift registers 110 is different in size, where the maximum value is x 1. At this time,. DELTA.x_MAXMay be 20% of x 1.

Thus, under the condition that the materials and the cross-sectional areas S of the connecting lines L are the same, the sum of the lengths of the two connecting lines L electrically connected with different shift registers 110 is basically the same by reasonably arranging the clock signal lines CLK and the connecting lines L, and the sum of the resistances of the two connecting lines L electrically connected with different shift registers 110 can be ensured to be basically the same.

Illustratively, as shown in fig. 10, the lengths of the two connection lines L electrically connected to one shift register 110 in the scan driving circuit 100 are L1 and L2, respectively, and the lengths of the two connection lines L electrically connected to the other shift register 110 in the scan driving circuit 100 are L3 and L4, respectively, and the sum of the magnitudes of L1 and L2 differs from the sum of the magnitudes of L3 and L4 by a second predetermined value Δ x. It is further understood that this condition is satisfied between any two shift registers 110 in the scan driving circuit 100.

Illustratively, as shown in fig. 7, the pitches h between adjacent clock signal lines CLK are equal. This can simplify wiring.

Illustratively, as shown in fig. 7 to 13, the plurality of clock signal lines CLK includes: a first clock signal line group CLKA and a second clock signal line group CLKB. The first clock signal line group CLKA includes at least two clock signal lines CLK, and the second clock signal line group CLKB includes at least two clock signal lines CLK.

It is understood that the number of clock signal lines CLK included in the first clock signal line group CLKA and the number of clock signal lines CLK included in the second clock signal line group CLKB are related to the actual requirements of the scan driving circuit, and may be, for example: 2. 4, 6, 8, etc.

For example, as shown in fig. 7, the second clock signal group CLKB is closer to the plurality of shift registers 110 than the first clock signal group CLKA.

Illustratively, as shown in fig. 10, the plurality of shift registers 110 includes: a plurality of shift register groups 110A. The shift register group 110A includes at least two shift registers 110. Two clock signal lines CLK electrically connected to the same shift register 110 are respectively located in the first clock signal line group CLKA and the second clock signal line group CLKB.

It is understood that the number of shift registers 110 in the shift register group 110A, the number of clock signal lines CLK included in the first clock signal line group CLKA, and the number of clock signal lines CLK included in the second clock signal line group CLKB are the same.

Illustratively, as shown in fig. 8 and 9, the arrangement order of the clock signal lines CLK electrically connected to the at least two shift registers 110 in the first clock signal line group CLKA and the arrangement order of the clock signal lines CLK electrically connected to the at least two shift registers 110 in the second clock signal line group CLKB are reversed.

This ensures that the sum of the distances between the two clock signal lines CLK electrically connected to different shift registers 110 and the shift register 110 is substantially the same, and that the sum of the lengths of the two connection lines L electrically connected to different shift registers 110 is substantially the same.

For example, as shown in FIG. 8, the first clock signal group CLKA includes M clock signal lines CLK and is arranged along the second direction X in ascending order of 1, 2, 3 … M-2, M-1, M. The second clock signal group CLKB includes M clock signal lines CLK and is arranged in descending order M, M-1, M-2 … 3, 2, 1 along the second direction X.

For example, as shown in FIG. 9, the first clock signal group CLKA includes M clock signal lines CLK and is arranged along the second direction X in descending order of M, M-1, M-2 … 3, 2, 1. The second clock signal group CLKB includes M clock signal lines CLK and is arranged in ascending order of 1, 2, 3 … M-2, M-1, M along the second direction X.

It is to be understood that, when the first clock signal group CLKA includes M clock signal lines CLK arranged in an out-of-order along the second direction X, the M clock signal lines CLK included in the second clock signal group CLKB are arranged in an order opposite to the above-described out-of-order along the second direction X.

For example, as shown in fig. 10, the first clock signal line group CLKA includes six clock signal lines CLK, the second clock signal line group CLKB includes six clock signal lines CLK, and the shift register group includes six shift registers 110.

The first clock signal line and the twelfth clock signal line are electrically connected with the 6n-5 th shift register. And the second clock signal line and the eleventh clock signal line are electrically connected with the 6n-4 th shift register. And the third clock signal line and the tenth clock signal line are electrically connected with the 6n-3 shift registers. And the fourth clock signal line and the ninth clock signal line are electrically connected with the 6n-2 shift register. And the fifth clock signal line and the eighth clock signal line are electrically connected with the 6n-1 th shift register. And the sixth clock signal line and the seventh clock signal line are electrically connected with the 6 nth shift register. n is a positive integer.

It is to be understood that, as shown in fig. 10, a plurality of shift register groups 110A may share the first clock signal line group CLKA and the second clock signal line group CLKB. Here, n may represent the number of the shift register sets 110A, and may be specifically selected and set according to actual needs.

The present disclosure has various arrangements for the structure of the shift register 110 and the electrical connection with other structures, which can be selected according to actual needs.

In some examples, as shown in fig. 11, the scan signal terminal GATE of the output circuit 101 is also electrically connected to an end portion of one first GATE line GL 1.

The scan signal terminal GATE may output a scan signal, and the scan signal is transmitted along the first GATE line GL 1. In the case of using the scan signal as the first control signal, the scan signal terminal GATE of the output circuit 101 can control the on/off of the switching transistor M1 by supplying scan signals of different potentials to the GATE of the switching transistor M1 in different operations.

At this time, the entire circuit structure of the shift register 110 can refer to the structure in one example described below.

In some examples, as shown in fig. 17, the shift register 110 includes: an output circuit 101, a first input circuit 102, a first control circuit 103, a first reset circuit 104, a second reset circuit 105, a third reset circuit 106, a fourth reset circuit 107, and a fifth reset circuit 108.

Illustratively, as shown in fig. 17, the first output circuit 101 includes: a fourth transistor M4, a fifth transistor M5, and a first capacitor C1.

For example, the gate of the fourth transistor M4 is electrically connected to the first pull-up node Q1, the first pole of the fourth transistor M4 is electrically connected to the third control signal terminal CLKD _1, and the second pole of the fourth transistor M4 is electrically connected to the shift signal terminal CR.

For example, the GATE of the fifth transistor M5 is electrically connected to the first pull-up node Q1, the first pole of the fifth transistor M5 is electrically connected to the clock signal terminal CK, and the second pole of the fifth transistor M5 is electrically connected to the scan signal terminal GATE. Wherein the fifth transistor M5 is configured to be turned on under the control of the voltage of the first pull-up node Q1, and transmit the clock signal received at the clock signal terminal CK to the scan signal terminal GATE, so that the scan signal terminal GATE outputs the scan signal.

For example, a first terminal of the first capacitor C1 is electrically connected to the first pull-up node Q1, and a second terminal of the first capacitor C1 is electrically connected to the scan signal terminal GATE.

Illustratively, as shown in fig. 17, the first input circuit 102 includes a thirty-one transistor M31.

For example, the gate of the thirty-first transistor M31 is electrically connected to the input signal terminal Iput, the first pole of the thirty-first transistor M31 is electrically connected to the input signal terminal Iput, and the second pole of the thirty-first transistor M31 is electrically connected to the first pull-up node Q1.

Illustratively, as shown in fig. 17, the first control circuit 103 includes: a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10.

For example, the gate of the seventh transistor M7 is electrically connected to the third voltage signal terminal VDD _ a, the first pole of the seventh transistor M7 is electrically connected to the third voltage signal terminal VDD _ a, and the second pole of the seventh transistor M7 is electrically connected to the gate of the eighth transistor M8 and the first pole of the ninth transistor M9.

For example, a first pole of the eighth transistor M8 is electrically connected to the third voltage signal terminal VDD _ a, and a second pole of the eighth transistor M8 is electrically connected to the first pull-down node QB _ a and the first pole of the tenth transistor M10.

For example, the gate of the ninth transistor M9 is electrically connected to the first pull-up node Q1, and the second pole of the ninth transistor M9 is electrically connected to the fourth voltage signal terminal VGL 1. A gate of the tenth transistor M10 is electrically connected to the first pull-up node Q1, and a second pole of the tenth transistor M10 is electrically connected to the fourth voltage signal terminal VGL 1.

Illustratively, as shown in fig. 17, the first reset circuit 104 includes: the fifteenth transistor M15.

For example, the gate of the fifteenth transistor M15 is electrically connected to the input signal terminal Iput, the first pole of the fifteenth transistor M15 is electrically connected to the first pull-down node QB _ a, and the second pole of the fifteenth transistor M15 is electrically connected to the fourth voltage signal terminal VGL 1.

Illustratively, as shown in fig. 17, the second reset circuit 105 includes: a seventeenth transistor M17.

For example, the gate of the seventeenth transistor M17 is electrically connected to the first pull-down node QB _ a, the first pole of the seventeenth transistor M17 is electrically connected to the first pull-up node Q1, and the second pole of the seventeenth transistor M17 is electrically connected to the fourth voltage signal terminal VGL 1.

Illustratively, as shown in fig. 17, the third reset circuit 106 includes: an eighteenth transistor M18 and a twentieth transistor M20.

For example, the gate of the eighteenth transistor M18 is electrically connected to the first pull-down node QB _ a, the first pole of the eighteenth transistor M18 is electrically connected to the shift signal terminal CR, and the second pole of the eighteenth transistor M18 is electrically connected to the fourth voltage signal terminal VGL 1.

For example, the GATE of the twentieth transistor M20 is electrically connected to the first pull-down node QB _ a, the first pole of the twentieth transistor M20 is electrically connected to the scan signal terminal GATE, and the second pole of the twentieth transistor M20 is electrically connected to the fifth voltage signal terminal VGL 2.

Illustratively, as shown in fig. 17, the fourth reset circuit 107 includes: a twentieth transistor M22.

For example, the gate of the twentieth transistor M22 is electrically connected to the display reset signal terminal STD, the first pole of the twentieth transistor M22 is electrically connected to the first pull-up node Q1, and the second pole of the twentieth transistor M22 is electrically connected to the fourth voltage signal terminal VGL 1.

Illustratively, as shown in fig. 17, the fifth reset circuit 108 includes: a twenty-ninth transistor M29.

For example, a gate of the twenty-ninth transistor M29 is electrically connected to the global reset signal terminal TRST, a first pole of the twenty-ninth transistor M29 is electrically connected to the first pull-up node Q1, and a second pole of the twenty-ninth transistor M29 is electrically connected to the fourth voltage signal terminal VGL 1.

It should be noted that the structure of the shift register 110 in the above example is only a schematic description, and should not be construed as a limitation to the specific structure of the shift register 110 in the present disclosure.

In other examples, as shown in fig. 12, the shift register 110 includes: the first sub-shift register 110a and the second sub-shift register 110b, the clock signal terminal CK of the output circuit 101a of the first sub-shift register 110a is electrically connected to one connection line L, and the clock signal terminal CK of the output circuit 101b of the second sub-shift register 110b is electrically connected to one connection line L.

In this way, the clock signal terminal CK of the output circuit 101a of the first sub-shift register 110a may be electrically connected to one clock signal line CLK through one connection line L, and the clock signal terminal CK of the output circuit 101b of the second sub-shift register 110b may be electrically connected to one clock signal line CLK through one connection line L, at this time, the shift register 110 may still be electrically connected to two clock signal lines CLK at the same time, and at this time, the sum of the lengths of the two connection lines L electrically connected to different shift registers 110 is still equal, that is, in the case that the plurality of connection lines L use the same material and cross-sectional area S, the sum of the resistances of the two connection lines L is equal, and the beneficial effects mentioned in some embodiments above may still be achieved.

It is understood that the sum of the lengths of the connection lines L electrically connected to the output circuits 101a of the first sub-shift register 110a is different from the length of the connection lines L electrically connected to the output circuits 101b of the second sub-shift register 110 b.

Illustratively, the length of the connection line L electrically connected to the output circuit 101a of the first sub-shift register 110a is greater than the length of the connection line L electrically connected to the output circuit 101b of the second sub-shift register 110 b.

The relative position relationship between the first sub-shift register 110a and the second sub-shift register 110b is not limited in the present disclosure, and can be selectively set according to actual needs.

For example, as shown in fig. 12, the first sub shift register 110a and the second sub shift register 110b may be adjacently disposed in the second direction X.

As another example, the first sub shift register 110a and the second sub shift register 110b may be adjacently disposed along the first direction Y.

Illustratively, as shown in fig. 13 and 18, the output circuit 101a of the first sub-shift register 110a is further electrically connected to the first scan signal terminal GATE1, the output circuit 101b of the second sub-shift register 110b is further electrically connected to the second scan signal terminal GATE2, and the display device 1000 further includes: a plurality of second gate lines GL 2. The first scan signal terminal GATE1 is electrically connected to an end portion of the first GATE line GL1, and the second scan signal terminal GATE2 is electrically connected to the second GATE line GL2, and is electrically connected to the first GATE line GL1 through the second GATE line GL2 except for two end portions.

It is understood that, at this time, the scan signals received by the pixel driving circuits 200 in the same row are generated by the combination of the first scan signal output from the first scan signal terminal GATE1 of the first sub-shift register 110a and the second scan signal output from the second scan signal terminal GATE2 of the second sub-shift register 110 b.

The position of the first gate line GL1 other than the two end portions refers to a position between the two end portions in the first gate line GL 1.

For example, the second scan signal terminal GATE2 may be electrically connected to the first GATE line GL1 at the center position O through the second GATE line GL 2.

The center position O refers to a position of the first gate line GL1 at which the distances from the two end positions are equal.

Illustratively, the orthographic projection of the second gate lines GL2 on the plane of the display device 1000 is not overlapped with the orthographic projection of the transistors included in the pixel driving circuit 200 on the plane of the display device 1000.

This can prevent the parasitic capacitance from being generated between the second gate line GL2 and the transistor, and can also prevent the coupling between the parasitic capacitance and the storage capacitor Cst of the pixel driving circuit 200 during the light-emitting period t2, so as to reduce the capacitive reactance of the second scan signal during the transmission process along the second gate line GL2 and reduce the falling time of the second scan signal. Since the scan signal output by the shift register 110 is formed by the combined action of the first scan signal and the second scan signal, when the falling time of the second scan signal is reduced, the falling time of the scan signal received by the gate of the control transistor M1 can be reduced, and the turn-off time of the control transistor M1 can be further shortened.

Note that, when the display device 1000 adopts the double-end driving method, that is, the display device 1000 includes two scan driving circuits 100, both the two scan driving circuits 100 are electrically connected to the first gate line GL1, and the two scan driving circuits 100 simultaneously transmit scan signals to the first gate line GL 1. At this time, the positions of the first gate line GL1 other than the two end portions are distant from the shift register 110, that is, the time required for the positions of the first gate line GL1 other than the two end portions to receive the scan signal is long, that is, the falling time of the scan signal at the positions of the first gate line GL1 other than the two end portions is long.

By electrically connecting the second gate line GL2 to the first gate line GL1 at positions other than two end portions, and by making the orthographic projection of the second gate line GL2 on the plane of the display device 1000 not coincide with the orthographic projection of the plurality of transistors included in the pixel driving circuit 200 on the plane of the display device 1000, the second scanning signal can be transmitted to the first gate line GL1 at positions other than two end portions with less obstruction during transmission along the second gate line GL2, so that the falling time of the scanning signal at the first gate line GL1 at positions other than two end portions can be reduced.

It should be noted that, of the positions of the first gate line GL1 except for the two end portions, the center position O of the first gate line GL1 is the position at which the scanning signal is received at the latest, and by electrically connecting the second gate line GL2 to the center position O of the first gate line GL1, the falling edge time of the scanning signal at the center position of the first gate line GL1 can be effectively reduced.

At this time, the entire circuit structure of the shift register 110 can refer to the structure in the following example.

In some examples, the first sub-shift register 110a and the second sub-shift register 110b may each employ the structure of the shift register shown in the above examples.

In other examples, as shown in fig. 18, the structure of the first sub shift register 110a may refer to the circuit structure in one example described above, and the first sub shift register 110 is also electrically connected to the second pull-down node QB _ B of the second sub shift register.

For the sake of distinction, the scan signal terminal GATE electrically connected to the second pole of the fifth transistor M5 may be understood as the first scan signal terminal GATE1, and the output circuit of the first sub-shift register 110a is denoted by reference numeral 101 a.

Illustratively, as shown in fig. 18, the second reset circuit 105 further includes: a sixteenth transistor M16.

For example, as shown in fig. 18, the gate of the sixteenth transistor M16 is electrically connected to the second pull-down node QB _ B, the first pole of the sixteenth transistor M16 is connected to the first pull-up node Q1, and the second pole of the sixteenth transistor M16 is electrically connected to the fourth voltage signal terminal VGL 1.

Illustratively, as shown in fig. 18, the third reset circuit 106 further includes: a nineteenth transistor M19 and a twenty-first transistor M21.

For example, as shown in fig. 18, the gate of the nineteenth transistor M19 is electrically connected to the second pull-down node QB _ B, the first pole of the nineteenth transistor M19 is electrically connected to the shift signal terminal CR, and the second pole of the nineteenth transistor M19 is electrically connected to the fourth voltage signal terminal VGL 1.

For example, as shown in fig. 18, the GATE of the twenty-first transistor M21 is electrically connected to the second pull-down node QB _ B, the first pole of the twenty-first transistor M21 is electrically connected to the first scan signal terminal GATE1, and the second pole of the twenty-first transistor M21 is electrically connected to the fifth voltage signal terminal VGL 2.

The structure of the second sub-shift register 110b is schematically described below.

Illustratively, as shown in fig. 18, the second sub shift register 110b includes: an output circuit 101b, a second input circuit 202, a second control circuit 203, a sixth reset circuit 204, a seventh reset circuit 205, an eighth reset circuit 206, a ninth reset circuit 207, and a tenth reset circuit 208.

Illustratively, as shown in fig. 18, the output circuit 201 includes: a sixth transistor M6 and a second capacitor C2.

For example, as shown in fig. 18, the GATE of the sixth transistor M6 is electrically connected to the second pull-up node Q2, the first pole of the sixth transistor M6 is electrically connected to the clock signal terminal CK, and the second pole of the sixth transistor M6 is electrically connected to the second scan signal terminal GATE 2.

For example, as shown in fig. 18, a first terminal of the second capacitor C2 is electrically connected to the second pull-up node Q2, and a second terminal of the second capacitor C2 is electrically connected to the second scan signal terminal GATE 2.

Illustratively, as shown in fig. 18, the second input circuit 202 further includes: a thirty-second transistor M32.

For example, as shown in fig. 18, the gate of the thirtieth transistor M32 is electrically connected to the input signal terminal Iput, the first pole of the thirtieth transistor M32 is electrically connected to the input signal terminal Iput, and the second pole of the thirtieth transistor M32 is electrically connected to the second pull-up node Q2.

Illustratively, as shown in fig. 18, the second control circuit 203 includes: an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, and a fourteenth transistor M14.

For example, as shown in fig. 18, the gate of the eleventh transistor M11 is electrically connected to the sixth voltage signal terminal VDD _ B, the first pole of the eleventh transistor M11 is electrically connected to the third voltage signal terminal VDD _ B, and the second pole of the eleventh transistor M11 is electrically connected to the gate of the twelfth transistor M12 and the first pole of the thirteenth transistor M13. A first pole of the twelfth transistor M12 is electrically connected to the sixth voltage signal terminal VDD _ B, and a second pole of the twelfth transistor M12 is electrically connected to the second pull-down node QB _ B and the first pole of the fourteenth transistor M14. A gate of the thirteenth transistor M13 is electrically connected to the second pull-up node Q2, and a second pole of the thirteenth transistor M13 is electrically connected to the fourth voltage signal terminal VGL 1. A gate of the fourteenth transistor M14 is electrically connected to the second pull-up node Q2, and a second pole of the fourteenth transistor M14 is electrically connected to the fourth voltage signal terminal VGL 1.

Illustratively, as shown in fig. 18, the sixth reset circuit 204 includes: a twenty-third transistor M23.

For example, as shown in fig. 18, the gate of the twentieth transistor M23 is electrically connected to the input signal terminal Iput, the first pole of the twentieth transistor M23 is electrically connected to the second pull-down node QB _ B, and the second pole of the twentieth transistor M23 is electrically connected to the fourth voltage signal terminal VGL 1.

Illustratively, as shown in fig. 18, the seventh reset circuit 205 includes: a twenty-fourth transistor M24 and a twenty-fifth transistor M25.

For example, as shown in fig. 18, the gate of the twenty-fourth transistor M24 is electrically connected to the first pull-down node QB _ a, the first pole of the twenty-fourth transistor M24 is electrically connected to the second pull-up node Q2, and the second pole of the twenty-fourth transistor M24 is electrically connected to the fourth voltage signal terminal VGL 1. A gate of the twenty-fifth transistor M25 is electrically connected to the second pull-down node QB _ B, a first pole of the twenty-fifth transistor M25 is electrically connected to the second pull-up node Q2, and a second pole of the twenty-fifth transistor M25 is electrically connected to the fourth voltage signal terminal VGL 1.

Illustratively, as shown in fig. 18, the eighth reset circuit 206 includes: a twenty-sixth transistor M26 and a twenty-seventh transistor M27.

For example, as shown in fig. 18, the GATE of the twenty-sixth transistor M26 is electrically connected to the second pull-down node QB _ B, the first pole of the twenty-sixth transistor M26 is electrically connected to the second scan signal terminal GATE2, and the second pole of the twenty-sixth transistor M26 is electrically connected to the fifth voltage signal terminal VGL 2. A GATE of the twenty-seventh transistor M27 is electrically connected to the first pull-down node QB _ a, a first pole of the twenty-seventh transistor M27 is electrically connected to the second scan signal terminal GATE2, and a second pole of the twenty-seventh transistor M27 is electrically connected to the fifth voltage signal terminal VGL 2.

Illustratively, as shown in fig. 18, the ninth reset circuit 207 includes: a twenty-eighth transistor M28.

For example, the gate of the twenty-eighth transistor M28 is electrically connected to the display reset signal terminal STD, the first pole of the twenty-eighth transistor M28 is electrically connected to the second pull-up node Q2, and the second pole of the twenty-eighth transistor M28 is electrically connected to the fourth voltage signal terminal VGL 1.

Illustratively, as shown in fig. 18, the tenth reset circuit 208 includes: a thirtieth transistor M30.

For example, a gate of the thirtieth transistor M30 is electrically connected to the global reset signal terminal TRST, a first pole of the thirtieth transistor M30 is electrically connected to the second pull-up node Q2, and a second pole of the thirtieth transistor M30 is electrically connected to the fourth voltage signal terminal VGL 1.

It should be noted that the structure of the shift register 110 in the above embodiments is only an exemplary description, and should not be construed as a limitation to the specific structure of the shift register 110 in the present disclosure.

In some embodiments, as shown in fig. 3 and 4, the display device 1000 includes at least one scan driving circuit 100 as described in some of the examples above.

The scan driving circuit 100 included in the display device 1000 has the same structure and beneficial effects as the scan driving circuit 100 provided in some examples, and the description thereof is omitted here.

Illustratively, as shown in fig. 3, the display device 1000 includes one scan driving circuit 100.

Illustratively, as shown in fig. 4, the number of the scan driving circuits 100 is two, and the two scan driving circuits 100 are respectively located at two opposite sides of the plurality of first gate lines GL1 and are respectively electrically connected to the plurality of first gate lines GL 1.

Thus, the two scan driving circuits 100 can simultaneously transmit the scan signals to the pixel driving circuit 200, so that the driving capability of the scan driving circuit 100 can be improved.

For example, as shown in fig. 4, each of the plurality of first gate lines GL1 is electrically connected to two scan driving circuits 100 at the same time.

In the scan driving circuit 100, since there are both the plurality of clock signal lines CLK extending in the first direction Y and the plurality of connection lines L extending in the second direction X, at least one of the connection lines L needs to cross over the plurality of clock signal lines CLK to be electrically connected to the shift register 110, and thus, a short-circuit problem is likely to occur at a position where the connection line L and the clock signal line CLK meet. In the scan driving circuit 100 'in the related art, one clock signal line CLK' is electrically connected to one shift register 110 'through one connection line L', and when a short circuit problem occurs, it is difficult to maintain the scan driving circuit 100 ', so that the scan driving circuit 100' is easily unable to normally operate.

Based on this, in some embodiments, a maintenance method of a scan driving circuit is provided, which is applied to the scan driving circuit 100 as described in any one of the above examples, as shown in fig. 14, and includes S100 to S200.

S100: and detecting the connecting line L, and judging whether the connecting line L and the clock signal line CLK crossed with the connecting line L are short-circuited or not.

For example, an Array Tester (AT) may be used to detect the connection line L, and determine whether the connection line L is shorted according to a signal collected by the AT.

S200: in the case where the connection line L and the clock signal line CLK crossing the connection line L are short-circuited, a portion of the connection line L between the shift register 110 electrically connected thereto and the clock signal line short-circuited therewith is cut off, and a portion of the connection line L between the clock signal line electrically connected thereto and the clock signal line short-circuited therewith is cut off.

Since the clock signal end of the shift register 110 included in the scan driving circuit 100 is electrically connected to the two clock signal lines CLK and is electrically connected to the two clock signal lines CLK through the two connection lines L, when a short circuit occurs in one of the two connection lines L, by using the above method, on one hand, signal transmission between the short-circuited connection line and the shift register 110 and signal transmission between the short-circuited clock signal line and the clock signal line electrically connected thereto can be cut off, thereby preventing the malfunction from continuing to occur, and on the other hand, the other normal connection line L can still transmit a clock signal to the shift register 110, thereby enabling the shift register 110 to continue to operate normally.

For example, the connecting line L may be cut by laser cutting.

For example, as shown in fig. 15, when one connection line L is short-circuited with one clock signal line CLK, a short-circuited point is marked as a, a connection point between the short-circuited connection line L and the clock signal line CLK electrically connected thereto is marked as b, and a connection point between the short-circuited connection line L and the shift register 110 electrically connected thereto is marked as c, and at this time, a portion between a and b and a portion between a and c are cut off, respectively, the above advantageous effects can be achieved.

For example, one connection line L is shorted to at least two clock signal lines CLK.

As shown in fig. 16, one connection line L is short-circuited with two clock signal lines CLK. At this time, the two short-circuited sites may be respectively marked as d and e, the connection point of the short-circuited connection line L and the clock signal line CLK electrically connected thereto is marked as f, the connection point of the short-circuited connection line L and the shift register 110 electrically connected thereto is marked as g, where e is closer to g than d, and at this time, the portion between f and d, the portion between d and e, and the portion between e and g are respectively cut off, so that the above advantageous effects can be achieved.

It should be noted that, in the case where one connection line L is short-circuited with more than two clock signal lines CLK, the above-mentioned cutting principle may be referred to cut off the portions between the respective sites, so as to achieve the above-mentioned beneficial effects.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art will appreciate that changes or substitutions within the technical scope of the present disclosure are included in the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A scan driving circuit, comprising:

a plurality of clock signal lines extending in a first direction;

a plurality of connecting lines extending in a second direction; one of the connection lines is electrically connected to one of the clock signal lines; and the number of the first and second groups,

a plurality of shift registers; the shift register includes: an output circuit; the output circuit is electrically connected with the clock signal end; the clock signal end is also electrically connected with the two connecting wires and is electrically connected with the two clock signal wires through the two connecting wires;

clock signals transmitted by two clock signal lines electrically connected with the same shift register are the same; in any two of the shift registers, the difference between the sum of the resistances of the two connecting lines electrically connected with different shift registers is a first preset value.

2. The scan driving circuit according to claim 1, wherein a sum of lengths of two of the connection lines electrically connected to different ones of the shift registers differs by a second predetermined value between any two of the shift registers.

3. The scan driving circuit according to claim 1, wherein the output circuit is further electrically connected to a scan signal terminal;

the scanning driving circuit is applied to a display device, and the display device comprises: a plurality of first gate lines extending in the second direction;

the scanning signal terminal is also electrically connected with the end part of one first grid line.

4. The scan driver circuit according to claim 1, wherein the shift register comprises: a first sub shift register and a second sub shift register;

the clock signal end of the output circuit of the first sub-shift register is electrically connected with one connecting wire;

and the clock signal end of the output circuit of the second sub shift register is electrically connected with one connecting wire.

5. The scan driving circuit according to claim 4, wherein the output circuit of the first sub-shift register is further electrically connected to a first scan signal terminal, and the output circuit of the second sub-shift register is further electrically connected to a second scan signal terminal;

the scanning driving circuit is applied to a display device, and the display device comprises: a plurality of first gate lines and a plurality of second gate lines;

the first scanning signal end is electrically connected with the end part of the first grid line;

the second scanning signal terminal is electrically connected with the second grid line and is electrically connected with the first grid line at a position except two end parts through the second grid line.

6. The scan driving circuit according to claim 5, wherein the second scan signal terminal is electrically connected to a central position of the first gate line through the second gate line.

7. The scan driver circuit according to claim 5, wherein the display device includes a plurality of pixel driver circuits, the pixel driver circuit comprising: a plurality of transistors;

the orthographic projection of the second grid lines on the plane where the display device is located and the orthographic projection of the transistors on the plane where the display device is located are not overlapped.

8. The scan driving circuit according to claim 4, wherein a length of the connection line electrically connected to the output circuit of the first sub shift register is longer than a length of the connection line electrically connected to the output circuit of the second sub shift register.

9. The scan driving circuit according to claim 1, wherein the plurality of clock signal lines include: a first clock signal line group and a second clock signal line group;

the plurality of shift registers include: a plurality of shift register groups; the shift register group comprises at least two shift registers; the two clock signal lines electrically connected with the same shift register are respectively positioned in the first clock signal line group and the second clock signal line group;

the arrangement order of the clock signal lines in the first clock signal line group electrically connected with the at least two shift registers is opposite to the arrangement order of the clock signal lines in the second clock signal line group electrically connected with the at least two shift registers.

10. The scan driving circuit according to claim 9, wherein the first clock signal line group includes six clock signal lines, and the second clock signal line group includes six clock signal lines; the shift register group comprises six shift registers;

the first clock signal line and the twelfth clock signal line are electrically connected with the 6n-5 th shift register;

the second clock signal line and the eleventh clock signal line are electrically connected with the 6n-4 th shift register;

the third clock signal line and the tenth clock signal line are electrically connected with the 6n-3 shift registers;

the fourth clock signal line and the ninth clock signal line are electrically connected with the 6n-2 shift register;

the fifth clock signal line and the eighth clock signal line are electrically connected with the 6n-1 th shift register;

the sixth clock signal line and the seventh clock signal line are electrically connected with the 6 nth shift register;

n is a positive integer.

11. A maintenance method of a scan driving circuit, the maintenance method being applied to the scan driving circuit according to any one of claims 1 to 10, wherein the scan driving circuit includes a plurality of clock signal lines, a plurality of connection lines, and a plurality of shift registers; the maintenance method comprises the following steps:

detecting the connecting line, and judging whether the connecting line and a clock signal line crossed with the connecting line are short-circuited or not;

and under the condition of short circuit between the connecting line and the clock signal line crossed with the connecting line, cutting off a part of the connecting line, which is positioned between the shift register electrically connected with the connecting line and the clock signal line short-circuited with the connecting line, and a part of the connecting line, which is positioned between the clock signal line electrically connected with the connecting line and the clock signal line short-circuited with the connecting line.

12. A display device, characterized in that the display device comprises: at least one scan driver circuit as claimed in any one of claims 1 to 10.

13. The display device according to claim 12, wherein the display device comprises: a plurality of first gate lines extending in a second direction;

the number of the scanning driving circuits is two;

the two scanning driving circuits are respectively positioned at two opposite sides of the plurality of first grid lines and are respectively and electrically connected with the plurality of first grid lines.