CN114077089B

CN114077089B - Display panel and display device

Info

Publication number: CN114077089B
Application number: CN202111404991.6A
Authority: CN
Inventors: 冯大伟; 赵宇; 张勇; 王建; 王先; 葛杨; 马建威; 石磊; 关星星; 王策; 郭晖
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Optoelectronics Technology Co Ltd
Priority date: 2021-11-24
Filing date: 2021-11-24
Publication date: 2023-10-13
Anticipated expiration: 2041-11-24
Also published as: CN114077089A

Abstract

The application provides a display panel and a display device, wherein in the display panel, a pixel electrode is arranged on a substrate and is positioned in a pixel area; a gap is formed between the pixel electrode and the signal lines on two sides of the pixel electrode; the first shielding part is arranged at one end of the gap close to the corresponding thin film transistor, and the orthographic projection of the first shielding part on the substrate at least covers the orthographic projection of part of the gap on the substrate; the first shielding portion is insulated from the signal line and the pixel electrode. The first shielding part can not be influenced by the size of the thin film transistor and the distance between the first shielding part and the thin film transistor, so that light leakage at the position of the gap close to the thin film transistor is fully shielded, and the contrast of the display device is improved.

Description

Display panel and display device

Technical Field

The application relates to the technical field of display, in particular to a display panel and a display device.

Background

At present, the size of the aperture ratio of the display product directly influences the size of the transmittance of the product, thereby directly determining the competitiveness of the display product. In the conventional display product, a non-driving region (non-pixel region) exists between adjacent pixels on the display panel, and the liquid crystal arrangement is not controlled, so that a light leakage phenomenon occurs.

Therefore, in the prior art, a Black Matrix (BM) is generally required to be disposed on a color film substrate disposed opposite to an array substrate to block light leakage of a non-driving area. However, the distance between the black matrix color film substrate and the array substrate is relatively long, and the alignment offset in the mask process is relatively large, so that the black matrix usually covers a part of the pixel area to completely block light leakage. Therefore, the existing black matrix occupies a certain space of the display product, the aperture ratio of the display product is lost to a certain extent, the transmittance of the display product is influenced, the optical properties such as the color gamut of the display picture of the display product are influenced, and the competitiveness of the display product is further influenced.

Disclosure of Invention

The application provides a display panel and a display device, which solve the technical problem of aperture ratio loss caused by light leakage shielding of the display device through a black matrix in the prior art.

In a first aspect, the present application provides a display panel comprising:

a substrate base;

a plurality of scanning lines which are arranged on the substrate base plate at intervals and extend along the row direction;

a plurality of signal lines arranged on the substrate base plate at intervals and extending along the column direction; wherein the scan lines are insulated from the signal lines to overlap to define a plurality of pixel regions;

a plurality of pixel electrodes disposed on the substrate and located in the plurality of pixel regions; each pixel electrode is connected with at least one adjacent signal line through a corresponding thin film transistor, and a gap is formed between at least one pixel electrode and at least one adjacent signal line;

the first shielding part is arranged at one end of the gap close to the corresponding thin film transistor;

wherein the orthographic projection of the first shielding part on the substrate covers at least part of orthographic projection of the gap on the substrate; the first shielding portion is insulated from the signal line and the pixel electrode.

In some embodiments, the display panel further includes:

the second shielding part is arranged at one end of the gap away from the corresponding thin film transistor;

the second shielding part is used for covering at least part of the orthographic projection of the gap on the substrate, and the second shielding part is mutually insulated from the scanning line and the first shielding part.

In some embodiments, in the display panel, the second shielding portion and the signal line are located at a same layer.

In some embodiments, in the display panel, the second shielding portion is connected to the adjacent signal line.

In some embodiments, in the display panel, the layer where the first shielding portion is located between the layer where the signal line is located and the substrate.

In some embodiments, in the display panel, the first shielding portion and the scan line are located at a same layer.

In some embodiments, in the display panel, the gap is formed between at least one pixel electrode and the signal lines adjacent to both sides.

In some embodiments, in the display panel, an orthographic projection of the thin film transistor on the substrate is located between the corresponding pixel electrode and an orthographic projection of the scan line on the substrate.

In some embodiments, in the display panel, a distance between an end of the pixel electrode, which is close to the corresponding thin film transistor, and the adjacent scanning line is a first distance, and a distance between an end of the pixel electrode, which is far from the corresponding thin film transistor, and the adjacent scanning line is a second distance;

the first distance corresponding to the same pixel electrode is larger than the second distance.

In some embodiments, in the display panel, a drain electrode of the thin film transistor is electrically connected to the corresponding pixel electrode through a first connection portion;

the first connecting part and the signal line are positioned on the same layer, and the orthographic projection size of the first connecting part on the substrate base plate is larger than the line width of the drain electrode of the thin film transistor.

In some embodiments, in the above display panel, the display panel further includes:

a common electrode, the layer of which is located between the layer of the pixel electrode and the layer of the signal line;

wherein the common electrode is isolated from the signal line by a first insulating layer; the common electrode is isolated from the pixel electrode by a second insulating layer; the orthographic projection of the common electrode on the substrate base plate at least covers the orthographic projection of part of the signal line on the substrate base plate.

In some embodiments, in the display panel, the first connection portion is electrically connected to the pixel electrode through a second contact hole penetrating the first insulating layer and the second insulating layer.

In some embodiments, in the display panel, the plurality of signal lines includes a plurality of data lines and a plurality of common lines alternately arranged;

wherein the common electrode is electrically connected to the common line through at least one first contact hole penetrating the first insulating layer.

In some embodiments, in the display panel, two adjacent pixel electrodes in the same row are respectively connected to the scan lines on two sides.

In some embodiments, in the display panel, each of the scan lines includes a first gate line and a second gate line disposed at intervals.

In some embodiments, in the display panel, the pixel electrodes in the same column are respectively connected to the first gate lines adjacent thereto; or alternatively, the first and second heat exchangers may be,

the pixel electrodes of the same column are all connected with the second gate lines adjacent to the pixel electrodes.

In some embodiments, the display panel further includes: a color film substrate arranged opposite to the substrate;

the color film substrate is provided with a black matrix layer at one side close to the substrate, and orthographic projection of the black matrix layer on the substrate at least covers orthographic projection of part of scanning lines and part of signal lines on the substrate.

In a second aspect, the present application provides a display device comprising a display panel as claimed in any one of the first aspects.

By adopting the technical scheme, at least the following technical effects can be achieved:

the application provides a display panel and a display device, wherein a plurality of pixel electrodes are arranged on a substrate and are positioned in a plurality of pixel areas; a gap is formed between at least one pixel electrode and at least one adjacent signal line; the first shielding part is arranged at one end of the gap close to the corresponding thin film transistor, and the orthographic projection of the first shielding part on the substrate at least covers the orthographic projection of part of the gap on the substrate; the first shielding portion is insulated from the signal line and the pixel electrode. The first shielding part can not be influenced by the size of the thin film transistor and the distance between the first shielding part and the thin film transistor, so that light leakage at the position of the gap close to the thin film transistor is fully shielded, and the contrast of the display device is improved. And the distance between the first shielding part and the substrate is relatively short, compared with the black matrix layer, the alignment offset in the mask process is relatively small, the overlapping width of the first shielding part and the pixel electrode can be very small, the loss of the aperture ratio can be greatly reduced, and the transmittance of the display device is improved.

Drawings

The accompanying drawings are included to provide a further understanding of the application, and are incorporated in and constitute a part of this specification, illustrate the application and together with the description serve to explain, without limitation, the application. In the drawings:

fig. 1 is a schematic cross-sectional view of a display panel at a location of a thin film transistor;

FIG. 2 is a schematic diagram of a process sequence of a film layer of a display panel;

FIG. 3 is a schematic cross-sectional view of a display panel at a signal line position;

FIG. 4 is a schematic top view of another display panel;

FIG. 5 is a schematic cross-sectional view of FIG. 4 along line A-A';

FIG. 6 is a schematic view of an electric field shielding of the display panel shown in FIG. 4;

FIG. 7 is a schematic diagram of an optical simulation result of the display panel shown in FIG. 4;

FIG. 8 is a schematic top plan view of a display panel according to an exemplary embodiment of the present application;

FIG. 9 is a schematic cross-sectional view of FIG. 8 along line B-B';

FIG. 10 is a schematic diagram of optical simulation results of the display panel shown in FIG. 8;

FIG. 11 is a schematic top plan view of another display panel according to an exemplary embodiment of the present application;

FIG. 12 is a schematic cross-sectional view of FIG. 11 along line C-C';

in the drawings, wherein like parts are designated by like reference numerals throughout, the drawings are not to scale;

the reference numerals are:

down Base-substrate board; gate-Gate layer; a GI-gate insulating layer; an Active-Active layer; SD-source drain metal layer; s-source electrode; d-drain electrode; PVX 1-a first insulating layer; 1 ^st An ITO-common electrode layer; PVX 2-a second insulating layer; PVX-insulating layer; 2 ^nd An ITO-pixel electrode layer; BM-black matrix layer; up Base-color film substrate;

11-a substrate base; 12-scanning lines; 121-a first gate line; 122-a second gate line; 13-signal lines; 131-data lines; 132-a common line; 14-pixel electrodes; 141-a second connection; 15-a thin film transistor; 151-gate; 152-an active layer; 153-drain; 154-first connection; 16-a common electrode; CNT-contact holes; BM-black matrix layer; a gap between the S-pixel electrode and the signal line; d1—overlap width of pixel electrode and common electrode; d2—overlap width of the shielding portion and the pixel electrode; a GI-gate insulating layer; PVX 1-a first insulating layer; PVX 2-a second insulating layer; 31-a color film substrate;

21-a substrate base; 22-scan lines; 221-a first gate line; 222-a second gate line; 23-signal lines; 231-data line; 232-a common line; 24-pixel electrodes; 241-a second connection; a 25-thin film transistor; 251-gate; 252-active layer; 253-drain; 254-first connection; 26-a common electrode; 27-a first shielding part; 28-a second shield; CNT 2-second contact holes; BM-black matrix layer; a gap between the S-pixel electrode and the signal line; d1—overlap width of pixel electrode and common electrode; d2—the overlapping width of the second shielding portion and the pixel electrode; d3—the overlapping width of the first shielding portion and the pixel electrode; a GI-gate insulating layer; PVX 1-a first insulating layer; PVX 2-a second insulating layer; 41-color film substrate.

Detailed Description

The following will describe embodiments of the present application in detail with reference to the drawings and examples, thereby solving the technical problems by applying technical means to the present application, and realizing the corresponding technical effects can be fully understood and implemented accordingly. The embodiment of the application and the characteristics in the embodiment can be mutually combined on the premise of no conflict, and the formed technical scheme is within the protection scope of the application. In the drawings, the size of layers and regions, as well as the relative sizes, may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that, although the terms "first," "second," "third," etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In the following description, for the purpose of providing a thorough understanding of the present application, detailed structures and steps are presented in order to illustrate the technical solution presented by the present application. Preferred embodiments of the present application are described in detail below, however, the present application may have other embodiments in addition to these detailed descriptions.

In the conventional structure of a display panel such as a liquid crystal display panel, a 6Mask scheme is generally adopted, and a film structure is illustrated in fig. 1 by a thin film transistor (Thin Film Transistor, TFT) position.

A Gate layer Gate, a Gate insulating layer GI, an Active layer Active, a source/drain metal layer SD, a first insulating layer PVX1, a common electrode layer 1st ITO, a second insulating layer PVX2, and a pixel electrode layer 2nd ITO, which are stacked in this order, are formed on a substrate Down Base.

Wherein, the grid layer Gate is used for forming grid and scanning line of the thin film transistor; the grid insulating layer GI is used as an insulating layer between the Active layer and the grid layer Gate; the source/drain metal layer SD is used to form the source and drain electrodes of the thin film transistor, and the signal line (including the common line and the data line); the grid electrode, the Active layer Active, the source electrode S and the drain electrode D form the thin film transistor; the first insulating layer PVX1 is used as an insulating layer between the Active layer, the source drain metal layer SD and the common electrode layer 1st ITO; the common electrode layer 1st ITO is used to form a common electrode; the second insulating layer PVX2 is used as an insulating layer between the common electrode layer 1st ITO and the pixel electrode layer 2nd ITO; the pixel electrode layer 2nd ITO is used to form a pixel electrode. The drain electrode D of the thin film transistor is connected to the pixel electrode layer 2nd ITO through a contact hole (not labeled in the drawing) penetrating the first insulating layer PVX1 and the second insulating layer PVX2, so as to transmit a signal on the signal line to the pixel electrode through the thin film transistor, so as to drive the pixel electrode.

The process sequence of the display panel is shown in fig. 2, wherein the Gate layer Gate, the Active layer Active, the source/drain metal layer SD, the common electrode layer 1st ITO, the second insulating layer PVX2, and the pixel electrode layer 2nd ITO all need to be subjected to a mask (mask) process, that is, the panel needs to be subjected to a 6mask process. Wherein the mask process comprises the procedures of film deposition, gluing, exposure, development, etching, photoresist removal and the like. Since the formation of the contact hole between the drain electrode and the pixel electrode layer 2nd ITO can be simultaneously completed in the mask process of the second insulating layer PVX2, the mask process is not required in the film process of the first insulating layer PVX 1. The film process of the gate insulating layer GI and the first insulating layer PVX1 does not involve a mask process, but involves only a film deposition (dep.) process. The film deposition (dep.) process includes film deposition, annealing, and the like.

In the above mask process, all the film layers can be aligned by taking Gate layer Gate as alignment reference layer, and the alignment precision between the film layers satisfies the following calculation formula:

A～B＝Sqrt((A_tol/2)^2+(B_tol/2)^2+A_ol^2+B_ol^2)；

wherein A, B represents different layers, A-B represents the alignment precision between two layers, namely the maximum offset, A_tool is the fluctuation value of the technological parameter of the A layer, A_ol is the alignment fluctuation of the A layer relative to the reference layer, and when the A_ol is used as the reference layer, the A_ol value is 0. The B represents different film layers with the same meaning and is not repeated,

it will be appreciated that the position and linewidth of the reference film is the most accurate and the film offset is the smallest.

Taking a twisted nematic liquid crystal display panel (Twisted Nematic Liquid Crystal Display, TN-LCD) as an example, a gap is usually formed between the pixel electrode and the adjacent signal line, and a black matrix layer BM on the color film substrate Up Base is usually used for shielding, so that the alignment offset in the mask process is larger, and therefore, the black matrix usually needs to cover a larger part of the pixel area, so that light leakage can be completely blocked. In general, the maximum offset is required to be more than 5 micrometers, and the wrapping distance is required to be further extended to be more than 10 micrometers in order to shield the disorder electric field below, as shown in fig. 3, the loss of the aperture ratio is serious, and the transmittance of the display product is seriously affected.

In another display panel, the gap between the pixel electrode and the adjacent signal line is not blocked using the black matrix layer BM on the color film substrate, but is blocked by the widened portion of the signal line. The structure of such a display panel includes, as shown in fig. 4 and 5, a substrate 11, a plurality of scanning lines 12, a plurality of signal lines 13, a pixel electrode 14, a common electrode 16, a thin film transistor 15, a gate insulating layer GI, a first insulating layer PVX1, a second insulating layer PVX2, and a color film substrate 31.

Wherein a plurality of scanning lines are disposed on the substrate 11 at intervals and extend in a row direction, each scanning line 12 includes a first gate line 121 and a second gate line 122. The scan lines 12 are formed by the gate layer.

The plurality of signal lines 13 are disposed on the substrate 11 at intervals and extend in the column direction, and the plurality of signal lines 13 are arranged in the row direction.

The plurality of signal lines 13 include a plurality of data lines 131 and a plurality of common lines 132 alternately arranged.

The scan lines 12 are insulated from the data lines 131 and the common lines 132 to define a plurality of pixel regions (not shown). The scan line 12 is insulated from the data line 131 and the common line 132 by a gate insulating layer GI.

The data line 131 and the common line 132 are formed through a source-drain metal layer.

The pixel electrode 14 is disposed on the substrate 11 and located in the pixel region, and the orthographic projection of the pixel electrode 14 on the substrate 11 does not cover the orthographic projection of the scan line 12 and the signal line 13 on the substrate 11.

The layer of the common electrode 16 is located between the layer of the pixel electrode 14 and the layer of the signal line 13, the common electrode 16 is isolated from the signal line 13 by the first insulating layer PVX1, and the common electrode 16 is isolated from the pixel electrode 14 by the second insulating layer PVX2.

The orthographic projection of the common electrode 16 on the substrate 11 covers at least the orthographic projection of a part of the scanning line 12 and a part of the signal line 13 on the substrate 11, and the orthographic projection of a part of the pixel electrode 15 on the substrate 11.

The pixel electrode 14 is connected to at least one signal line 13 adjacent thereto through a corresponding thin film transistor 15. In some cases, the pixel electrode 14 is connected to an adjacent data line 131 through a corresponding thin film transistor 15.

The thin film transistor 15 includes a gate electrode 151, an active layer 152, a source electrode (not shown) and a drain electrode 153, wherein the source electrode of the thin film transistor 15 is connected to the adjacent data line 131, and the drain electrode 153 is electrically connected to the corresponding pixel electrode 14 through the first connection portion 154. The first connection portion 154 is formed on the same layer as the drain electrode 153, and the materials of the two layers are the same.

And the pixel electrode 14 may be electrically connected to the first connection part 154 through the second connection part 141. The second connection portion 141 is located on the same layer as the pixel electrode 14, and the materials of the two layers are the same.

Specifically, the second connection portion 141 is connected to the first connection portion 154 through a contact hole CNT penetrating the second insulating layer PVX2 and the first insulating layer PVX 1.

In the above-described display panel, since the gap S is formed between the pixel electrode 14 and the signal lines on both sides, which causes light leakage in a dark state of the display panel, the signal lines 13 are widened at the position of the gap S to form the shielding portion 17, and the orthographic projection of the shielding portion 17 on the substrate 11 covers the orthographic projection of the partial gap S on the substrate 11.

When the black state is displayed (Dark Status), the advantage of high alignment precision between metal layers can be fully utilized, the backlight light leakage is shielded by utilizing the shielding part 17 formed by widening the signal line 13, the alignment precision (maximum offset) of the signal line is about 2 micrometers relative to the reference film layer grid layer, and meanwhile, the disorder electric field of the signal line 13 below is shielded by utilizing the common electrode, as shown by an arrow at the position of the signal line 13 in fig. 6.

However, in the display panel, in order to ensure that the thin film transistor 15 and the pixel electrode 14 are well connected, the aperture of the contact hole CNT is as large as possible, so that the dimensions of the first connection portion 154 and the second connection portion 141 are as large as possible to satisfy the formation and contact performance of the contact hole CNT, which results in a short distance between the first connection portion 154 and the signal lines on both sides, and in order to avoid the problem of crosstalk between the signal lines 13 and the pixel electrode 14 due to short circuit or crosstalk between the first connection portion 154 and the shielding portions 17 on both sides, the shielding portions 17 cannot be provided on both sides of the first connection portion 154 to shield light leakage, which eventually causes dark light leakage on both sides of the first connection portion 154, and the optical simulation result is shown in fig. 7. In order to avoid serious loss of aperture ratio, the light leakage in the portion (the area indicated by the dotted circle in fig. 7) is not completely blocked by the black matrix layer BM on the color film substrate 31, so that dark light leakage still occurs, thereby reducing contrast.

In the display panel described above, the common electrode 16 and the pixel electrode 14 have a coverage width D1, and the shielding portion 17 and the pixel electrode 14 have a coverage width D2. When the gate layer is used as an alignment reference layer for the mask process of the shielding portion 17 and the pixel electrode 14, the alignment fluctuation (offset) between the shielding portion 17 and the pixel electrode 14 is relatively large, so the coverage width D2 of the shielding portion 17 and the pixel electrode 14 needs to be large enough (the design value needs to be larger than the alignment precision of both), so that the light shielding effect can be ensured, and the aperture ratio is also lost to a certain extent. PPI is more severe when the pixel size is smaller and PPI is higher. Due to the high PPI plus double gate design, the aperture ratio is significantly reduced, and the corresponding transmittance is also significantly reduced.

Therefore, an embodiment of the present application provides a display panel, as shown in fig. 8 and 9, which includes a substrate 21, a plurality of scan lines 22, a plurality of signal lines 23, a plurality of pixel electrodes 24, a thin film transistor 25, a first shielding portion 27, a gate insulating layer GI, a first insulating layer PVX1, and a second insulating layer PVX2.

The plurality of scan lines 22 are disposed on the substrate 21 at intervals and extend in the row direction. The scan lines 22 are formed through the gate layer.

The plurality of signal lines 23 are disposed on the substrate 21 at intervals and extend in the column direction, and the plurality of signal lines 23 are arranged in the row direction, the signal lines 23 being formed by the source-drain metal layer.

The signal lines 23 and the scanning lines 22 are insulated and overlapped to define a plurality of pixel regions (not shown). The signal line 23 and the scanning line 22 are insulated from each other by a gate insulating layer GI.

The plurality of pixel electrodes 24 are disposed on the substrate 21 and located in the pixel region, and the orthographic projection of the pixel electrodes 24 on the substrate 21 does not cover the orthographic projection of the scan lines 22 and the signal lines 23 on the substrate 21.

Each pixel electrode 24 is connected to at least one signal line 23 adjacent thereto through a corresponding thin film transistor 25.

In the display panel described above, a gap S is provided between at least one pixel electrode 24 and at least one signal line 23 (at least one signal line) adjacent thereto, and this gap S causes light leakage in a dark state of the display panel.

In this embodiment, the first shielding portion 27 is disposed at one end of the gap S near the corresponding thin film transistor 25, and the orthographic projection of the first shielding portion 27 on the substrate 21 covers at least the orthographic projection of a portion of the gap S on the substrate 21; the first shielding portion 27 is insulated from the signal line 23 and the pixel electrode 24.

In this case, since the first shielding portion 27 is insulated from the signal line 23 and the pixel electrode 24, even if the front projection of the first shielding portion 27 on the substrate 21 overlaps the front projection of the signal line 23 and the pixel electrode 24 on the substrate 21 in some embodiments, the first shielding portion 27 does not cause a short circuit or signal crosstalk with the pixel electrode 24. Therefore, the first shielding portion 27 is not affected by the size of the thin film transistor 25 and the distance from the thin film transistor 25, so as to fully shield the light leakage at the position of the gap S close to the thin film transistor 25, and improve the contrast of the display device, and the optical simulation result is shown in fig. 10. The rest positions are within the wrapping range of the black matrix layer BM, so that no extra light leakage is generated in the actual product.

In some embodiments, at least one pixel electrode 24 has a gap S between two adjacent signal lines 23. Correspondingly, the first shielding parts 27 are arranged at the gaps S at both sides of the pixel electrode 24 to shield the light leakage, so as to further reduce the light leakage.

In some embodiments, a plurality of (or even each) pixel electrodes 24 have a gap S between them and the signal lines 23 adjacent to both sides. Correspondingly, the first shielding part 27 is arranged at the gap S at two sides of each pixel electrode 24 to shield the light leakage, so as to further reduce the light leakage.

In the display panel described above, the coverage width of the common electrode 26 and the pixel electrode 24 is D1, and the coverage width of the first shielding portion 27 and the pixel electrode 24 is D3.

Because the distance between the first shielding portion 27 and the substrate 21 is relatively short, the layer where the first shielding portion 27 is located can be used as an alignment reference film layer, compared with the technical scheme of shielding light of the black matrix layer BM, the alignment offset of the first shielding portion 27 in the mask process is relatively small, the coverage width D3 of the first shielding portion 27 and the pixel electrode 24 can be very small, the loss of the aperture ratio can be greatly reduced, and the transmittance of the display device is improved.

In some embodiments, the layer of the first shielding portion 27 is located between the layer of the signal line 23 and the substrate 21.

Correspondingly, in some embodiments, the material of the first shielding portion 27 includes a light shielding metal material. Further, the layer where the first shielding part 27 is located can be used as an alignment reference film layer, so that the loss of the aperture ratio is greatly reduced, and the transmittance of the display device is improved.

In some embodiments, the first barrier 27 is located at the same layer as the scan line 22.

In some embodiments, the first shielding portion 27 is formed of the same material as the scan line 22, i.e., the same gate layer.

In some embodiments, the orthographic projection of the thin film transistor 25 on the substrate 21 is between its corresponding pixel electrode 24 and the orthographic projection of the scan line 22 on the substrate 21.

The distance between the end of the pixel electrode 24 near the corresponding thin film transistor 25 and the adjacent scanning line 22 is a first distance (not labeled in the figure), and the distance between the end of the pixel electrode 24 far from the corresponding thin film transistor 25 and the adjacent scanning line 22 is a second distance (not labeled in the figure).

Wherein the first distance corresponding to the same pixel electrode 24 is greater than the second distance.

It will be appreciated that the gap S is close to one end of the corresponding thin film transistor 25, and the distance between the end of the gap S close to the corresponding thin film transistor 25 and the adjacent scanning line 22 is relatively large due to the existence of the thin film transistor 25, so that crosstalk with the scanning line 22 may be disregarded, which is also why the first shielding portion 27 may be located at the same layer as the scanning line 22.

While the gap S is far from one end of the corresponding thin film transistor 25 and is very small from the adjacent scanning line 22, in the embodiment in which the first shielding portion 27 and the scanning line 22 are located on the same layer, if the first shielding portion 27 is still used as a component for shielding light leakage, a short circuit is likely to occur between the first shielding portion 27 and the adjacent scanning line 22, so in some embodiments, the display panel further includes: the second shielding portion 28 is disposed at an end of the gap S away from the corresponding thin film transistor 25.

Wherein, the orthographic projection of the second shielding part 28 on the substrate 21 covers the orthographic projection of at least part of the gap S on the substrate 21, and the second shielding part 28 is insulated from the scanning line 22 and the first shielding part 27.

In some embodiments, the second shielding portion 28 and the signal line 23 are located on the same layer, and the second shielding portion 28 and the signal line 23 may be formed as a source-drain metal layer.

In some embodiments, the second shielding portion 28 is connected to the adjacent signal line 23, which corresponds to the second shielding portion 28 being formed by widening the signal line 23 in synchronization with the signal line 23.

The first shielding portion 27 and the second shielding portion 28 cooperate with each other, so that light leakage at the position of the gap S can be shielded to a certain extent, the contrast of the display device is improved, and the crosstalk problem between the signal line 23 and the pixel electrode 24 is avoided.

In the display panel, the coverage width of the first shielding portion 27 and the pixel electrode 24 is D3, and the coverage width of the second shielding portion 28 and the pixel electrode 24 is D2.

Because the first shielding part 27 and the second shielding part 28 are mutually insulated, overlapping compensation positions can be used for shielding light, the defect of insufficient shielding of a single-layer shielding part is overcome, dark state light leakage is reduced, and the contrast ratio is improved. The middle position of the gap S may be shielded by extending the first shielding portion 27 as shown in fig. 11 and 12, or may be shielded by extending the second shielding portion 28 as shown in fig. 8 and 9.

In some embodiments, in the masking process of the pixel electrode 24, the layer (Gate layer) where the first shielding portion 27 is located may be used as an alignment reference layer, and gate_ol is 0 according to an alignment accuracy formula, where the coverage width D3 of the first shielding portion 27 and the pixel electrode 24 is smaller than the coverage width D2 of the second shielding portion 28 and the pixel electrode 24, so that the aperture ratio is improved compared to a shielding scheme that only uses a widened portion of the signal line 23. And since the coverage width D3 of the first shielding portion 27 and the pixel electrode 24 is smaller than the coverage width D2 of the second shielding portion 28 and the pixel electrode 24, the middle position of the gap S can be shielded by extending the first shielding portion 27, that is, the first shielding portion 27 is used for main shielding, and the second shielding portion 28 is used for auxiliary shielding, so that the aperture ratio is further improved, as shown in fig. 11 and 12. In the display panel, the second shielding part 28 is used as auxiliary shielding, so that the area of the second shielding part 28 is smaller, the coverage area of the second shielding part 28 (the widened part of the signal line 23) and the pixel electrode 24 is reduced, and the risk of crosstalk of signals on the signal line 23 to pixels is reduced.

In some embodiments, in the masking process of the pixel electrode 24, the layer (source-drain metal layer) where the second shielding portion 28 is located may be used as an alignment reference layer, and according to the alignment accuracy formula, sd_ol is 0, so that the coverage width D2 of the second shielding portion 28 and the pixel electrode 24 is smaller than the coverage width D3 of the first shielding portion 27 and the pixel electrode 24, the coverage width of the second shielding portion 28 may be reduced, and at this time, the middle complementary position of the gap S may be shielded by extending the second shielding portion 28, that is, the second shielding portion 28 mainly shields, and the first shielding portion 27 serves as an auxiliary shielding, so as to further improve the aperture ratio, as shown in fig. 8 and 9. In the display panel, the first shielding part 27 is used for auxiliary shielding, so that the area of the first shielding part 27 is smaller, the overlapping of the first shielding part 27 and the signal line 23 is reduced, the signal line 23 can ensure the load through the second shielding part 28 with a large area, and the risk of insufficient pixel charging is reduced.

The two design schemes are basically consistent in final aperture ratio, and the metal layers with higher alignment precision (small alignment offset) are used as main shielding, the metal layers with relatively low alignment precision (large alignment offset) are used for auxiliary shielding, so that the improvement of transmittance and the improvement of dark state light leakage are finally realized.

The thin film transistor 25 includes a gate electrode 251, an active layer 252, a source electrode (not shown) and a drain electrode 253, wherein the source electrode of the thin film transistor 25 is connected to the adjacent data line 231, and the drain electrode 253 is electrically connected to the corresponding pixel electrode 24 through the first connection portion 254. The first connection portion 254 is formed on the same layer as the signal line 23 and the drain electrode 253, and is also made of the same material, i.e., is formed of a source/drain metal layer.

The pixel electrode 24 may be electrically connected to the first connection portion 254 through the second connection portion 241. The second connection portion 241 is formed on the same layer as the pixel electrode 24, and is also made of the same material, i.e., is formed on the same layer as the pixel electrode 24.

In some embodiments, in order to ensure the connection effect of the drain electrode 253 of the thin film transistor 25 and the pixel electrode 24, the orthographic projection dimensions of the first connection portion 254 and the second connection portion 241 on the substrate 21 are larger than the line width of the drain electrode 253 of the thin film transistor 25.

In some embodiments, the display panel further includes a common electrode 26.

The common electrode 26 is located between the layer of the pixel electrode 24 and the layer of the signal line 23, the common electrode 26 is isolated from the signal line 23 by the first insulating layer PVX1, and the common electrode 26 is isolated from the pixel electrode 24 by the second insulating layer PVX2.

The orthographic projection of the common electrode 26 on the substrate 21 covers at least the orthographic projection of a part of the scanning line 22 and a part of the signal line 23 on the substrate 21, and the orthographic projection of a part of the pixel electrode 24 on the substrate 21.

The coverage width of the common electrode 26 and the pixel electrode 24 is D1.

Correspondingly, the second connection portion 241 is connected to the first connection portion 254 through a second contact hole CNT2 penetrating the second insulating layer PVX2 and the first insulating layer PVX 1.

In some embodiments, the plurality of signal lines 23 include a plurality of data lines 231 and a plurality of common lines 232 alternately arranged. Correspondingly, the pixel electrode 24 is connected to the adjacent data line 231 through the corresponding thin film transistor 25.

Wherein the common electrode 26 is electrically connected to the common line 232 through at least one first contact hole (not shown) penetrating the first insulating layer.

This structure can increase the resistance of the common line 232, reduce the voltage drop, avoid the delay of signals, and improve the display effect of the display panel.

In some embodiments, the orthographic projection of the first contact hole on the substrate 21 may be located between the orthographic projections of the first gate line 221 and the second gate line 222 on the substrate 21 in the scan line 22, and the common line 232 may be provided with a contact portion (e.g., a circular contact portion on the common line 232 in fig. 8 and 11) having a size larger than a line width of the common line 232 at the position of the first contact hole.

The materials of the pixel electrode 24 and the common electrode 26 each include an Indium Tin Oxide (ITO) material.

In some embodiments, two adjacent pixel electrodes 24 of the same row are respectively connected to the scan lines 22 on both sides.

In some embodiments, each scan line 22 includes a first gate line 221 and a second gate line 222 disposed at intervals; or, the pixel electrodes 24 of the same column are all connected to the second gate lines 222 adjacent thereto.

In this arrangement of the pixel electrodes 24, the positions of the thin film transistors 25 corresponding to the pixel electrodes 24 in the same row or column are staggered, so that the first shielding portions 27 and the second shielding portions 28 corresponding to the pixel electrodes 24 in the same row or column are staggered, and even if the alignment accuracy of the first shielding portions 27 and the second shielding portions 28 is different, the difference of the aperture ratio caused by the different alignment accuracy of the first shielding portions 27 and the second shielding portions 28 can be compensated by the pixel arrangement.

In some embodiments, the display panel further includes a color film substrate 41 disposed opposite to the substrate 21;

wherein, the color film substrate 41 is provided with a black matrix layer BM on a side close to the substrate 21, and the orthographic projection of the black matrix layer BM on the substrate 21 covers at least the orthographic projection of a part of the scanning lines 22 and a part of the signal lines 23 on the substrate 21.

In order to avoid the influence of the black matrix layer BM on the pixel aperture ratio, the black matrix layer BM needs to not block the pixel electrode 24 as much as possible except for a necessary portion defining the pixel shape. In the present application, the black matrix layer BM may not need to be blocked at the position of the gap S due to the arrangement of the first blocking portion 27 and the second blocking portion 28, and of course, the black matrix layer BM may cover a part of the gap S, that is, the front projection of the black matrix layer BM on the substrate 21 may cover the front projection of the part of the gap S on the substrate 21, which structure will not affect the aperture ratio.

In the application, the first shielding part 27 is arranged at one end of the gap S close to the corresponding thin film transistor 25, and the orthographic projection of the first shielding part 27 on the substrate 21 at least covers the orthographic projection of part of the gap S on the substrate 21; the first shielding portion 27 is insulated from the signal line 23 and the pixel electrode 24. The first shielding portion 27 can sufficiently shield light leakage at a position of the gap S close to the thin film transistor 25 without being affected by the size of the thin film transistor 25 and the distance from the thin film transistor 25, thereby improving the contrast of the display device.

The embodiment of the application also provides a display device, which comprises the display panel.

In some embodiments, the display device is a display panel, and the display panel includes the display substrate and the glass cover plate.

In some embodiments, the display device may include a display panel and a housing, the display panel being connected to the housing, e.g., the display panel is embedded within the housing. The display device can be any device with display function, such as a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator and the like.

The above is only a preferred embodiment of the present application, and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application. Although the embodiments of the present application are disclosed above, the present application is not limited to the embodiments which are used for the convenience of understanding the present application. Any person skilled in the art can make any modification and variation in form and detail without departing from the spirit and scope of the present disclosure, but the scope of the present disclosure is still subject to the scope of the present disclosure as defined by the appended claims.

Claims

1. A display panel, comprising:

a substrate base;

wherein the orthographic projection of the first shielding part on the substrate covers at least part of orthographic projection of the gap on the substrate; the first shielding part is insulated from the signal line and the pixel electrode;

further comprises:

2. The display panel according to claim 1, wherein the second shielding portion is located at the same layer as the signal line.

3. The display panel according to claim 2, wherein the second shielding portion is connected to the adjacent signal line.

4. The display panel according to claim 1, wherein the layer where the first shielding portion is located between the layer where the signal line is located and the substrate base plate.

5. The display panel of claim 4, wherein the first shielding portion is located at the same layer as the scan line.

6. The display panel according to claim 1, wherein at least one of the pixel electrodes has the gap with the signal lines adjacent to both sides.

7. The display panel of claim 1, wherein the orthographic projection of the thin film transistor on the substrate is between its corresponding orthographic projection of the pixel electrode and the scan line on the substrate.

8. The display panel according to claim 7, wherein a distance between an end of the pixel electrode close to the corresponding thin film transistor and the scanning line adjacent thereto is a first distance, and a distance between an end of the pixel electrode far from the corresponding thin film transistor and the scanning line adjacent thereto is a second distance;

9. The display panel according to claim 1, wherein a drain electrode of the thin film transistor is electrically connected to the corresponding pixel electrode through a first connection portion;

10. The display panel of claim 9, wherein the display panel further comprises:

11. The display panel according to claim 10, wherein the first connection portion is electrically connected to the pixel electrode through a second contact hole penetrating the first insulating layer and the second insulating layer.

12. The display panel according to claim 10, wherein the plurality of signal lines include a plurality of data lines and a plurality of common lines alternately arranged;

13. The display panel according to claim 1, wherein two adjacent pixel electrodes in the same row are connected to the scanning lines on both sides, respectively.

14. The display panel of claim 1, wherein each of the scan lines includes a first gate line and a second gate line disposed at a spacing.

15. The display panel according to claim 14, wherein the pixel electrodes of the same column are connected to the first gate lines adjacent thereto, respectively; or alternatively, the first and second heat exchangers may be,

16. The display panel of claim 1, further comprising: a color film substrate arranged opposite to the substrate;

17. A display device, comprising: the display panel of any one of claims 1 to 16.