CN114050147A - Semiconductor package device and method of manufacturing the same - Google Patents

Semiconductor package device and method of manufacturing the same Download PDF

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Publication number
CN114050147A
CN114050147A CN202111295022.1A CN202111295022A CN114050147A CN 114050147 A CN114050147 A CN 114050147A CN 202111295022 A CN202111295022 A CN 202111295022A CN 114050147 A CN114050147 A CN 114050147A
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density
area
low
layer
bridging
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Chinese (zh)
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吕文隆
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Priority to CN202111295022.1A priority Critical patent/CN114050147A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/48175—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H01L2224/48177—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48175—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H01L2224/48179—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the bond pad protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body

Abstract

The present disclosure relates to a semiconductor package device and a method of manufacturing the same. The semiconductor package device includes: a bridging rewiring layer including a high-density wiring area and a low-density wiring area; the first electronic element is arranged below the bridging redistribution layer, a first high-density input-output (I/O) area and a first low-density I/O area are arranged on the active surface of the first electronic element, the first high-density I/O area is electrically connected with the high-density circuit area, and the first low-density I/O area is electrically connected with the low-density circuit area through a routing wire; and the second electronic element is arranged adjacent to the first electronic element, the active surface of the second electronic element is provided with a second high-density I/O area and a second low-density I/O area, and the second high-density I/O area is electrically connected with the high-density circuit area.

Description

Semiconductor package device and method of manufacturing the same
Technical Field
The present disclosure relates to the field of semiconductor packaging technologies, and in particular, to a semiconductor packaging device and a method for manufacturing the same.
Background
Conventional package structures, such as a FOCoS (Fan Out Chip on Substrate) package structure, an ASIC (Application Specific Integrated Circuit) electronic component and an HBM (High Bandwidth Memory) electronic component, are prone to have a shift problem in an FCB (Flip Chip Bonding) process, which results in a Bonding failure (non-join) phenomenon at a low density input-output I/O area metal block (bump).
Disclosure of Invention
The present disclosure provides a semiconductor package device and a method of manufacturing the same.
In a first aspect, the present disclosure provides a semiconductor package device, comprising:
a bridging rewiring layer including a high-density wiring area and a low-density wiring area;
the first electronic element is arranged below the bridging redistribution layer, a first high-density I/O area and a first low-density I/O area are arranged on the active surface of the first electronic element, the first high-density I/O area is electrically connected with the high-density circuit area, and the first low-density I/O area is electrically connected with the low-density circuit area through a routing wire;
and the second electronic element is arranged adjacent to the first electronic element, a second high-density I/O area and a second low-density I/O area are arranged on the active surface of the second electronic element, and the second high-density I/O area is electrically connected with the high-density circuit area.
In some optional embodiments, the second low-density I/O region is electrically connected to the low-density circuit region by wire bonding.
In some optional embodiments, the bridging redistribution layer further includes a via through which a wire bond is connected to the low-density wiring region.
In some optional embodiments, a protective layer is disposed on the bridging redistribution layer corresponding to the through hole, and the protective layer covers the routing passing through the through hole.
In some alternative embodiments, solder balls are disposed on the low-density wiring areas.
In some optional embodiments, a line layer is disposed on the bridging redistribution layer, and the line layer includes a first via hole electrically connected to the bridging redistribution layer.
In some optional embodiments, the circuit layer further comprises a second via electrically connecting the second low density I/O region.
In some optional embodiments, solder balls are disposed on the circuit layer.
In some optional embodiments, an underfill is filled between the first electronic component, the second electronic component and the high-density circuit region.
In some optional embodiments, the apparatus further comprises:
and the packaging layer is arranged below the bridging redistribution layer and wraps the first electronic element and the second electronic element.
In some alternative embodiments, the surface of the encapsulation layer is substantially coplanar with the inactive surface of the first electronic component or the inactive surface of the second electronic component.
In some alternative embodiments, the surface of the encapsulation layer is provided with a heat dissipation layer.
In some optional embodiments, the first high-density I/O region and the high-density wiring region are electrically connected by solder, and the second high-density I/O region and the high-density wiring region are electrically connected by solder.
In some alternative embodiments, the first low density I/O area has a via diameter larger than that of the first high density I/O area, and the second low density I/O area has a via diameter larger than that of the second high density I/O area.
In a second aspect, the present disclosure provides a method of manufacturing a semiconductor package device, including:
providing a bridging redistribution layer, wherein the bridging redistribution layer comprises a high-density line area and a low-density line area;
providing a first electronic element and a second electronic element, wherein the active surface of the first electronic element is provided with a first high-density input-output (I/O) area and a first low-density I/O area, and the active surface of the second electronic element is provided with a second high-density I/O area and a second low-density I/O area;
electrically connecting the first and second high-density I/O regions with the high-density wiring region;
and electrically connecting the first low-density I/O area and the second low-density I/O area with the low-density circuit area through routing.
In some optional embodiments, before the electrically connecting the first low-density I/O region and the second low-density I/O region to the low-density circuit region by wire bonding, the method further includes:
and turning over the bridging rewiring layer.
In a semiconductor package device and a method of manufacturing the same provided in the present disclosure, the semiconductor package device is designed to include: a bridging rewiring layer including a high-density wiring area and a low-density wiring area; the first electronic element is arranged below the bridging redistribution layer, a first high-density I/O area and a first low-density I/O area are arranged on the active surface of the first electronic element, the first high-density I/O area is electrically connected with the high-density circuit area, and the first low-density I/O area is electrically connected with the low-density circuit area through a routing wire; the second electronic element is arranged adjacent to the first electronic element, a second high-density I/O area and a second low-density I/O area are arranged on the active surface of the second electronic element, and the second high-density I/O area is electrically connected with the high-density circuit area; the first low-density I/O area is electrically connected with the low-density circuit area through a routing, so that the problem of welding failure caused by deviation generated when the first low-density I/O area is directly connected with the low-density circuit area through an FCB (flux control bus) process is solved.
Drawings
Other features, objects and advantages of the disclosure will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
fig. 1A is a schematic longitudinal cross-sectional structure of one embodiment of a semiconductor package device according to the present disclosure;
fig. 1B, 1C, 1D, 1E, 1F are schematic longitudinal cross-sectional structures of different embodiments of semiconductor packaging devices according to the present disclosure;
fig. 2A-2H are cross-sectional views of a semiconductor package device fabricated at various stages according to one embodiment of the present disclosure.
Description of the symbols:
11-bridging rewiring layers; 111-high density circuit area; 112-low density circuit area; 113-a via; 12-a first electronic component; 121-a first high density I/O region; 122-first low density I/O region; 13-a second electronic component; 131-a second high density I/O region; 132-a second low density I/O region; 14-a line layer; 141-a first via hole; 142-a second via hole; 15-solder balls; 16-an encapsulation layer; 17-a heat dissipation layer; 18-routing; 19-underfill; 20-a protective layer; 21-a carrier plate; 22-seed layer;
Detailed Description
The following description of the embodiments of the present disclosure will be provided in conjunction with the accompanying drawings and examples, and those skilled in the art can easily understand the technical problems and effects of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. In addition, for convenience of description, only portions related to the related invention are shown in the drawings.
It should be noted that the structures, proportions, and dimensions shown in the drawings and described in the specification are for the understanding and reading of the present disclosure, and are not intended to limit the conditions under which the present disclosure can be implemented, so they are not technically significant, and any modifications of the structures, changes in the proportions and adjustments of the dimensions should be made without affecting the efficacy and attainment of the same. In addition, the terms "above", "first", "second" and "a" as used herein are for the sake of clarity only, and are not intended to limit the scope of the present disclosure, and changes or modifications of the relative relationship may be made without substantial changes in the technical content.
It should also be noted that the longitudinal section corresponding to the embodiment of the present disclosure may be a front view direction section, the transverse section may be a right view direction section, and the horizontal section may be a top view direction section.
In addition, the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Referring to fig. 1A, fig. 1A is a schematic longitudinal cross-sectional structure of one embodiment of a semiconductor package device according to the present disclosure.
As shown in fig. 1A, the semiconductor package device 100A may include: bridging the redistribution layer 11, the first electronic component 12, and the second electronic component 13. Wherein:
the bridging redistribution layer 11 includes a high-density wiring region 111 and a low-density wiring region 112.
The bridging redistribution Layer 11 may be a redistribution Layer (RDL) composed of conductive traces and Dielectric material (Dielectric). It should be noted that, currently known or future developed redistribution layer forming techniques may be adopted in the manufacturing process, and the disclosure is not limited thereto, and for example, the redistribution layer may be formed by using processes including but not limited to photolithography, electroplating (plating), Electroless plating (electroplating), and the like. Here, the dielectric material may include organic and/or inorganic substances, wherein the organic substance may be, for example: polyamide fibers (Polyamide, PA), Polyimide (PI), Epoxy resins (Epoxy), Poly-p-Phenylene Benzobisoxazole (PBO) fibers, FR-4 Epoxy glass cloth laminates, PP (preprg, PrePreg or so-called PrePreg, PrePreg), ABF (Ajinomoto Build-up Film), etc., and inorganic substances such as silicon (Si), glass (glass), ceramic (ceramic), silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material may include a seed layer and a metal layer. Here, the seed layer may be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., and the metal layer may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or an alloy thereof.
The bridging redistribution layer 11 may also include interconnect structures (interconnections), such as Conductive traces (Conductive traces), Conductive vias (Conductive vias), and the like. Here, the conductive via may be a through hole, a buried hole, or a blind hole, and the through hole, the buried hole, or the blind hole may be filled with a conductive material such as a metal or a metal alloy, where the metal may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or an alloy thereof.
Here, the density of the high-density wiring area 111 and the low-density wiring area 112 may include the I/O number density of the rewiring layer. In the present disclosure, the I/O may include conductive vias.
The first electronic element 12 is disposed below the bridging redistribution layer 11, the active surface of the first electronic element 12 is provided with a first high-density I/O area 121 and a first low-density I/O area 122, the first high-density I/O area 121 is electrically connected to the high-density circuit area 111, and the first low-density I/O area 122 is electrically connected to the low-density circuit area 112 through a wire bonding 18.
And a second electronic component 13 disposed adjacent to the first electronic component 12, wherein an active surface of the second electronic component 13 is provided with a second high-density I/O area 131 and a second low-density I/O area 132, and the second high-density I/O area 131 is electrically connected to the high-density wiring area 111.
The types of the first electronic component 12 and the second electronic component 13 are not particularly limited in this disclosure, the first electronic component 12 and the second electronic component 13 may be the same type or different types of electronic components, and the first electronic component 12 and the second electronic component 13 may include, for example, a die (die), an ASIC (Application Specific Integrated Circuit) chip, a Power Management Circuit (PMIC) chip, or an HBM (High Bandwidth Memory) chip.
In some alternative embodiments, as shown in fig. 1A, the second low density I/O area 132 is electrically connected to the low density circuit area 112 by bonding wires 18.
In some alternative embodiments, as shown in fig. 1A, the bridging redistribution layer 11 further includes a via 113, and the wire 18 is connected to the low-density wiring region 112 through the via 113.
In some alternative embodiments, the first high-density I/O region 121 and the high-density wiring region 111 are electrically connected by solder, and the second high-density I/O region 131 and the high-density wiring region 111 are electrically connected by solder.
In some alternative embodiments, the via diameter of the first low-density I/O area 122 is larger than that of the first high-density I/O area 121, and the via diameter of the second low-density I/O area 132 is larger than that of the second high-density I/O area 131.
In some alternative embodiments, as shown in fig. 1A, the bridging redistribution layer 11 is provided with a line layer 14, the line layer 14 includes a first via 141, and the first via 141 is electrically connected to the bridging redistribution layer 11.
The wiring layer 14 may be a wiring layer or a redistribution layer composed of conductive traces and Dielectric material (Dielectric). It should be noted that, currently known or future developed redistribution layer forming techniques may be adopted in the manufacturing process, and the disclosure is not limited thereto, and for example, the redistribution layer may be formed by using processes including but not limited to photolithography, electroplating (plating), Electroless plating (electroplating), and the like. Here, the dielectric material may include organic and/or inorganic substances, wherein the organic substance may be, for example: polyamide fiber (PA), PI, Epoxy resin (Epoxy), Poly-p-Phenylene Benzobisoxazole (PBO) fiber, FR-4 Epoxy glass cloth laminate, PP, ABF, etc., and inorganic substances may be, for example, silicon (Si), glass (glass), ceramic (ceramic), silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material may include a seed layer and a metal layer. Here, the seed layer may be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., and the metal layer may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or an alloy thereof.
The line layer 14 may also include interconnect structures (interconnects), such as Conductive traces (Conductive traces), Conductive vias (Conductive vias), and the like. Here, the conductive via may be a through hole, a buried hole, or a blind hole, and the through hole, the buried hole, or the blind hole may be filled with a conductive material such as a metal or a metal alloy, where the metal may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or an alloy thereof.
In some alternative embodiments, as shown in fig. 1A, solder balls 15 are disposed on the wiring layer 14.
In some alternative embodiments, as shown in fig. 1A, an underfill 19 is filled between the first electronic component 12, the second electronic component 13 and the high-density circuit region 111.
In some alternative embodiments, as shown in fig. 1A, the semiconductor package apparatus 100A further includes: and an encapsulating layer 16 disposed below the bridging redistribution layer 11 and encapsulating the first electronic element 12 and the second electronic element 13.
The encapsulation layer 16 may be formed of various Molding compounds (Molding compounds). For example, the molding material may include Epoxy resin (Epoxy resin), Filler (Filler), Catalyst (Catalyst), Pigment (Pigment), Release Agent (Release Agent), Flame Retardant (Flame Retardant), Coupling Agent (Coupling Agent), Hardener (hardner), Low Stress absorbent (Low Stress Absorber), Adhesion Promoter (Adhesion Promoter), Ion trap (Ion Trapping Agent), and the like.
Referring now to fig. 1B, fig. 1B is a schematic diagram of a longitudinal cross-sectional structure of one embodiment 100B of a semiconductor package device according to the present disclosure. The semiconductor package device 100B shown in fig. 1B is similar to the semiconductor package device 100A shown in fig. 1A, except that in the semiconductor package device 100B, the surface of the encapsulation layer 16 is substantially coplanar with the inactive surface of the first electronic component 12.
Here, two surfaces being substantially coplanar can be considered to be: the difference in height between the two surfaces is no greater than 5 micrometers (μm), no greater than 2 micrometers (μm), no greater than 1 micrometer (μm), or no greater than 0.5 micrometers (μm).
In some alternative embodiments, the surface of the encapsulation layer 16 is substantially coplanar with the inactive side of the first electronic component 12 or the inactive side of the second electronic component 13.
Referring now to fig. 1C, fig. 1C is a schematic diagram of a longitudinal cross-sectional structure of one embodiment 100C of a semiconductor package device according to the present disclosure. The semiconductor package device 100C shown in fig. 1C is similar to the semiconductor package device 100A shown in fig. 1A, except that in the semiconductor package device 100C, a heat dissipation layer 17 is provided on the surface of the encapsulation layer 16. In some alternative embodiments, the heat dissipation layer 17 is disposed against the inactive side of the first electronic component 12. The heat dissipation layer 17 can conduct heat with the package layer 16 and the first electronic component 12, thereby improving the heat dissipation performance of the semiconductor package device.
Referring now to fig. 1D, fig. 1D is a schematic diagram of a longitudinal cross-sectional structure of one embodiment 100D of a semiconductor package device according to the present disclosure. The semiconductor packaging apparatus 100D shown in fig. 1D is similar to the semiconductor packaging apparatus 100A shown in fig. 1A, except that in the semiconductor packaging apparatus 100D, the bridging redistribution layer 11 is further provided with the same structure as the bridging redistribution layer 11, the first electronic element 12 and the second electronic element 13 in the extending direction, and the structure of the bridging redistribution layer 11 in the extending direction corresponds to the structure shown in fig. 1A, and is not described again here.
Referring now to fig. 1E, fig. 1E is a schematic diagram of a longitudinal cross-sectional structure of one embodiment 100E of a semiconductor package device according to the present disclosure. The semiconductor package device 100E shown in fig. 1E is similar to the semiconductor package device 100A shown in fig. 1A, except that in the semiconductor package device 100E, the circuit layer 14 further includes a second via 142, and the second via 142 is electrically connected to the second low-density I/O region 132.
Referring now to fig. 1F, fig. 1F is a schematic diagram of a longitudinal cross-sectional structure of one embodiment 100F of a semiconductor package device according to the present disclosure. The semiconductor package device 100F shown in fig. 1F is similar to the semiconductor package device 100A shown in fig. 1A, except that in the semiconductor package device 100F, a protection layer 20 is disposed on the bridging redistribution layer 11 corresponding to the through hole, and the protection layer 20 covers the bonding wire 18 passing through the through hole; the low-density wiring region 112 is provided with solder balls 15.
The protective layer 20 may comprise liquid and/or thin film organics such as: non-conductive adhesive (Non-conductive Plastic, NCP), Non-conductive Film (NCF), Anisotropic Conductive Film (ACF), anisotropic conductive Adhesive (ACP), PI, Epoxy, resin (resin), PP, ABF, adhesive (glue), and the like.
Referring now to fig. 2A through 2H, fig. 2A through 2H are schematic longitudinal cross-sectional structural views of semiconductor package devices 200A, 200B, 200C, 200D, 200E, 200F, 200G, and 200H fabricated at various stages according to one embodiment of the present disclosure.
Referring to fig. 2A, a carrier board 21 is provided, and a bridging rewiring layer 11 is disposed on the carrier board 21.
The bridging redistribution layer 11 includes a high-density circuit region 111 and a low-density circuit region 112, and is provided with a via 113.
Referring to fig. 2B, a first electronic component 12 and a second electronic component 13 are provided, the active surface of the first electronic component 12 is provided with a first high-density I/O area 121 and a first low-density I/O area 122, and the active surface of the second electronic component 13 is provided with a second high-density I/O area 131 and a second low-density I/O area 132.
The first high-density I/O area 121 of the first electronic element 12 and the second high-density I/O area 131 of the second electronic element 13 are bonded to the high-density wiring area 111, so that the first high-density I/O area 121 and the second high-density I/O area 131 are electrically connected to the high-density wiring area 111.
For example, Flip Chip Bonding (FCB), Thermal Compression Bonding (TCB), or the like may be used for the electrical connection process.
The first low-density I/O area and the second low-density I/O area are electrically connected with the low-density circuit area through a routing.
Referring to fig. 2C, an underfill 19 is filled between the first electronic component 12, the second electronic component 13, and the high-density wiring region 111.
Referring to fig. 2D, molding is performed to form an encapsulation layer 16, and the encapsulation layer 16 encapsulates the first electronic element 12 and the second electronic element 13.
Referring to fig. 2E, the carrier plate 21 is removed after being flipped.
Referring to fig. 2F, the first low density I/O area 122 and the second low density I/O area 132 are electrically connected to the low density wiring area 112 by wire bonding 18.
Referring to fig. 2G, a line layer 14 is provided on the bridging rewiring layer 11, and the line layer 14 includes a first via hole 141, and the first via hole 141 electrically connects the bridging rewiring layer 11.
Referring to fig. 2H, solder balls 15 are disposed on the wiring layer 14.
The method for manufacturing the semiconductor structure provided by the present disclosure can achieve similar technical effects to the aforementioned semiconductor structure, and is not described herein again.
While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof within the embodiments without departing from the true spirit and scope of the disclosure as defined by the appended claims. The illustrations may not be drawn to scale. There may be a difference between the technical reproduction and the actual implementation in the present disclosure due to variables in the manufacturing process, and the like. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present disclosure.

Claims (10)

1. A semiconductor package device, comprising:
a bridging rewiring layer including a high-density wiring area and a low-density wiring area;
the first electronic element is arranged below the bridging redistribution layer, a first high-density input-output (I/O) area and a first low-density I/O area are arranged on the active surface of the first electronic element, the first high-density I/O area is electrically connected with the high-density circuit area, and the first low-density I/O area is electrically connected with the low-density circuit area through a routing wire;
and the second electronic element is arranged adjacent to the first electronic element, a second high-density I/O area and a second low-density I/O area are arranged on the active surface of the second electronic element, and the second high-density I/O area is electrically connected with the high-density circuit area.
2. The apparatus of claim 1, wherein the second low density I/O region is electrically connected to the low density circuit region by wire bonding.
3. The apparatus of claim 1 or 2, wherein the bridging redistribution layer further comprises vias through which wire bonds connect the low density wiring regions.
4. The apparatus of claim 3, wherein a protective layer is disposed on the bridging redistribution layer corresponding to the via, the protective layer covering a wire bond passing through the via.
5. The apparatus of claim 4, wherein solder balls are disposed on the low density wiring areas.
6. The device of claim 1, wherein a line layer is disposed on the bridging redistribution layer, the line layer including a first via electrically connecting the bridging redistribution layer.
7. The apparatus of claim 6, wherein the wiring layer further comprises a second via electrically connecting the second low density I/O region.
8. The apparatus of claim 6, wherein solder balls are disposed on the wiring layer.
9. The device of claim 1, wherein an underfill is filled between the first electronic component, the second electronic component and the high-density wiring region.
10. The apparatus of claim 1, wherein the first low density I/O area has a via diameter larger than the first high density I/O area, and the second low density I/O area has a via diameter larger than the second high density I/O area.
CN202111295022.1A 2021-11-03 2021-11-03 Semiconductor package device and method of manufacturing the same Pending CN114050147A (en)

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CN202111295022.1A CN114050147A (en) 2021-11-03 2021-11-03 Semiconductor package device and method of manufacturing the same

Applications Claiming Priority (1)

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CN202111295022.1A CN114050147A (en) 2021-11-03 2021-11-03 Semiconductor package device and method of manufacturing the same

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