CN114050131A - Semiconductor packaging device - Google Patents

Semiconductor packaging device Download PDF

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Publication number
CN114050131A
CN114050131A CN202111213555.0A CN202111213555A CN114050131A CN 114050131 A CN114050131 A CN 114050131A CN 202111213555 A CN202111213555 A CN 202111213555A CN 114050131 A CN114050131 A CN 114050131A
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CN
China
Prior art keywords
chip
circuit layer
barrier structure
present disclosure
layer
Prior art date
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Pending
Application number
CN202111213555.0A
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Chinese (zh)
Inventor
柯伯贤
李德章
洪志斌
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Filing date
Publication date
Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Priority to CN202111213555.0A priority Critical patent/CN114050131A/en
Publication of CN114050131A publication Critical patent/CN114050131A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/54—Providing fillings in containers, e.g. gas fillings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

Abstract

The present disclosure relates to a semiconductor package device, including: a circuit layer; the first chip and the second chip are adjacently arranged on the circuit layer; and the barrier structure is arranged on the circuit layer and positioned between the first chip and the second chip, and the upper surface of the barrier structure is higher than the upper surface of the first chip, or the upper surface of the barrier structure is basically coplanar with the upper surface of the first chip.

Description

Semiconductor packaging device
Technical Field
The present disclosure relates to the field of semiconductor packaging technology, and more particularly, to a semiconductor packaging apparatus.
Background
In the FOCoS (FanOut Chip on Substrate) structure, because of the difference in thermal expansion coefficient of each material structure, thermal stress is generated during thermal cycling, so that it is not able to bear the stress, and cracks (crack) or damages (delam) are easily generated between the underfill (Under fill) and the HBM (High Bandwidth Memory) Chip.
Disclosure of Invention
The present disclosure provides a semiconductor package device and a method of manufacturing the same.
In a first aspect, the present disclosure provides a semiconductor package device, comprising:
a circuit layer;
the first chip and the second chip are adjacently arranged on the circuit layer;
and the barrier structure is arranged on the circuit layer and positioned between the first chip and the second chip, and the upper surface of the barrier structure is higher than the upper surface of the first chip, or the upper surface of the barrier structure is basically coplanar with the upper surface of the first chip.
In some optional embodiments, the apparatus further comprises:
an underfill disposed between the first chip, the barrier structure, and the line layer.
In some optional embodiments, the apparatus further comprises:
and the packaging material is arranged on the circuit layer and coats the first chip, the second chip and the blocking structure.
In some optional embodiments, the encapsulation material is partially disposed between the second chip and the blocking structure.
In some alternative embodiments, the material of the encapsulation material is the same as the encapsulation material of the second chip.
In some optional embodiments, an upper surface of the first chip is exposed through the encapsulation material.
In some optional embodiments, an upper surface of the second chip is exposed through the encapsulant.
In some alternative embodiments, the upper surface of the first chip and the upper surface of the second chip are substantially coplanar.
In some optional embodiments, the apparatus further comprises:
and the electric connector is arranged below the circuit layer and is electrically connected with the circuit layer.
In some optional embodiments, the apparatus further comprises:
and the substrate is arranged below the circuit layer and is electrically connected with the circuit layer.
In some optional embodiments, the routing layer comprises a redistribution layer.
In a second aspect, the present disclosure provides a method of manufacturing a semiconductor package device, including:
providing a circuit layer;
arranging a blocking structure on the circuit layer;
and respectively arranging a first chip and a second chip on the circuit layer and on two sides of the blocking structure, wherein the upper surface of the blocking structure is higher than the upper surface of the first chip, or the upper surface of the blocking structure is substantially coplanar with the upper surface of the first chip.
In some optional embodiments, the method further comprises:
an underfill is disposed between the first chip, the barrier structure, and the wiring layer.
In some optional embodiments, the method further comprises:
and molding to form a packaging material, wherein the packaging material coats the first chip, the second chip and the barrier structure.
In a semiconductor package device and a method of manufacturing the same provided in the present disclosure, the semiconductor package device is designed to include: a circuit layer; the first chip and the second chip are adjacently arranged on the circuit layer; the blocking structure is arranged on the circuit layer and positioned between the first chip and the second chip, and the upper surface of the blocking structure is higher than the upper surface of the first chip, or the upper surface of the blocking structure is basically coplanar with the upper surface of the first chip; the blocking structure is arranged between the first chip and the second chip, and the upper surface of the blocking structure is not lower than the upper surface of the first chip, so that when the underfill is arranged on the side of the first chip, the blocking structure can block the underfill from contacting the second chip, and further, the second chip and the underfill are prevented from being cracked or damaged due to different thermal expansion coefficients in a thermal cycle manufacturing process.
Drawings
Other features, objects and advantages of the disclosure will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
fig. 1 is a schematic longitudinal cross-sectional structure of one embodiment of a semiconductor package device according to the present disclosure;
fig. 2A-2H are schematic longitudinal cross-sectional structural views of a semiconductor package device fabricated at various stages according to one embodiment of the present disclosure.
Description of the symbols:
11-a line layer; 12-a first chip; 13-a second chip; 14-a barrier structure; 15-underfill; 16-packaging material; 17-electrical connections; 18-a substrate; 21-carrier plate.
Detailed Description
The following description of the embodiments of the present disclosure will be provided in conjunction with the accompanying drawings and examples, and those skilled in the art can easily understand the technical problems and effects of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. In addition, for convenience of description, only portions related to the related invention are shown in the drawings.
It should be noted that the structures, proportions, and dimensions shown in the drawings and described in the specification are for the understanding and reading of the present disclosure, and are not intended to limit the conditions under which the present disclosure can be implemented, so they are not technically significant, and any modifications of the structures, changes in the proportions and adjustments of the dimensions should be made without affecting the efficacy and attainment of the same. In the present specification, the terms "upper", "first", "second" and "first" are used for clarity of description only, and are not intended to limit the scope of the present disclosure, and changes or modifications in relative relationships thereof should be construed as being within the scope of the present disclosure without substantial technical changes.
It should also be noted that the longitudinal section corresponding to the embodiment of the present disclosure may be a front view direction section, the transverse section may be a right view direction section, and the horizontal section may be a top view direction section.
In addition, the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Referring to fig. 1, fig. 1 is a schematic longitudinal cross-sectional structure of one embodiment of a semiconductor package device according to the present disclosure.
As shown in fig. 1, the semiconductor package device 100A may include: line layer 11, first chip 12, second chip 13 and barrier structure 14. Wherein:
the wiring Layer 11 may be a wiring Layer or a redistribution Layer (RDL) composed of conductive traces and Dielectric material (Dielectric). It should be noted that, currently known or future developed redistribution layer forming techniques may be adopted in the manufacturing process, and the disclosure is not limited thereto, and for example, the redistribution layer may be formed by using processes including but not limited to photolithography, electroplating (plating), Electroless plating (electroplating), and the like. Here, the dielectric material may include organic and/or inorganic substances, wherein the organic substance may be, for example: polyamide fibers (Polyamide, PA), Polyimide (PI), Epoxy resins (Epoxy), Poly-p-Phenylene Benzobisoxazole (PBO) fibers, FR-4 Epoxy glass cloth laminates, PP (preprg, PrePreg or so-called PrePreg, PrePreg), ABF (Ajinomoto Build-up Film), etc., and inorganic substances such as silicon (Si), glass (glass), ceramic (ceramic), silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material may include a seed layer and a metal layer. Here, the seed layer may be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., and the metal layer may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or an alloy thereof.
The first chip 12 and the second chip 13 are adjacently disposed on the circuit layer 11.
Here, the first chip 12 may include an ASIC (Application Specific Integrated Circuit) chip, and the second chip 13 may include an HBM (High Bandwidth Memory) chip.
And the barrier structure 14 is arranged on the circuit layer 11 and located between the first chip 12 and the second chip 13, and an upper surface of the barrier structure 14 is higher than an upper surface of the first chip 12, or the upper surface of the barrier structure 14 is substantially coplanar with the upper surface of the first chip 12.
Here, two surfaces being substantially coplanar can be considered to be: the difference in height between the two surfaces is no greater than 5 micrometers (μm), no greater than 2 micrometers (μm), no greater than 1 micrometer (μm), or no greater than 0.5 micrometers (μm).
The barrier structure 14 is capable of providing a barrier between the first chip 12 and the second chip 13. The material of the barrier structure 14 is not particularly limited in the present disclosure, and the barrier function can be achieved. In some alternative implementations, the material of the barrier structure 14 may include grains (die).
In some alternative embodiments, as shown in fig. 1, the semiconductor package device 100A may further include: an underfill 15.
And an underfill 15 disposed between the first chip 12, the barrier structure 14 and the circuit layer 11.
The blocking structure 14 can block the underfill 15 from contacting the second chip 13, so as to prevent the underfill 15 from contacting the package material of the second chip 13, and further prevent the underfill 15 from being cracked or damaged due to the different thermal expansion coefficients of the underfill 15 and the package material of the second chip 13 in the thermal cycle process.
In some alternative embodiments, as shown in fig. 1, the semiconductor package device 100A may further include: and a sealing material 16.
And the packaging material 16 is arranged on the circuit layer 11 and covers the first chip 12, the second chip 13 and the barrier structure 14.
The potting material 16 may be formed of various Molding compounds (Molding compounds). For example, the molding material may include Epoxy resin (Epoxy resin), Filler (Filler), Catalyst (Catalyst), Pigment (Pigment), Release Agent (Release Agent), Flame Retardant (Flame Retardant), Coupling Agent (Coupling Agent), Hardener (hardner), Low Stress absorbent (Low Stress Absorber), adhesion promoter (adhesion promoter), ion trap (ion trapping Agent), and the like.
In some alternative embodiments, as shown in fig. 1, the encapsulant 16 is partially disposed between the second chip 13 and the blocking structure 14.
The material of the encapsulating material 16 is the same as that of the second chip 13.
It is understood that the HBM chip surface includes an encapsulation material, where the encapsulation material may be formed of various molding materials.
When the material of the encapsulant 16 is the same as the encapsulant of the second chip 13, the thermal expansion coefficients of the two are also the same, so that the cracking or damage caused by the difference of the thermal expansion coefficients of the different materials in the thermal cycle process can be avoided.
In some alternative embodiments, as shown in fig. 1, the upper surface of the first chip 12 is exposed through the encapsulant 16.
In some alternative embodiments, as shown in fig. 1, the upper surface of the second chip 13 is exposed through the packaging material 16.
In some alternative embodiments, as shown in fig. 1, the upper surface of the first chip 12 and the upper surface of the second chip 13 are substantially coplanar.
In some alternative embodiments, as shown in fig. 1, the semiconductor package device 100A may further include: an electrical connection 17.
And the electric connector 17 is arranged below the circuit layer 11 and is electrically connected with the circuit layer 11.
Here, the electrical connection member 17 may include a Solder ball (Solder ball), a Solder bump (Solder bump), a Conductive Pillar (Conductive Pillar), a Pad (Solder Pad), or the like.
In some alternative embodiments, as shown in fig. 1, the semiconductor package device 100A may further include: a substrate 18.
And a substrate 18 disposed under the circuit layer 11 and electrically connected to the circuit layer 11.
The substrate 18 may be a substrate composed of a conductive material and a Dielectric material (Dielectric). Here, the dielectric material may include organic and/or inorganic substances, wherein the organic substance may be, for example: polyamide fibers (Polyamide, PA), Polyimide (PI), Epoxy resins (Epoxy), Poly-p-Phenylene Benzobisoxazole (PBO) fibers, FR-4 Epoxy glass cloth laminates, PP (preprg, PrePreg or so-called PrePreg, PrePreg), ABF (Ajinomoto Build-up Film), etc., and inorganic substances such as silicon (Si), glass (glass), ceramic (ceramic), silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material may include a seed layer and a metal layer. Here, the seed layer may be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., and the metal layer may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or an alloy thereof.
Here, as shown in fig. 1, the substrate 18 may be electrically connected to the wiring layer 11 through an electrical connector 17.
The embodiment of the disclosure also provides a manufacturing method of the semiconductor packaging device. Fig. 2A-2H are schematic longitudinal cross-sectional structural views of semiconductor package devices 200A, 200B, 200C, 200D, 200E, 200F, 200G, and 200H fabricated at various stages according to one embodiment of the present disclosure.
Referring to fig. 2A, a carrier board 21 is provided, and a wiring layer 11 is disposed on the carrier board 21.
Referring to fig. 2B, a barrier structure 14 is provided, and the barrier structure 14 is disposed on the line layer 11.
Here, the barrier structure 14 may be attached on the wiring layer 11.
Referring to fig. 2C, a first chip 12 and a second chip 13 are provided.
The first chip 12 and the second chip 13 are disposed on the wiring layer 11 and located on both sides of the barrier structure 14.
Here, the upper surface of the barrier structure 14 is higher than the upper surface of the first chip 12, or the upper surface of the barrier structure 14 is substantially coplanar with the upper surface of the first chip 12.
Referring to fig. 2D, an underfill 15 is disposed between the first chip 12, the barrier structure 14, and the wiring layer 11.
Here, the Underfill 15 may be provided between the first chip 12, the barrier structure 14, and the wiring layer 11 by Capillary Underfill (CUF).
Referring to fig. 2E, the encapsulant 16 is formed by molding, wherein the encapsulant 16 encapsulates the first chip 12, the second chip 13 and the blocking structure 14.
Here, the thickness of the encapsulation material 16 may be reduced by a thinning process (e.g., grinding or etching, etc.) to expose the upper surfaces of the first chip 12 and the second chip 13.
Referring to fig. 2F, carrier plate 21 is removed.
Referring to fig. 2G, the semiconductor package device 200F is flipped over, the electrical connector 17 is disposed on the wiring layer 11, and the electrical connector 17 is electrically connected to the wiring layer 11.
Referring to fig. 2H, first, the substrate 18 is disposed on the wiring layer 11, and the substrate 18 is electrically connected to the electrical connector 17.
Then, the semiconductor package device 200H is turned over.
For example, Flip Chip Bonding (FCB), Thermal Compression Bonding (TCB), or the like may be used for the electrical connection process
The method for manufacturing the semiconductor structure provided by the present disclosure can achieve similar technical effects to the aforementioned semiconductor structure, and is not described herein again.
While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof within the embodiments without departing from the true spirit and scope of the disclosure as defined by the appended claims. The illustrations may not be drawn to scale. There may be a difference between the technical reproduction and the actual implementation in the present disclosure due to variables in the manufacturing process, and the like. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present disclosure.

Claims (10)

1. A semiconductor package device, comprising:
a circuit layer;
the first chip and the second chip are adjacently arranged on the circuit layer;
and the barrier structure is arranged on the circuit layer and positioned between the first chip and the second chip, and the upper surface of the barrier structure is higher than the upper surface of the first chip, or the upper surface of the barrier structure is basically coplanar with the upper surface of the first chip.
2. The apparatus of claim 1, wherein the apparatus further comprises:
an underfill disposed between the first chip, the barrier structure, and the line layer.
3. The apparatus of claim 2, wherein the apparatus further comprises:
and the packaging material is arranged on the circuit layer and coats the first chip, the second chip and the blocking structure.
4. The apparatus of claim 3, wherein the encapsulant portion is disposed between the second chip and the blocking structure.
5. The apparatus of claim 3, wherein the encapsulant is the same material as the encapsulant of the second chip.
6. The apparatus of claim 3, wherein an upper surface of the first chip is exposed through the encapsulant.
7. The apparatus of claim 3, wherein an upper surface of the second chip is exposed through the encapsulant.
8. The apparatus of claim 1, wherein an upper surface of the first chip and an upper surface of the second chip are substantially coplanar.
9. The apparatus of claim 1, wherein the apparatus further comprises:
and the electric connector is arranged below the circuit layer and is electrically connected with the circuit layer.
10. The apparatus of claim 1, wherein the apparatus further comprises:
and the substrate is arranged below the circuit layer and is electrically connected with the circuit layer.
CN202111213555.0A 2021-10-19 2021-10-19 Semiconductor packaging device Pending CN114050131A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111213555.0A CN114050131A (en) 2021-10-19 2021-10-19 Semiconductor packaging device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111213555.0A CN114050131A (en) 2021-10-19 2021-10-19 Semiconductor packaging device

Publications (1)

Publication Number Publication Date
CN114050131A true CN114050131A (en) 2022-02-15

Family

ID=80205656

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111213555.0A Pending CN114050131A (en) 2021-10-19 2021-10-19 Semiconductor packaging device

Country Status (1)

Country Link
CN (1) CN114050131A (en)

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