CN112420845A - Trench power semiconductor device and manufacturing method - Google Patents
Trench power semiconductor device and manufacturing method Download PDFInfo
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H—ELECTRICITY
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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Abstract
The invention relates to a trench power semiconductor device, wherein a drain metal is provided with a first conductive type substrate and a first conductive type epitaxial layer, the first conductive type epitaxial layer is provided with a second conductive type body region and a second conductive type well region, the second conductive type body region is internally provided with a first type trench, the second conductive type well region is internally provided with a second type trench, the second type trench is arranged around the first type trench, and the concentration peak value of a second conductive type impurity of the second conductive type body region is greater than that of the second conductive type impurity of the second conductive type well region.
Description
Technical Field
The invention relates to a power semiconductor structure and a manufacturing method thereof, in particular to a common groove power semiconductor structure and a manufacturing method thereof.
Background
As shown in fig. 13, which is a schematic diagram of a conventional trench power MOSFET structure, the conventional structure includes a cell region 001 and a terminal protection region 002, the cell region 001 is located in a central region of the device, the terminal protection region 002 is disposed around the cell region 001, and a second conductivity type body region 7 is disposed on the surface of the first conductivity type epitaxial layer 3 of each of the cell region 001 and the terminal protection region 002. Fig. 13 shows the breakdown position of the device when it is subjected to the breakdown voltage, the breakdown point is located on the side of the second-type trench 14 closest to the cell region 001 near the cell region 001, the breakdown point is extremely close to the second-type gate oxide layer 16, and the peak electric field is extremely high due to the high impurity concentration of the second conductivity-type body region 7, which easily causes damage to the gate oxide layer, resulting in a decrease in the withstand voltage of the device and a decrease in reliability.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a trench power semiconductor device and a manufacturing method thereof, wherein the trench power semiconductor device can improve the terminal withstand voltage and the reliability.
According to the technical scheme provided by the invention, the trench power semiconductor device comprises drain electrode metal, a semiconductor substrate, a first type of trench, first type of conductive polysilicon, a first type of gate oxide layer, a second type of conductive body region, a first type of conductive source region, a second type of insulating dielectric layer, a first type of insulating dielectric layer, a second type of conductive well region, source electrode metal, a metal field plate, a second type of trench, second type of conductive polysilicon and a second type of gate oxide layer;
the semiconductor substrate is arranged on the drain metal and divided into a cellular area and a terminal protection area, the cellular area is located in the central area of the semiconductor substrate, and the terminal protection area is located on the outer ring of the cellular area and surrounds the cellular area; the semiconductor substrate comprises a first conductive type substrate and a first conductive type epitaxial layer positioned on the first conductive type substrate;
a second conduction type body region and a second conduction type well region are arranged on the first conduction type epitaxial layer, the second conduction type body region completely covers the first conduction type epitaxial layer in the cellular region, the second conduction type well region completely or partially covers the first conduction type epitaxial layer in the terminal protection region, a first conduction type source region is arranged in the second conduction type body region, and a first type insulating medium layer is arranged on the second conduction type well region;
a first-class groove is formed in the upper surface of the first conduction type source region, penetrates through the first conduction type source region and the second conduction type body region downwards and finally extends into the first-class conduction type epitaxial layer, a first-class gate oxide layer is formed on the side wall and the bottom wall of the first-class groove, and first-class conductive polycrystalline silicon is arranged in the first-class gate oxide layer;
a second groove is formed in the upper surface of the second conduction type well region in a downward mode, the second groove penetrates through the second conduction type well region downwards and finally extends into the first conduction type epitaxial layer, a second gate oxide layer is arranged on the side wall and the bottom wall of the second groove, and second conduction polycrystalline silicon is arranged in the second gate oxide layer;
the source electrode metal is in ohmic contact with the first conduction type source region and the second conduction type body region through the through hole, the metal field plate is completely positioned in the terminal protection region and at least covers one second type groove, and the metal field plate is connected with a source electrode potential or a grid electrode potential.
Preferably, the second conductive-type body region not only completely covers the first conductive-type epitaxial layer located in the cell region but also partially extends into the termination protection region and covers the first conductive-type epitaxial layer near the cell region, a first conduction type source region is arranged on the second conduction type body region positioned in the cellular region, the second conduction type well region covers the first conduction type epitaxial layer at the outer side of the second conduction type body region, the first insulation medium layer not only completely covers the second conduction type well region but also covers the edge part of the second conduction type body region positioned in the terminal protection region, and a second type insulating medium layer is arranged on the first type insulating medium layer, the non-edge part of the second type conducting body region positioned in the terminal protection region and the first type insulating medium layer, and the source metal is in ohmic contact with the second type conducting body region extending into the terminal protection region through a through hole in the second type insulating medium layer.
Preferably, the second conductivity type body region completely covers not only the first conductivity type epitaxial layer located in the cell region but also the second conductivity type body region partially extends into the terminal protection region and covers the first conductivity type epitaxial layer near the cell region, the first conductivity type source region completely covers not only the second conductivity type body region located in the cell region but also partially extends into the terminal protection region and partially covers the second conductivity type body region near the cell region, the second conductivity type well region covers the first conductivity type epitaxial layer outside the second conductivity type body region, the first type insulating dielectric layer completely covers not only the second conductivity type well region but also the edge portion of the second conductivity type body region located in the terminal protection region, the second type insulating dielectric layer is provided on the first conductivity type source region and the first type insulating dielectric layer, and the source metal passes through the through hole in the second type insulating dielectric layer and the second conductivity type body region extending into the terminal protection region, The first conductive type source region is in ohmic contact.
Preferably, the second conductive type body region completely covers the first conductive type epitaxial layer in the cell region, the second conductive type well region completely covers the first conductive type epitaxial layer in the terminal protection region, the first insulating medium layer completely covers the second conductive type well region, the second insulating medium layer is arranged on the first conductive type source region and the first insulating medium layer, the first trench is arranged in the second conductive type well region in the terminal protection region close to the cell region, through holes are arranged on two sides of the first trench, and the source metal is in ohmic contact with the second conductive type well region through the through holes.
Preferably, a concentration peak of the second conductivity type impurity of the second conductivity type body region is larger than a concentration peak of the second conductivity type impurity of the second conductivity type well region.
Preferably, the first type of conductive polysilicon in the first type of trench is connected with the gate potential, and the second type of conductive polysilicon in the second type of trench is arranged in a floating manner.
Preferably, the power semiconductor device is an N-type power semiconductor device or a P-type power semiconductor device, and when the power semiconductor device is an N-type power semiconductor device, the first conductivity type is an N-type, and the second conductivity type is a P-type; when the power semiconductor device is a P-type semiconductor device, the first conductivity type is P-type and the second conductivity type is N-type.
The manufacturing method of the trench power semiconductor device comprises the following steps:
the method comprises the following steps: providing a first conductive type substrate, and growing a first conductive type epitaxial layer on the first conductive type substrate;
step two: implanting second conductive type impurities into the first conductive type epitaxial layer, and annealing to form a second conductive type well region;
step three: selectively etching the grooves to form a first type groove and a second type groove; thermally growing to form a first gate oxide layer and a second gate oxide layer; depositing conductive polysilicon; etching and reserving the first type of conductive polysilicon in the first type of groove and the second type of conductive polysilicon in the second type of groove;
step four: depositing a first type of insulating medium layer;
step five: selectively etching and removing the first type insulating medium layer in the cellular region and the first type insulating medium layer in part of the terminal protection region to expose the upper surface of part of the second conductive type well region;
step six: generally injecting second conductive type impurities, and annealing to form a second conductive type body region;
step seven: implanting first conductive type impurities into the surface of a second conductive type body region in the cellular region and activating to form a first conductive type source region;
step eight: depositing a second type insulating medium layer;
step nine: selectively etching a through hole in the second type of insulating medium layer;
step ten: and depositing metal and selectively etching the metal to form source metal and a metal field plate and finally forming drain metal.
The manufacturing method of the trench power semiconductor device can further comprise the following steps:
the method comprises the following steps: providing a first conductive type substrate, and growing a first conductive type epitaxial layer on the first conductive type substrate;
step two: implanting second conductive type impurities into the first conductive type epitaxial layer, and annealing to form a second conductive type well region;
step three: selectively etching the grooves to form a first type groove and a second type groove; thermally growing to form a first gate oxide layer and a second gate oxide layer; depositing conductive polysilicon on the first-class gate oxide layer and the second-class gate oxide layer; etching and reserving the first type of conductive polysilicon in the first type of groove and the second type of conductive polysilicon in the second type of groove;
step four: depositing a first type of insulating medium layer;
step five: selectively etching and removing the first type insulating medium layer in the cellular region and the first type insulating medium layer in part of the terminal protection region to expose the upper surface of part of the second conductive type well region;
step six: generally injecting second conductive type impurities, and annealing to form a second conductive type body region;
step seven: generally injecting first conductive type impurities and activating to form a first conductive type source region;
step eight: depositing a second type insulating medium layer;
step nine: selectively etching a through hole in the second type of insulating medium layer;
step ten: and depositing metal and selectively etching the metal to form source metal and a metal field plate and finally forming drain metal.
The manufacturing method of the trench power semiconductor device can further comprise the following steps:
the method comprises the following steps: providing a first conductive type substrate, and growing a first conductive type epitaxial layer on the first conductive type substrate;
step two: implanting second conductive type impurities into the first conductive type epitaxial layer, and annealing to form a second conductive type well region;
step three: selectively etching the grooves to form a first type groove and a second type groove; thermally growing to form a first gate oxide layer and a second gate oxide layer; depositing conductive polysilicon on the first-class gate oxide layer and the second-class gate oxide layer; etching and reserving the first type of conductive polysilicon in the first type of groove and the second type of conductive polysilicon in the second type of groove;
step four: depositing a first type of insulating medium layer;
step five: selectively etching and removing the first insulating medium layer in the cellular region to expose the upper surface of part of the second conductive type well region;
step six: generally injecting second conductive type impurities, and annealing to form a second conductive type body region;
step seven: generally injecting first conductive type impurities and activating to form a first conductive type source region;
step eight: depositing a second type insulating medium layer;
step nine: selectively etching a through hole in the second type of insulating medium layer;
step ten: and depositing metal and selectively etching the metal to form source metal and a metal field plate and finally forming drain metal.
The invention can improve the terminal withstand voltage of the power semiconductor device and improve the reliability of the power semiconductor device.
Drawings
Fig. 1 is a schematic structural diagram of a power semiconductor device according to embodiment 1 of the present invention, in which an epitaxial layer is formed.
Fig. 2 is a schematic structural diagram of a power semiconductor device provided in embodiment 1 of the present invention for forming a second conductivity type well region.
Fig. 3 is a schematic structural diagram of a power semiconductor device according to embodiment 1 of the present invention, in which a first type trench and a second type trench, a first type gate oxide layer and a second type gate oxide layer, and a first type conductive polysilicon and a second type conductive polysilicon are formed.
Fig. 4 is a schematic structural diagram of a power semiconductor device provided in embodiment 1 of the present invention, in which a first type of insulating dielectric layer is formed by deposition.
Fig. 5 is a schematic structural diagram of a power semiconductor device according to embodiment 1 of the present invention, in which the first insulating dielectric layer is removed by selective etching.
Fig. 6 is a schematic structural diagram of the power semiconductor device according to embodiment 1 of the present invention, in which the second conductive type impurity is implanted and thermally annealed to form the second conductive type body region.
Fig. 7 is a schematic structural diagram of the power semiconductor device according to embodiment 1 of the present invention, in which first conductivity type impurities are selectively implanted and activated to form a first conductivity type source region.
Fig. 8 is a schematic structural diagram of a power semiconductor device provided in embodiment 1 of the present invention, in which a second type of insulating dielectric layer is formed by deposition.
Fig. 9 is a schematic structural diagram of a power semiconductor device according to embodiment 1 of the present invention, in which a through hole is selectively etched in a second insulating dielectric layer in a cell region.
Fig. 10 is a schematic structural diagram of a power semiconductor device according to embodiment 1 of the present invention, in which metal is deposited and selectively etched to form a source metal, a metal field plate, and a drain metal.
Fig. 11 is a schematic structural diagram of a power semiconductor device according to embodiment 2 of the present invention.
Fig. 12 is a schematic structural diagram of a power semiconductor device according to embodiment 3 of the present invention.
Fig. 13 is a schematic structural diagram of a conventional trench power semiconductor device.
Detailed Description
The present invention will be further described with reference to the following specific examples.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings. In which like parts are designated by like reference numerals. It should be noted that the words "left", "right", "upper" and "lower" used in the following description refer to directions in the drawings. The terms "inner" and "outer" are used to refer to directions toward and away from, respectively, the geometric center of a particular component.
The invention includes the following embodiments, and it should be explained that for an N-type power semiconductor device, the first conduction type in the invention is N-type conduction, and the second conduction type is P-type conduction; for a P-type power semiconductor device, the N-type in the invention is a P-type conductivity, and the second conductivity type is an N-type conductivity.
Example 1
A trench power semiconductor device, as shown in fig. 10, includes a drain metal 1, a semiconductor substrate, a first type trench 4, a first type conductive polysilicon 5, a first type gate oxide 6, a second type conductive body region 7, a first type conductive source region 8, a second type insulating dielectric layer 9, a first type insulating dielectric layer 10, a second type conductive well region 11, a source metal 12, a metal field plate 13, a second type trench 14, a second type conductive polysilicon 15, and a second type gate oxide 16;
the semiconductor substrate is arranged on the drain metal 1 and is divided into a cell area 001 and a terminal protection area 002, the cell area 001 is located in the central area of the semiconductor substrate, and the terminal protection area 002 is located on the outer ring of the cell area 001 and surrounds the cell area 001; the semiconductor substrate comprises a first conductive type substrate 2 and a first conductive type epitaxial layer 3 positioned on the first conductive type substrate 2;
a second conductive type body region 7 and a second conductive type well region 11 are arranged on the first conductive type epitaxial layer 3, the second conductive type body region 7 not only completely covers the first conductive type epitaxial layer 3 in the cell region 001, but also the second conductive type body region 7 partially extends into the terminal protection region 002 and covers the first conductive type epitaxial layer 3 close to the cell region 001, and the second conductive type well region 11 covers the first conductive type epitaxial layer 3 outside the second conductive type body region 7;
a first conductive type source region 8 is arranged in a second conductive type body region 7 positioned in the cellular region 001, a first groove 4 is formed downwards on the upper surface of the first conductive type source region 8, the first groove 4 penetrates through the first conductive type source region 8 and the second conductive type body region 7 downwards and finally extends into a first conductive type epitaxial layer 3, a first gate oxide layer 6 is formed on the side wall and the bottom wall of the first groove 4, and first conductive polycrystalline silicon 5 is arranged in the first gate oxide layer 6;
six second-class grooves 14 are formed in the upper surface of the second conduction type well region 11 in a downward mode, the second-class grooves 14 penetrate through the second conduction type well region 11 downwards and finally extend into the first conduction type epitaxial layer 3, second-class gate oxide layers 16 are arranged on the side walls and the bottom wall of each second-class groove 14, and second-class conductive polycrystalline silicon 15 is arranged in each second-class gate oxide layer 16;
a first-type insulating dielectric layer 10 is arranged on the second conduction-type well region 11, the first-type insulating dielectric layer 10 not only completely covers the second conduction-type well region 11 but also covers the edge part of the second conduction-type body region 7 positioned in the terminal protection region 002, a second-type insulating dielectric layer 9 is arranged on the first conduction-type source region 8, the non-edge part of the second conduction-type body region 7 positioned in the terminal protection region 002 and the first-type insulating dielectric layer 10, a source electrode metal 12 and a metal field plate 13 are arranged on the second-type insulating dielectric layer 9, the source electrode metal 12 not only completely covers the second-type insulating dielectric layer 9 positioned in the cell region 001 but also partially extends into the terminal protection region 002 and covers the second-type insulating dielectric layer 9 close to the cell region 001, the source electrode metal 12 is in ohmic contact with the first conduction-type source region 8 and the second conduction-type body region 7 through a through hole, the metal field plate 13 is completely positioned in the, and the metal field plate 13 covers at least one second type of groove 14, the metal field plate 13 is connected with a source electrode potential or a grid electrode potential, and the source electrode metal 12 is in ohmic contact with the second conductive type body region 7 extending into the terminal protection region 002 through a through hole in the second type of insulating medium layer 9.
The concentration peak value of the second conductivity type impurity of the second conductivity type body region 7 is larger than the concentration peak value of the second conductivity type impurity of the second conductivity type well region 11.
The first conductive polysilicon 5 in the first trench 4 is connected with the gate potential, and the second conductive polysilicon 15 in the second trench 14 is floating.
The manufacturing method of the trench power semiconductor device comprises the following steps:
the method comprises the following steps: providing a first conductivity type substrate 2, growing a first conductivity type epitaxial layer 3 on said first conductivity type substrate 2, as shown in fig. 1;
step two: implanting second conductivity type impurities into the first conductivity type epitaxial layer 3, and annealing to form a second conductivity type well region 11;
step three: selectively etching the grooves to form a first type groove 4 and a second type groove 14; thermally growing to form a first-type gate oxide layer 6 and a second-type gate oxide layer 16; depositing conductive polysilicon; etching and reserving the first type conductive polysilicon 5 in the first type groove 4 and the second type conductive polysilicon 15 in the second type groove 14, as shown in fig. 2;
step four: depositing a first type of insulating dielectric layer 10, as shown in fig. 4;
step five: selectively etching and removing the first type insulating dielectric layer 10 in the cell region 001 and the first type insulating dielectric layer 10 in a part of the terminal protection region 002 to expose the upper surface of a part of the second conductive type well region 11, as shown in fig. 5;
step six: second conductivity type impurities are generally implanted, and a second conductivity type body region 7 is formed after annealing, as shown in fig. 6;
step seven: implanting first conductivity type impurities on the surface of the second conductivity type body region 7 located in the cell region 001 and activating to form a first conductivity type source region 8, as shown in fig. 7;
step eight: depositing a second type insulating dielectric layer 9, as shown in fig. 8;
step nine: selectively etching a through hole on the second type insulating medium layer 9, as shown in fig. 9;
step ten: metal is deposited and selectively etched to form source metal 12 and metal field plate 13 and finally drain metal 1, as shown in fig. 10.
Example 2
A trench power semiconductor device comprises drain metal 1, a semiconductor substrate, a first type trench 4, first type conductive polysilicon 5, a first type gate oxide layer 6, a second conductive type body region 7, a first conductive type source region 8, a second type insulating dielectric layer 9, a first type insulating dielectric layer 10, a second conductive type well region 11, source metal 12, a metal field plate 13, a second type trench 14, second type conductive polysilicon 15 and a second type gate oxide layer 16;
the semiconductor substrate is arranged on the drain metal 1 and is divided into a cell area 001 and a terminal protection area 002, the cell area 001 is located in the central area of the semiconductor substrate, and the terminal protection area 002 is located on the outer ring of the cell area 001 and surrounds the cell area 001; the semiconductor substrate comprises a first conductive type substrate 2 and a first conductive type epitaxial layer 3 positioned on the first conductive type substrate 2;
a second conductive type body region 7 and a second conductive type well region 11 are arranged on the first conductive type epitaxial layer 3, wherein the second conductive type body region 7 not only completely covers the first conductive type epitaxial layer 3 in the cell region 001, but also the second conductive type body region 7 partially extends into the terminal protection region 002 and covers the first conductive type epitaxial layer 3 close to the cell region 001;
a first conductive type source region 8 is arranged in the second conductive type body region 7, the first conductive type source region 8 not only completely covers the second conductive type body region 7 in the cellular region 001, but also partially extends into the terminal protection region 002 and partially covers the second conductive type body region 7 close to the cellular region 001, a first-type groove 4 is formed in the upper surface of the first conductive type source region 8, the first-type groove 4 penetrates through the first conductive type source region 8 and the second conductive type body region 7 downwards and finally extends into the first-type conductive type epitaxial layer 3, a first-type gate oxide layer 6 is formed on the side wall and the bottom wall of the first-type groove 4, and first-type conductive polycrystalline silicon 5 is arranged in the first-type gate oxide layer 6;
the second conductive type well region 11 covers the first conductive type epitaxial layer 3 outside the second conductive type body region 7, six second grooves 14 are formed in the upper surface of the second conductive type well region 11 downwards, the second grooves 14 penetrate through the second conductive type well region 11 downwards and finally extend into the first conductive type epitaxial layer 3, second type gate oxide layers 16 are arranged on the side walls and the bottom walls of the second type grooves 14, and second type conductive polycrystalline silicon 15 is arranged in the second type gate oxide layers 16;
a first insulating dielectric layer 10 is arranged on the second conductive type well region 11, the first insulating dielectric layer 10 not only completely covers the second conductive type well region 11 but also covers the edge part of the second conductive type body region 7 positioned in the terminal protection region 002, a second insulating dielectric layer 9 is arranged on the first conductive type source region 8 and the first insulating dielectric layer 10, a source electrode metal 12 and a metal field plate 13 are arranged on the second insulating dielectric layer 9, the source electrode metal 12 not only completely covers the second insulating dielectric layer 9 positioned in the cell region 001 but also partially extends into the terminal protection region 002 and covers the second insulating dielectric layer 9 close to the cell region 001, the source electrode metal 12 is in ohmic contact with the second conductive type body region 7 and the first conductive type source region 8 extending into the terminal protection region 002 through a through hole in the second insulating dielectric layer 9, the metal field plate 13 is completely positioned in the terminal protection region 002, and the metal field plate 13 covers at least one second type trench 14, and the metal field plate 13 is connected with a source electrode potential or a grid electrode potential.
The concentration peak value of the second conductivity type impurity of the second conductivity type body region 7 is larger than the concentration peak value of the second conductivity type impurity of the second conductivity type well region 11.
The first conductive polysilicon 5 in the first trench 4 is connected with the gate potential, and the second conductive polysilicon 15 in the second trench 14 is floating.
The manufacturing method of the trench power semiconductor device comprises the following steps:
the method comprises the following steps: providing a first conductive type substrate 2, and growing a first conductive type epitaxial layer 3 on the first conductive type substrate 2;
step two: implanting second conductivity type impurities into the first conductivity type epitaxial layer 3, and annealing to form a second conductivity type well region 11;
step three: selectively etching the grooves to form a first type groove 4 and a second type groove 14; thermally growing to form a first-type gate oxide layer 6 and a second-type gate oxide layer 16; depositing conductive polysilicon; etching and reserving the first type of conductive polysilicon 5 in the first type of groove 4 and the second type of conductive polysilicon 15 in the second type of groove 14;
step four: depositing a first type of insulating medium layer 10;
step five: selectively etching and removing the first-type insulating medium layer 10 in the cellular region 001 and the first-type insulating medium layer 10 in part of the terminal protection region 002 to expose the upper surface of part of the second conductive type well region 11;
step six: second conductive type impurities are generally injected, and a second conductive type body region 7 is formed after annealing;
step seven: generally implanting first conductive type impurities and activating to form a first conductive type source region 8;
step eight: depositing a second type insulating dielectric layer 9;
step nine: selectively etching a through hole on the second insulating medium layer 9;
step ten: and depositing metal and selectively etching the metal to form a source metal 12 and a metal field plate 13, and finally forming a drain metal 1.
Example 3
A trench power semiconductor device comprises drain metal 1, a semiconductor substrate, a first type trench 4, first type conductive polysilicon 5, a first type gate oxide layer 6, a second conductive type body region 7, a first conductive type source region 8, a second type insulating dielectric layer 9, a first type insulating dielectric layer 10, a second conductive type well region 11, source metal 12, a metal field plate 13, a second type trench 14, second type conductive polysilicon 15 and a second type gate oxide layer 16;
the semiconductor substrate is arranged on the drain metal 1 and is divided into a cell area 001 and a terminal protection area 002, the cell area 001 is located in the central area of the semiconductor substrate, and the terminal protection area 002 is located on the outer ring of the cell area 001 and surrounds the cell area 001; the semiconductor substrate comprises a first conductive type substrate 2 and a first conductive type epitaxial layer 3 positioned on the first conductive type substrate 2;
a second conductive type body region 7 and a second conductive type well region 11 are arranged on the first conductive type epitaxial layer 3, the second conductive type body region 7 completely covers the first conductive type epitaxial layer 3 in the cell region 001, a first conductive type source region 8 is arranged in the second conductive type body region 7, a first-class groove 4 is formed in the upper surface of the first conductive type source region 8 downwards, the first-class groove 4 penetrates through the first conductive type source region 8 and the second conductive type body region 7 downwards and finally extends into the first-class conductive type epitaxial layer 3, a first-class gate oxide layer 6 is formed on the side wall and the bottom wall of the first-class groove 4, and first-class conductive polysilicon 5 is arranged in the first-class gate oxide layer 6;
the second conductive type well region 11 completely or partially covers the first conductive type epitaxial layer 3 in the terminal protection region 002, a second-class groove 14 is formed in the upper surface of the second conductive type well region 11 in a downward direction, the second-class groove 14 penetrates through the second conductive type well region 11 downwards and finally extends into the first-class conductive type epitaxial layer 3, second-class gate oxide layers 16 are arranged on the side walls and the bottom wall of the second-class groove 14, second-class conductive polycrystalline silicon 15 is arranged in the second-class gate oxide layers 16, a first-class insulating medium layer 10 is arranged on the second conductive type well region 11, and the first-class insulating medium layer 10 completely covers the second conductive type well region 11;
a second type insulating medium layer 9 is arranged on the first conduction type source region 8 and the first type insulating medium layer 10, a source electrode metal 12 and a metal field plate 13 are arranged on the second type insulating medium layer 9, the source electrode metal 12 not only completely covers the second type insulating medium layer 9 positioned in the cellular region 001, but also partially extends into the terminal protection region 002 and covers the second type insulating medium layer 9 close to the cellular region 001, a first type groove 4 is arranged in a second conduction type well region 11 in the terminal protection region 002 close to the cellular region 001, through holes are arranged on two sides of the first type groove 4, the source electrode metal 12 is in ohmic contact with the second conduction type well region 11 through the through holes, the metal field plate 13 is completely positioned in the terminal field plate protection region 002, and the metal field plate 13 at least covers one second type groove 14, and the metal field plate 13 is connected with a source electrode potential or a grid electrode potential.
The concentration peak value of the second conductivity type impurity of the second conductivity type body region 7 is larger than the concentration peak value of the second conductivity type impurity of the second conductivity type well region 11.
The first conductive polysilicon 5 in the first trench 4 is connected with the gate potential, and the second conductive polysilicon 15 in the second trench 14 is floating.
The manufacturing method of the trench power semiconductor device comprises the following steps:
the method comprises the following steps: providing a first conductive type substrate 2, and growing a first conductive type epitaxial layer 3 on the first conductive type substrate 2;
step two: implanting second conductivity type impurities into the first conductivity type epitaxial layer 3, and annealing to form a second conductivity type well region 11;
step three: selectively etching the grooves to form a first type groove 4 and a second type groove 14; thermally growing to form a first-type gate oxide layer 6 and a second-type gate oxide layer 16; depositing conductive polysilicon; etching and reserving the first type of conductive polysilicon 5 in the first type of groove 4 and the second type of conductive polysilicon 15 in the second type of groove 14;
step four: depositing a first type of insulating medium layer 10;
step five: selectively etching and removing the first insulating medium layer 10 in the cell region 001 to expose the upper surface of part of the second conductive type well region 11;
step six: second conductive type impurities are generally injected, and a second conductive type body region 7 is formed after annealing;
step seven: generally implanting first conductive type impurities and activating to form a first conductive type source region 8;
step eight: depositing a second type insulating dielectric layer 9;
step nine: selectively etching a through hole on the second insulating medium layer 9;
step ten: and depositing metal and selectively etching the metal to form a source metal 12 and a metal field plate 13, and finally forming a drain metal 1.
Those of ordinary skill in the art will understand that: the above description is only exemplary of the present invention and should not be construed as limiting the present invention, and any modifications, equivalents, improvements and the like made within the spirit of the present invention should be included in the scope of the present invention.
Claims (10)
1. A trench power semiconductor device comprises drain electrode metal (1), a semiconductor substrate, a first type of trench (4), first type of conductive polysilicon (5), a first type of gate oxide layer (6), a second type of conductive body region (7), a first type of conductive source region (8), a second type of insulating dielectric layer (9), a first type of insulating dielectric layer (10), a second type of conductive well region (11), source electrode metal (12), a metal field plate (13), a second type of trench (14), second type of conductive polysilicon (15) and a second type of gate oxide layer (16);
the semiconductor substrate is arranged on the drain metal (1), the semiconductor substrate is divided into a cell area (001) and a terminal protection area (002), the cell area (001) is located in the center of the semiconductor substrate, and the terminal protection area (002) is located on the outer ring of the cell area (001) and surrounds the cell area (001); the semiconductor substrate comprises a first conductive type substrate (2) and a first conductive type epitaxial layer (3) positioned on the first conductive type substrate (2);
the method is characterized in that: a second conductive type body region (7) and a second conductive type well region (11) are arranged on the first conductive type epitaxial layer (3), the second conductive type body region (7) completely covers the first conductive type epitaxial layer (3) in the cell region (001), the second conductive type well region (11) completely or partially covers the first conductive type epitaxial layer (3) in the terminal protection region (002), a first conductive type source region (8) is arranged in the second conductive type body region (7), and a first insulating medium layer (10) is arranged on the second conductive type well region (11);
a first-class groove (4) is formed in the upper surface of the first conduction type source region (8) in a downward mode, the first-class groove (4) penetrates through the first conduction type source region (8) and the second conduction type body region (7) downwards and finally extends into the first-class conduction type epitaxial layer (3), a first-class gate oxide layer (6) is formed on the side wall and the bottom wall of the first-class groove (4), and first-class conductive polycrystalline silicon (5) is arranged in the first-class gate oxide layer (6);
a second groove (14) is formed in the upper surface of the second conduction type well region (11) in a downward mode, the second groove (14) penetrates through the second conduction type well region (11) downwards and finally extends into the first conduction type epitaxial layer (3), a second gate oxide layer (16) is arranged on the side wall and the bottom wall of the second groove (14), and second conduction polycrystalline silicon (15) is arranged in the second gate oxide layer (16);
a second type insulating medium layer (9) is arranged on the first conduction type source region (8) and the first type insulating medium layer (10), source electrode metal (12) and a metal field plate (13) are arranged on the second type insulating medium layer (9), the source electrode metal (12) not only completely covers the second type insulating medium layer (9) in the cellular region (001) but also partially extends into the terminal protection region (002) and covers the second type insulating medium layer (9) close to the cellular region (001), the source electrode metal (12) is in ohmic contact with the first conduction type source region (8) and the second conduction type body region (7) through a through hole, the metal field plate (13) is completely positioned in the terminal protection region (002), the metal field plate (13) at least covers one second type groove (14), and the metal field plate (13) is connected with a source electrode potential or a grid electrode potential.
2. The trench power semiconductor device of claim 1 wherein: the second conduction type body region (7) not only completely covers the first conduction type epitaxial layer (3) in the cell region (001), but also the second conduction type body region (7) partially extends into the terminal protection region (002) and covers the first conduction type epitaxial layer (3) close to the cell region (001), a first conduction type source region (8) is arranged on the second conduction type body region (7) in the cell region (001), the second conduction type well region (11) covers the first conduction type epitaxial layer (3) outside the second conduction type body region (7), the first insulation medium layer (10) not only completely covers the second conduction type well region (11) but also covers the edge part of the second conduction type body region (7) in the terminal protection region (002), and non-edge parts of the second conduction type body region (7) in the first conduction type source region (8) and the terminal protection region (002) and the first insulation medium layer (10) are provided with And a second type insulating medium layer (9) is arranged, and the source metal (12) is in ohmic contact with the second conduction type body region (7) extending into the terminal protection region (002) through a through hole in the second type insulating medium layer (9).
3. The trench power semiconductor device of claim 1 wherein: the second conduction type body region (7) completely covers the first conduction type epitaxial layer (3) in the cell region (001) and the second conduction type body region (7) partially extends into the terminal protection region (002) and covers the first conduction type epitaxial layer (3) close to the cell region (001), the first conduction type source region (8) completely covers the second conduction type body region (7) in the cell region (001) and partially extends into the terminal protection region (002) and partially covers the second conduction type body region (7) close to the cell region (001), the second conduction type well region (11) covers the first conduction type epitaxial layer (3) outside the second conduction type body region (7), the first type insulating medium layer (10) completely covers the second conduction type well region (11) and covers the edge portion of the second conduction type body region (7) in the terminal protection region (002), a second type insulating medium layer (9) is arranged on the first type insulating medium layer (10) and the first type conductive type source region (8), and the source metal (12) is in ohmic contact with the second type conductive type body region (7) and the first type conductive type source region (8) which extend into the terminal protection region (002) through holes in the second type insulating medium layer (9).
4. The trench power semiconductor device of claim 1 wherein: the second conductive type zone (7) completely covers the first conductive type epitaxial layer (3) in the cell zone (001), the second conductive type well region (11) completely covers the first conductive type epitaxial layer (3) in the terminal protection zone (002), the first insulating medium layer (10) completely covers the second conductive type well region (11), the second insulating medium layer (9) is arranged on the first conductive type source zone (8) and the first insulating medium layer (10), the first groove is arranged in the second conductive type well region in the terminal protection zone close to the cell zone, through holes are formed in two sides of the first groove, and source electrode metal is in ohmic contact with the second conductive type well region through the through holes.
5. The trench power semiconductor device according to any of claims 1 to 4, characterized by: the concentration peak of the second conductivity type impurity of the second conductivity type body region (7) is larger than the concentration peak of the second conductivity type impurity of the second conductivity type well region (11).
6. The trench power semiconductor device according to any of claims 1 to 4, characterized by: the first conductive polycrystalline silicon (5) in the first groove (4) is connected with a grid potential, and the second conductive polycrystalline silicon (15) in the second groove (14) is arranged in a floating mode.
7. The trench power semiconductor device according to any of claims 1 to 4, characterized by: the power semiconductor device is an N-type power semiconductor device or a P-type power semiconductor device, when the power semiconductor device is the N-type power semiconductor device, the first conduction type is an N type, and the second conduction type is a P type; when the power semiconductor device is a P-type semiconductor device, the first conductivity type is P-type and the second conductivity type is N-type.
8. A method of manufacturing a trench power semiconductor device as claimed in claim 2, comprising the steps of:
the method comprises the following steps: providing a first conductivity type substrate (2), growing a first conductivity type epitaxial layer (3) on the first conductivity type substrate (2);
step two: implanting second conductivity type impurities into the first conductivity type epitaxial layer (3), and annealing to form a second conductivity type well region (11);
step three: selectively etching the grooves to form a first type of groove (4) and a second type of groove (14); thermally growing to form a first gate oxide layer (6) and a second gate oxide layer (16); depositing conductive polysilicon; etching and reserving the first type of conductive polysilicon (5) in the first type of groove (4) and the second type of conductive polysilicon (15) in the second type of groove (14);
step four: depositing a first type of insulating dielectric layer (10);
step five: selectively etching and removing the first insulating medium layer (10) in the cellular region (001) and the first insulating medium layer (10) in a part of the terminal protection region (002) to expose the upper surface of a part of the second conductive type well region (11);
step six: second conductive type impurities are generally injected, and a second conductive type body region (7) is formed after annealing;
step seven: implanting first conductivity type impurities on the surface of a second conductivity type body region (7) in the cell region (001) and activating to form a first conductivity type source region (8);
step eight: depositing a second type of insulating medium layer (9);
step nine: selectively etching a through hole on the second type of insulating medium layer (9);
step ten: and depositing metal and selectively etching the metal to form a source metal (12) and a metal field plate (13), and finally forming a drain metal (1).
9. A method of manufacturing a trench power semiconductor device as claimed in claim 3, comprising the steps of:
the method comprises the following steps: providing a first conductivity type substrate (2), growing a first conductivity type epitaxial layer (3) on the first conductivity type substrate (2);
step two: implanting second conductivity type impurities into the first conductivity type epitaxial layer (3), and annealing to form a second conductivity type well region (11);
step three: selectively etching the grooves to form a first type of groove (4) and a second type of groove (14); thermally growing to form a first gate oxide layer (6) and a second gate oxide layer (16); depositing conductive polysilicon; etching and reserving the first type of conductive polysilicon (5) in the first type of groove (4) and the second type of conductive polysilicon (15) in the second type of groove (14);
step four: depositing a first type of insulating dielectric layer (10);
step five: selectively etching and removing the first insulating medium layer (10) in the cellular region (001) and the first insulating medium layer (10) in a part of the terminal protection region (002) to expose the upper surface of a part of the second conductive type well region (11);
step six: second conductive type impurities are generally injected, and a second conductive type body region (7) is formed after annealing;
step seven: generally implanting first conductive type impurities and activating to form a first conductive type source region (8);
step eight: depositing a second type of insulating medium layer (9);
step nine: selectively etching a through hole on the second type of insulating medium layer (9);
step ten: and depositing metal and selectively etching the metal to form a source metal (12) and a metal field plate (13), and finally forming a drain metal (1).
10. A method of manufacturing a trench power semiconductor device as claimed in claim 4, comprising the steps of:
the method comprises the following steps: providing a first conductivity type substrate (2), growing a first conductivity type epitaxial layer (3) on the first conductivity type substrate (2);
step two: implanting second conductivity type impurities into the first conductivity type epitaxial layer (3), and annealing to form a second conductivity type well region (11);
step three: selectively etching the grooves to form a first type of groove (4) and a second type of groove (14); thermally growing to form a first gate oxide layer (6) and a second gate oxide layer (16); depositing conductive polysilicon; etching and reserving the first type of conductive polysilicon (5) in the first type of groove (4) and the second type of conductive polysilicon (15) in the second type of groove (14);
step four: depositing a first type of insulating dielectric layer (10);
step five: selectively etching and removing the first insulating medium layer (10) in the cellular region (001) to expose the upper surface of part of the second conductive type well region (11);
step six: second conductive type impurities are generally injected, and a second conductive type body region (7) is formed after annealing;
step seven: forming a first conductive type source region (8) by diffusing and activating first conductive type impurities;
step eight: depositing a second type of insulating medium layer (9);
step nine: selectively etching a through hole on the second type of insulating medium layer (9);
step ten: and depositing metal and selectively etching the metal to form a source metal (12) and a metal field plate (13), and finally forming a drain metal (1).
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