CN113703958B - Method, device, equipment and storage medium for accessing data among multi-architecture processors - Google Patents
Method, device, equipment and storage medium for accessing data among multi-architecture processors Download PDFInfo
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Abstract
The invention discloses a data access method among multiple architecture processors, which comprises the following steps: receiving a data access request sent by an access party CPU through an open protocol bus; analyzing the data access request to obtain a target CPU and a target data block to be accessed; judging whether an access record corresponding to the target data block exists in an access directory of the Cache agent; if yes, performing access operation on the target data block in the target CPU according to the access record; if not, the access operation is carried out on the target data block according to the bus snoop protocol through the address mapping. By applying the data access method among the multi-architecture processors, the data access among the multi-architecture processors can be realized without complex chip design, and the universality is high. The invention also discloses a data access device, equipment and storage medium between the multi-architecture processors, which have corresponding technical effects.
Description
Technical Field
The present invention relates to the field of computer applications, and in particular, to a method, an apparatus, a device, and a computer readable storage medium for accessing data between multiple processors.
Background
With the development of technologies such as big data and artificial intelligence, the requirements of the system on performance and power consumption are faced, and most of the systems adopt a multi-core architecture.
Central processing units (Central Processing Unit, CPU) are core components in computer and intelligent systems that take over a significant portion of the control and computing operations in the system. The most important and necessary functions of the CPU are to bear the upper operating system and application software, provide a perfect instruction set architecture and control the instruction and data transmission between the bottom modules of the system. Software systems designed based on different instruction set architectures are very different. Under different architectures, not only are the protocols of the interconnection between the processors different, but also the physical interface specifications of the interconnection are different. Processors of different architectures, even processors configured in different specifications under the same architecture, often adopt processor interconnection interfaces of different specifications, so that it is difficult to interconnect the processors of different architectures, and it is difficult to realize data access between the processors of different architectures.
At present, aiming at specific architecture CPUs of Intel and Power, a processor cooperation chip technology is utilized to design interfaces of specific CPU chips based on the Intel and Power, and the interfaces are used for breaking through the limit of interconnection interfaces in a single computing system and expanding the number of the CPUs. However, the current design of the cooperative chip of the processor is complex, and the interface of the cooperative chip needs to be customized for the specific target CPU architecture, so that on one hand, a CPU manufacturer is required to open the interface design of the cooperative chip, and on the other hand, the cooperative chip cannot be compatible with other manufacturers. In addition, only very few manufacturers and systems currently have the technology, and the universality cannot be realized.
In summary, how to effectively solve the problems of complex chip design, inability to realize universality and the like in the existing data access method between processors with different architectures is a problem which needs to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide a data access method among multiple architecture processors, which can realize the data access among the multiple architecture processors without complex chip design and has high universality; it is another object of the present invention to provide a data access apparatus, device and computer readable storage medium between multi-architecture processors.
In order to solve the technical problems, the invention provides the following technical scheme:
a method of data access between multiple architecture processors, comprising:
receiving a data access request sent by an access party CPU through an open protocol bus;
analyzing the data access request to obtain a target CPU and a target data block to be accessed;
judging whether an access record corresponding to the target data block exists in an access directory of the Cache agent;
if yes, performing access operation on the target data block in the target CPU according to the access record;
if not, the access operation is carried out on the target data block according to the bus snoop protocol through address mapping.
In one embodiment of the present invention, after performing an access operation on a target data block in the target CPU according to the access record or performing an access operation on the target data block according to a bus snoop protocol through address mapping, the method further includes:
acquiring the target data block;
and returning the target data block to the CPU of the access party.
In one embodiment of the present invention, returning the target data block to the access CPU includes:
judging whether the target CPU and the access party CPU are mounted on the same cooperative interconnection chip or not;
if not, the target data block is sent to a second data arbitration module in a second cooperative interconnection chip of the access party CPU through a first data arbitration module in a first cooperative interconnection chip of the target CPU, so that the second data arbitration module returns the target data block to the access party CPU through the open protocol bus;
if yes, the target data block is returned to the CPU of the access party through the open protocol bus.
In a specific embodiment of the present invention, the sending, by a first data arbitration module in a first cooperative interconnection chip on which the target CPU is mounted, the target data block to a second data arbitration module in a second cooperative interconnection chip on which the access CPU is mounted includes:
and sending the target data block to a second data arbitration module in a second cooperative interconnection chip for mounting the CPU of the access party according to a custom chip protocol through a first data arbitration module in a first cooperative interconnection chip for mounting the target CPU.
In one embodiment of the present invention, after returning the target data block to the access CPU, the method further includes:
generating a latest access record;
and updating the access directory based on the latest access record by using the Cache agent.
In a specific embodiment of the present invention, the updating the access directory by using the Cache agent based on the latest access record includes:
judging whether the storage space corresponding to the access directory in the Cache agent is in a full state or not;
if not, the Cache agent is utilized to directly record the latest access record to the access directory;
if yes, searching the earliest access record in the access directory according to the access time sequence, and replacing the earliest access record with the latest access record by using the Cache agent.
A data access apparatus between multi-architecture processors, comprising:
a request receiving unit, configured to receive a data access request sent by an access party CPU through an open protocol bus;
the request analysis unit is used for analyzing the data access request to obtain a target CPU and a target data block to be accessed;
the judging unit is used for judging whether the access record corresponding to the target data block exists in the access directory of the Cache agent;
the first data access unit is used for performing access operation on the target data block in the target CPU according to the access record when the access record corresponding to the target data block exists in the access directory of the Cache agent;
and the second data access unit is used for performing access operation on the target data block according to a bus snoop protocol through address mapping when the fact that the access record corresponding to the target data block does not exist in the access directory of the Cache agent is determined.
In one embodiment of the present invention, the method further comprises:
a data block obtaining unit, configured to obtain a target data block in the target CPU after performing an access operation on the target data block according to the access record or performing an access operation on the target data block according to a bus snoop protocol through address mapping;
and the data block returning unit is used for returning the target data block to the CPU of the access party.
A data access device between multiple architecture processors, comprising:
a memory for storing a computer program;
and a processor for implementing the steps of the data access method between the multi-architecture processors as described above when executing the computer program.
A computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of a method of data access between multi-architecture processors as described above.
According to the data access method among the multi-architecture processors, the data access request sent by the CPU of the accessing party is received through the open protocol bus; analyzing the data access request to obtain a target CPU and a target data block to be accessed; judging whether an access record corresponding to the target data block exists in an access directory of the Cache agent; if yes, performing access operation on the target data block in the target CPU according to the access record; if not, the access operation is carried out on the target data block according to the bus snoop protocol through the address mapping.
According to the technical scheme, an open protocol bus for data transmission among the processors is preset, and a Cache agent is preset, wherein an access directory for recording the access state of the data blocks in the processors is maintained in the Cache agent. After analyzing the data access request sent by the CPU of the accessing party to obtain the accessed target CPU and the accessed target data block, when the corresponding access record exists, the data access is carried out according to the access record, and when the corresponding access record does not exist, the data access is carried out according to the bus snoop protocol through address mapping. The invention can flexibly support the expansion of the multiprocessor system, breaks the limit among different CPU manufacturers, supports the realization of multiprocessor systems with different scales, can realize the data access among the multi-architecture processors without complex chip design, and has high universality.
Correspondingly, the invention also provides a data access device, equipment and a computer readable storage medium between the multi-architecture processors corresponding to the data access method between the multi-architecture processors, which have the technical effects and are not repeated herein.
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In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for accessing data between multiple processors according to an embodiment of the present invention;
FIG. 2 is a block diagram of a co-interconnect chip for mounting a multi-architecture processor in accordance with an embodiment of the present invention;
FIG. 3 is a flowchart illustrating another embodiment of a method for accessing data between multiple processors according to the present invention;
FIG. 4 is a block diagram illustrating an architecture of a data access device between multiple processors according to an embodiment of the present invention;
FIG. 5 is a block diagram illustrating a data access device between multiple processors according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a specific structure of a data access device between multiple processors according to the present embodiment.
Detailed Description
In order to better understand the aspects of the present invention, the present invention will be described in further detail with reference to the accompanying drawings and detailed description. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, fig. 1 is a flowchart illustrating an implementation of a method for accessing data between multiple architecture processors according to an embodiment of the present invention, the method may include the following steps:
s101: and receiving a data access request sent by the CPU of the accessing party through the open protocol bus.
Referring to fig. 2, fig. 2 is a block diagram illustrating a co-interconnect chip for mounting a multi-architecture processor according to an embodiment of the present invention. The cooperative interconnection chip comprises an open protocol bus, a data arbitration module, a chip interconnection interface and a Cache agent. The open protocol bus is based on a unified open protocol and is used for connecting a plurality of CPUs, so that all CPUs connected on the same collaborative interconnection chip can realize mutual data access. When a certain CPU needs to access the data in other CPUs, a data access request is generated, and the data access request is sent to a cooperative interconnection chip mounted on the CPU of the accessing party.
The open protocol bus for connecting the CPU is not particularly limited to a certain protocol bus, and any protocol bus satisfying a certain condition may be used. First, cache coherency maintenance for processors is supported, and second, can be opened to individual processor vendors. At present, protocols such as CCIX and the like can meet the requirements in the market, and if the future openness guarantee is considered and the purpose of simplifying the protocols is considered, a set of standard protocols can be customized. However, as long as the two requirements are satisfied, the existing general protocol or the custom protocol can be adopted.
On an open protocol bus, once the protocol type is determined, the CPU interfaces, the required physical links, that can be most mounted on the bus can also be determined. For cost and implementation difficulty, the CPU interface (i.e. the number of CPUs that can be directly connected by a single cooperative interconnection chip) is not as good as possible, but the actual application situation should be considered. In practice, in most multiprocessor systems, the number of CPUs used is four or less, so if the general scenario is targeted, the number of CPU interfaces on the bus can be four. In addition, the data arbitration module and the Cache agent of the chip are also mounted on the bus.
S102: and analyzing the data access request to obtain a target CPU and a target data block to be accessed.
The data access request sent by the CPU of the accessing party contains information such as a target CPU to be accessed and a target data block. And the collaborative interconnection chip of the CPU of the mounting access party receives the data access request and analyzes the data access request to obtain a target CPU and a target data block to be accessed.
S103: and judging whether an access record corresponding to the target data block exists in the access directory of the Cache agent, if so, executing the step S104, and if not, executing the step S105.
The Cache agent in the cooperative interconnection chip maintains in advance an access directory for recording the access status to the data blocks in each processor. The Cache agent is used to implement a directory-based protocol to maintain coherency of the same data block state in the Cache memory between CPUs. After the collaborative interconnection chip analyzes the data access request to obtain the target CPU and the target data block to be accessed, judging whether an access record corresponding to the target data block exists in an access directory of the Cache agent, if so, indicating that the Cache agent records the accessed process of the target data block in the early stage, and executing the step S104 according to the access record, if not, indicating that the Cache agent does not record the accessed process of the target data block in the early stage, and executing the step S105.
In a directory protocol based system, the access states of data blocks that need to be cached in a cache memory are uniformly stored in an access directory, which uniformly manages the access states of all data blocks in each processor (i.e., CPU), and coordinates the problem of consistency. The access directory is similar to an arbiter and needs to be filed when the processor needs to load a block of data from memory into its own exclusive cache. When a block is changed by a processor, the access directory is responsible for changing the block access state, updating the other processor's backups in the cache, or invalidating the other processor's backups in the cache.
S104: and performing access operation on the target data block in the target CPU according to the access record.
When the access record corresponding to the target data block exists in the access directory of the Cache agent, the fact that the Cache agent records the accessed process of the target data block in the earlier stage is indicated, the target data block can be tracked according to the access record, and the access operation is carried out on the target data block in the target CPU according to the access record, so that the direct data access among the multi-architecture CPUs is realized according to the access record in the access directory.
S105: access operations are performed to the target data block in accordance with the bus snoop protocol via the address map.
When the fact that the access record corresponding to the target data block does not exist in the access directory of the Cache agent is determined, the fact that the Cache agent does not record the accessed process of the target data block in the earlier stage is indicated, the access record aiming at the target data block does not exist in the access directory, and the access operation is carried out on the target data block according to a bus snoop protocol through address mapping. By performing a series of broadcast and snoop operations according to the bus snoop protocol, the latest modification information for the target data block is obtained, namely, which CPU has the latest modification on the target data block is determined, so that the CPU which has the latest modification on the target data block returns the target data block bent by the latest modification to the target CPU, and the access to the target data block in the target CPU is realized.
In bus snoop protocols, for cached content in a cache memory that is exclusively owned by a processor (i.e., CPU), the processor is responsible for snooping the open protocol bus, which needs to be broadcast over the bus if the content is changed by the processor itself; otherwise, if the content state is changed by another processor, the cache memory of the processor receives notification from the bus, and the state of the local backup needs to be changed accordingly.
The access directory and the corresponding protocol processing are increased on the basis of the Cache consistency among processors realized by the original bus snoop protocol, so that the cost is reduced, and the system performance is improved.
According to the technical scheme, an open protocol bus for data transmission among the processors is preset, and a Cache agent is preset, wherein an access directory for recording the access state of the data blocks in the processors is maintained in the Cache agent. After analyzing the data access request sent by the CPU of the accessing party to obtain the accessed target CPU and the accessed target data block, when the corresponding access record exists, the data access is carried out according to the access record, and when the corresponding access record does not exist, the data access is carried out according to the bus snoop protocol through address mapping. The invention can flexibly support the expansion of the multiprocessor system, breaks the limit among different CPU manufacturers, supports the realization of multiprocessor systems with different scales, can realize the data access among the multi-architecture processors without complex chip design, and has high universality.
It should be noted that, based on the above embodiments, the embodiments of the present invention further provide corresponding improvements. The following embodiments relate to the same steps as those in the above embodiments or the steps corresponding to the steps may be referred to each other, and the corresponding beneficial effects may also be referred to each other, which will not be described in detail in the following modified embodiments.
Referring to fig. 3, fig. 3 is a flowchart illustrating another implementation of a method for accessing data between multiple architecture processors according to an embodiment of the present invention, the method may include the following steps:
s301: and receiving a data access request sent by the CPU of the accessing party through the open protocol bus.
S302: and analyzing the data access request to obtain a target CPU and a target data block to be accessed.
S303: and judging whether an access record corresponding to the target data block exists in the access directory of the Cache agent, if so, executing the step S304, and if not, executing the step S305.
S304: and performing access operation on the target data block in the target CPU according to the access record.
S305: access operations are performed to the target data block in accordance with the bus snoop protocol via the address map.
S306: and acquiring a target data block.
After access to the target data block in the target CPU is achieved, the target data block is acquired.
S307: and returning the target data block to the CPU of the accessing party.
After the target data block is acquired, the target data block is returned to the access party CPU, so that the access party CPU can perform corresponding operations such as checking, modifying and the like on the received target data block.
In one embodiment of the present invention, step S307 may include the steps of:
step one: judging whether the target CPU and the access party CPU are mounted on the same cooperative interconnection chip, if not, executing the second step, and if so, executing the third step;
step two: the method comprises the steps that a target data block is sent to a second data arbitration module in a second cooperative interconnection chip of a mounted access party CPU through a first data arbitration module in a first cooperative interconnection chip of the mounted target CPU, so that the second data arbitration module returns the target data block to the access party CPU through an open protocol bus;
step three: and returning the target data block to the CPU of the access party through the open protocol bus.
For convenience of description, the above three steps may be combined for explanation.
The accessing CPU may access the target CPU mounted on the same cooperative interconnection chip, or may access the target CPU mounted on a different cooperative interconnection chip. After the target data block is obtained, judging whether the target CPU and the access party CPU are mounted on the same cooperative interconnection chip, if not, indicating that the target CPU is currently in cross-chip data transmission, and sending the target data block to a second data arbitration module in a second cooperative interconnection chip for mounting the access party CPU through a first data arbitration module in the first cooperative interconnection chip for mounting the target CPU, so that the second data arbitration module returns the target data block to the access party CPU through an open protocol bus, if so, indicating that the target data block is currently in data transmission in the same chip, and directly returning the target data block to the access party CPU through the open protocol bus.
Referring to fig. 3, when it is determined that the target CPU and the accessing CPU are mounted on different cooperative interconnected chips, a specific process of returning the target data block from the target CPU to the accessing CPU may include: the target CPU sends the target data block to a data arbitration module in the cooperative interconnection chip where the target CPU is located through an open protocol bus, and sends the target data block to the data arbitration module in the cooperative interconnection chip where the access CPU is located through a chip interconnection interface of the cooperative interconnection chip where the target CPU is located and a chip interconnection interface of the cooperative interconnection chip where the access CPU is located, and then sends the target data block to the access CPU through the open protocol bus of the chip.
In a specific embodiment of the present invention, the sending, by the first data arbitration module in the first cooperative interconnection chip on which the target CPU is mounted, the target data block to the second data arbitration module in the second cooperative interconnection chip on which the accessing CPU is mounted may include the steps of:
and sending the target data block to a second data arbitration module in a second cooperative interconnection chip of the CPU of the mounting access party according to a custom chip protocol through a first data arbitration module in a first cooperative interconnection chip of the mounting target CPU.
The cooperative interconnection cooperates with the interconnection between chips, and can adopt various modes such as direct full interconnection, bus, network interconnection and the like according to the scale and the form of the system, in order to support the flexible configuration, the chip interconnection can preferably adopt a customized simplified protocol instead of a standardized protocol, and the chip interconnection interface can adopt a configurable multiport structure to support various interconnection topologies.
S308: a latest access record is generated.
After the access party CPU completes the access to the target data block in the target CPU, the latest access record is generated.
S309: and updating the access directory based on the latest access record by using the Cache agent.
After the latest access record is generated, the Cache agent is utilized to update the access directory based on the latest access record, so that the access state of the target data block is recorded in time, and the system overhead can be reduced when the same data block is accessed next time.
In one embodiment of the present invention, step S209 may include the steps of:
step one: judging whether the storage space corresponding to the access directory in the Cache agent is in a full state, if not, executing the second step, and if so, executing the third step.
Step two: directly recording the latest access record to an access directory by using a Cache agent;
step three: searching the earliest access record in the access directory according to the access time sequence, and replacing the earliest access record with the latest access record by using the Cache proxy.
For convenience of description, the above three steps may be combined for explanation.
As the total capacity of the storage space corresponding to the access directory in the Cache proxy is wasted if the total capacity is set according to the maximum supportable system scale, simulation analysis can be carried out on the target system, the storage space corresponding to the access directory in the Cache proxy is set to be more reasonable, and when the storage space corresponding to the access directory in the Cache proxy is full, the earliest access record is replaced by the latest access record according to the access sequence.
After generating the latest access record, judging whether a storage space corresponding to the access directory in the Cache agent is in a full state, if not, directly recording the latest access record to the access directory by using the Cache agent, and if so, searching the earliest access record in the access directory according to the access time sequence, and replacing the earliest access record with the latest access record by using the Cache agent. Therefore, excessive access records in the storage space corresponding to the access directory in the Cache agent are avoided, the access record query efficiency is improved, and meanwhile, the system storage space is saved.
Corresponding to the above method embodiment, the present invention further provides a data access device between multi-architecture processors, where the data access device between multi-architecture processors described below and the data access method between multi-architecture processors described above can be referred to correspondingly.
Referring to fig. 4, fig. 4 is a block diagram illustrating a data access apparatus between multiple architecture processors according to an embodiment of the present invention, the apparatus may include:
a request receiving unit 41, configured to receive a data access request sent by an access party CPU through an open protocol bus;
a request parsing unit 42, configured to parse the data access request to obtain a target CPU and a target data block to be accessed;
a judging unit 43, configured to judge whether an access record corresponding to the target data block exists in the access directory of the Cache agent;
a first data access unit 44, configured to perform an access operation on a target data block in the target CPU according to an access record when it is determined that the access record corresponding to the target data block exists in the access directory of the Cache agent;
and the second data access unit 45 is configured to perform an access operation on the target data block according to the bus snoop protocol through address mapping when it is determined that an access record corresponding to the target data block does not exist in the access directory of the Cache agent.
According to the technical scheme, an open protocol bus for data transmission among the processors is preset, and a Cache agent is preset, wherein an access directory for recording the access state of the data blocks in the processors is maintained in the Cache agent. After analyzing the data access request sent by the CPU of the accessing party to obtain the accessed target CPU and the accessed target data block, when the corresponding access record exists, the data access is carried out according to the access record, and when the corresponding access record does not exist, the data access is carried out according to the bus snoop protocol through address mapping. The invention can flexibly support the expansion of the multiprocessor system, breaks the limit among different CPU manufacturers, supports the realization of multiprocessor systems with different scales, can realize the data access among the multi-architecture processors without complex chip design, and has high universality.
In one embodiment of the present invention, the apparatus may further include:
the data block acquisition unit is used for acquiring the target data block after performing access operation on the target data block in the target CPU according to the access record or performing access operation on the target data block according to a bus snoop protocol through address mapping;
and the data block returning unit is used for returning the target data block to the CPU of the accessing party.
In one embodiment of the present invention, the data block return unit includes:
the first judging subunit is used for judging whether the target CPU and the access party CPU are mounted on the same collaborative interconnection chip or not;
the first data block returning subunit is configured to send, when it is determined that the target CPU and the access party CPU are mounted on different cooperative interconnection chips, the target data block to a second data arbitration module in a second cooperative interconnection chip on which the access party CPU is mounted through a first data arbitration module in the first cooperative interconnection chip on which the target CPU is mounted, so that the second data arbitration module returns the target data block to the access party CPU through an open protocol bus;
and the second data block returning subunit is used for returning the target data block to the access party CPU through the open protocol bus when the target CPU and the access party CPU are determined to be mounted on the same collaborative interconnection chip.
In a specific embodiment of the present invention, the first data block return subunit is specifically a unit that sends, through the first data arbitration module in the first cooperative interconnection chip on which the target CPU is mounted, the target data block to the second data arbitration module in the second cooperative interconnection chip on which the accessing CPU is mounted according to a custom chip protocol.
In one embodiment of the present invention, the apparatus may further include:
an access record generating unit for generating the latest access record after returning the target data block to the access party CPU;
and the directory updating unit is used for updating the access directory based on the latest access record by using the Cache agent.
In one embodiment of the present invention, the catalog updating unit includes:
the second judging subunit is used for judging whether the storage space corresponding to the access directory in the Cache agent is in a full state or not;
a recording subunit, configured to directly record the latest access record to the access directory by using the Cache proxy when it is determined that the storage space corresponding to the access directory in the Cache proxy is in an unsatisfied state;
and the replacing subunit is used for searching the earliest access record in the access directory according to the access time sequence when the storage space corresponding to the access directory in the Cache agent is in a full state, and replacing the earliest access record with the latest access record by using the Cache agent.
Corresponding to the above method embodiment, referring to fig. 5, fig. 5 is a schematic diagram of a data access device between multi-architecture processors provided by the present invention, where the device may include:
a memory 332 for storing a computer program;
processor 322, when executing the computer program, implements the steps of the data access method between multi-architecture processors of the method embodiments described above.
Specifically, referring to fig. 6, fig. 6 is a schematic diagram of a specific structure of a data access device between multi-architecture processors according to the present embodiment, where the data access device between multi-architecture processors may have relatively large differences due to different configurations or performances, and may include a processor (central processing units, CPU) 322 (e.g., one or more processors) and a memory 332, where the memory 332 stores one or more computer applications 342 or data 344. Wherein the memory 332 may be transient storage or persistent storage. The program stored in memory 332 may include one or more modules (not shown), each of which may include a series of instruction operations in the data processing apparatus. Still further, the processor 322 may be configured to communicate with the memory 332 to execute a series of instruction operations in the memory 332 on the inter-multi-architecture data access device 301.
The inter-multi-architecture processor data access device 301 may also include one or more power supplies 326, one or more wired or wireless network interfaces 350, one or more input/output interfaces 358, and/or one or more operating systems 341.
The steps in the method of data access between multi-architecture processors described above may be implemented by the structure of the data access device between multi-architecture processors.
Corresponding to the above method embodiments, the present invention also provides a computer readable storage medium having a computer program stored thereon, which when executed by a processor, performs the steps of:
receiving a data access request sent by an access party CPU through an open protocol bus; analyzing the data access request to obtain a target CPU and a target data block to be accessed; judging whether an access record corresponding to the target data block exists in an access directory of the Cache agent; if yes, performing access operation on the target data block in the target CPU according to the access record; if not, the access operation is carried out on the target data block according to the bus snoop protocol through the address mapping.
The computer readable storage medium may include: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
For the description of the computer-readable storage medium provided by the present invention, refer to the above method embodiments, and the disclosure is not repeated here.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, so that the same or similar parts between the embodiments are referred to each other. The apparatus, device and computer readable storage medium of the embodiments are described more simply because they correspond to the methods of the embodiments, and the description thereof will be given with reference to the method section.
The principles and embodiments of the present invention have been described herein with reference to specific examples, but the description of the examples above is only for aiding in understanding the technical solution of the present invention and its core ideas. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the invention can be made without departing from the principles of the invention and these modifications and adaptations are intended to be within the scope of the invention as defined in the following claims.
Claims (10)
1. A method of data access between multiple architecture processors, applied to a co-interconnect chip, the co-interconnect chip connected with a plurality of CPUs through an open protocol bus, the method comprising:
receiving a data access request sent by an access party CPU through an open protocol bus;
analyzing the data access request to obtain a target CPU and a target data block to be accessed;
judging whether an access record corresponding to the target data block exists in an access directory of the Cache agent; the access catalog is used for recording the access state of each data block in each CPU; the Cache agent is deployed on the collaborative interconnection chip;
if yes, performing access operation on the target data block in the target CPU according to the access record;
if not, the access operation is carried out on the target data block according to the bus snoop protocol through address mapping.
2. The method of claim 1, further comprising, after performing an access operation on a target data block in the target CPU according to the access record or performing an access operation on the target data block according to a bus snoop protocol through address mapping:
acquiring the target data block;
and returning the target data block to the CPU of the access party.
3. The method of claim 2, wherein returning the target data block to the accessing CPU comprises:
judging whether the target CPU and the access party CPU are mounted on the same cooperative interconnection chip or not;
if not, the target data block is sent to a second data arbitration module in a second cooperative interconnection chip of the access party CPU through a first data arbitration module in a first cooperative interconnection chip of the target CPU, so that the second data arbitration module returns the target data block to the access party CPU through the open protocol bus;
if yes, the target data block is returned to the CPU of the access party through the open protocol bus.
4. The method for data access between multiple architecture processors according to claim 3, wherein sending the target data block to a second data arbitration module in a second co-interconnect chip on which the accessing CPU is mounted by a first data arbitration module in a first co-interconnect chip on which the target CPU is mounted, comprises:
and sending the target data block to a second data arbitration module in a second cooperative interconnection chip for mounting the CPU of the access party according to a custom chip protocol through a first data arbitration module in a first cooperative interconnection chip for mounting the target CPU.
5. The method of inter-multi-architecture processor data access according to any one of claims 2 to 4, further comprising, after returning the target data block to the accessing CPU:
generating a latest access record;
and updating the access directory based on the latest access record by using the Cache agent.
6. The method of claim 5, wherein updating the access directory with the Cache agent based on the most recent access record, comprises:
judging whether the storage space corresponding to the access directory in the Cache agent is in a full state or not;
if not, the Cache agent is utilized to directly record the latest access record to the access directory;
if yes, searching the earliest access record in the access directory according to the access time sequence, and replacing the earliest access record with the latest access record by using the Cache agent.
7. A data access apparatus between multi-architecture processors, for use with a co-interconnect chip having a plurality of CPUs connected by an open protocol bus, the apparatus comprising:
a request receiving unit, configured to receive a data access request sent by an access party CPU through an open protocol bus;
the request analysis unit is used for analyzing the data access request to obtain a target CPU and a target data block to be accessed;
the judging unit is used for judging whether the access record corresponding to the target data block exists in the access directory of the Cache agent; the access record is used for recording the access state of each data block in each CPU; the Cache agent is deployed on the collaborative interconnection chip;
the first data access unit is used for performing access operation on the target data block in the target CPU according to the access record when the access record corresponding to the target data block exists in the access directory of the Cache agent;
and the second data access unit is used for performing access operation on the target data block according to a bus snoop protocol through address mapping when the fact that the access record corresponding to the target data block does not exist in the access directory of the Cache agent is determined.
8. The inter-multi-architecture processor data access apparatus of claim 7, further comprising:
a data block obtaining unit, configured to obtain a target data block in the target CPU after performing an access operation on the target data block according to the access record or performing an access operation on the target data block according to a bus snoop protocol through address mapping;
and the data block returning unit is used for returning the target data block to the CPU of the access party.
9. A multi-architecture inter-processor data access device, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the method for data access between multi-architecture processors according to any of claims 1 to 6 when executing said computer program.
10. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a computer program which, when executed by a processor, implements the steps of the method for data access between multi-architecture processors according to any of claims 1 to 6.
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