CN113849419B - Method, system, equipment and storage medium for generating test vector of chip - Google Patents
Method, system, equipment and storage medium for generating test vector of chip Download PDFInfo
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Abstract
The embodiment of the invention discloses a method, a device, equipment and a storage medium for generating a test vector of a chip. The method comprises the following steps: acquiring associated operation information generated in the process that a test case runs on a chip to be tested in real time; and generating a target test vector of the chip to be tested according to the associated operation information. The embodiment of the invention can optimize the flexibility of test vector generation of the chip and improve the generation efficiency and the test coverage range of the test vector.
Description
Technical Field
The embodiment of the invention relates to the technical field of chips, in particular to a method, a system, equipment and a storage medium for generating a test vector of a chip.
Background
With the demand for artificial intelligence becoming higher and higher, the number of IP Core (Intellectual Property Core) modules integrated inside the corresponding artificial intelligence chip tends to increase and the functions of the modules become more and more complex, and the bus structure, data path and functions of the chip also become more and more complex. Therefore, whether the system function level of the artificial intelligent chip can be comprehensively and efficiently tested in an ATE (Automatic Test Equipment) stage or not will have a great influence on the subsequent research and development progress of the chip product, the smooth mass production of the product and the landing of the business.
Currently, when a chip is tested in an ATE test stage, a corresponding test vector needs to be provided in advance. The existing test vector generation technologies mainly include the following: the prior art is applied to a chip Hardware simulation environment, and when a chip is simulated, an HDL (Hardware Description Language) file and a file variable are established to record a Test vector, that is, an input/output signal of a chip module to be tested is monitored, and meanwhile, under the condition that a JTAG (Joint Test Action Group) clock signal identical to that of ATE Test equipment is set, when a Test case runs, a signal, which is turned over each time, corresponding to the input/output signal of the chip module to be tested is sampled and recorded in the Test vector file at a rising edge of each JTAG clock. The second prior art is also applied to a chip hardware simulation environment, before test case simulation, corresponding log record statements are manually added to all positions needing to be recorded in each test case, after the test case simulation is completed, a log record file is generated and contains all print record information in the running process of the test case, then the log record file is analyzed and extracted manually or through scripts, and information needed by test vectors is recorded into a test vector file.
However, the above prior art has several problems in the following respects: firstly, aiming at the implementation mode and flexibility of test vectors, in the prior art, the JTAG clock frequency which is the same as that of a target ATE machine needs to be preset, after a test engineer needs to change the JTAG frequency of the ATE machine, the original test vectors can not be successfully tested, corresponding delay time needs to be manually increased or decreased at each position of the relevant test vectors, and the test is possible to pass through after repeated debugging, so that the flexibility is poor. In the second prior art, additional recording statements need to be added to all positions needing to be monitored in each test case, so that the operation complexity is high; after the test case simulation is completed, the log record file generated in the earlier stage needs to be analyzed and extracted again manually or by a script, so that the corresponding test vector can be generated, and the flexibility and the efficiency are poor. Secondly, the two prior arts can only be applied to a chip simulation environment, the simulation test takes a long time, and when a problem of a test case is found, the test case needs to be re-simulated and generated after being modified, so that the efficiency is low, and the rapid development and convergence of a test vector are not facilitated. In addition, when the number of the computing processing units in the chip is large, the test content and the coverage area of the corresponding test case are required to be increased, and the prior art is only suitable for the chip simulation environment, so that when more and more complex test contents need to be added in the test case, the simulation test time of a single test case is further increased, the generation of test vectors aiming at complex chip functional test cases cannot be efficiently completed in the prior art, the important functions of a plurality of chip modules cannot be effectively tested, and the corresponding ATE test coverage area is difficult to further improve.
Disclosure of Invention
The embodiment of the invention provides a method, a system, equipment and a storage medium for generating a test vector of a chip, which are used for optimizing the flexibility of generating the test vector of the chip and improving the generation efficiency and the test coverage range of the test vector.
In a first aspect, an embodiment of the present invention provides a method for generating a test vector of a chip, including:
acquiring associated operation information generated in the process that a test case runs on a chip to be tested in real time;
and generating a target test vector of the chip to be tested according to the associated operation information.
In a second aspect, an embodiment of the present invention further provides a test vector generation system for a chip, including: the device comprises a signal monitoring module and a vector generating module; the signal monitoring module is in communication connection with the vector generation module; wherein:
the signal monitoring module is used for acquiring the associated operation information generated in the process that the test case runs on the chip to be tested in real time and sending the associated operation information to the vector generation module;
and the vector generation module is used for receiving the correlation operation information and generating a target test vector of the chip to be tested according to the correlation operation information.
In a third aspect, an embodiment of the present invention further provides a computer device, where the computer device includes:
one or more processors;
storage means for storing one or more programs;
when the one or more programs are executed by the one or more processors, the one or more processors implement the method for generating the test vector of the chip provided by any embodiment of the invention.
In a fourth aspect, an embodiment of the present invention further provides a computer storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the method for generating test vectors of a chip provided in any embodiment of the present invention.
The embodiment of the invention can generate the target test vector of the chip to be tested according to the associated operation information by acquiring the associated operation information generated in the process that the test case runs on the chip to be tested in real time, thereby realizing the real-time acquisition of the associated operation information and the generation of the target test vector in any process of the test case running without specially setting a clock frequency signal, without special processing operations such as independently adding a complex log recording module in each test case, and without secondary conversion and special processing of the test vector through manual operation or scripts, the time for generating the test vector is far shorter than that of the prior art, more complex test contents can be accommodated, the problems of low flexibility, low generation efficiency and limited test coverage of the test vector generation in the prior art are solved, and the flexibility of the test vector generation of the chip is optimized, the generation efficiency and the test coverage range of the test vector are improved.
Drawings
Fig. 1 is a flowchart of a method for generating a test vector of a chip according to an embodiment of the present invention.
Fig. 2 is a flowchart of a method for generating test vectors of a chip according to a second embodiment of the present invention.
Fig. 3 is a schematic flowchart of generating a test vector of a chip according to a second embodiment of the present invention.
Fig. 4 is a schematic flowchart of generating a test vector of another chip according to the second embodiment of the present invention.
Fig. 5 is a schematic structural diagram of a test vector generation system of a chip according to a third embodiment of the present invention.
Fig. 6 is a schematic structural diagram of a computer device according to a fourth embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention.
It should be further noted that, for the convenience of description, only some but not all of the relevant aspects of the present invention are shown in the drawings. Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the operations (or steps) as a sequential process, many of the operations can be performed in parallel, concurrently or simultaneously. In addition, the order of the operations may be re-arranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figure. The processes may correspond to methods, functions, procedures, subroutines, and the like.
Example one
Fig. 1 is a flowchart of a method for generating a test vector of a chip according to an embodiment of the present invention, where the present embodiment is applicable to a case of generating a test vector of a chip, and the method can be executed by a device for generating a test vector of a chip according to an embodiment of the present invention, and the device can be implemented by software and/or hardware, and can be generally integrated in a computer device. Accordingly, as shown in fig. 1, the method comprises the following operations:
and S110, acquiring the associated operation information generated in the process that the test case runs on the chip to be tested in real time.
The test case may be data including test input and execution conditions, and may be used to run in the chip to be tested to obtain output of the chip to be tested, so as to test a specific function of the chip to be tested. The chip to be tested can be any chip which needs to test whether the function of the chip meets the requirement, optionally, the chip can be a field programmable logic array or an actual chip platform to be tested, and can be realized by using various software programming languages and scripting languages. The associated operation information may be information generated by an operation in the chip to be tested in a process in which the test case runs on the chip to be tested.
Correspondingly, in the process that the test case runs on the chip to be tested, the chip to be tested can be operated, for example, the control operation on the chip to be tested and/or the read-write access operation on data in the chip to be tested can be performed, so that the associated operation information is generated. In the process that the test case runs on the chip to be tested, the generated associated operation information may be obtained in real time, for example, the associated operation information may include read-write access information and/or control operation information of the chip to be tested.
Optionally, the test case may be connected to the chip to be tested through any test frame or debug tool having a matching interface, so that when the test case runs in the chip to be tested, the associated operation information generated by the operation of the currently running test case on the chip to be tested may be obtained in real time.
And S120, generating a target test vector of the chip to be tested according to the associated operation information.
The target test vector may be vector format data for recording input and output signals of the chip to be tested in a process that the test case runs on the chip to be tested.
Accordingly, the associated operation information may reflect an operation performed by the test case running in the chip to be tested, so that a target test vector of the chip to be tested may be generated according to the associated operation information, for example, the associated operation information may be stored as a file in a target test vector format according to a generation time sequence, so as to generate the target test vector, so that the target test vector may record a corresponding input/output signal of the chip to be tested in the test process.
The embodiment of the invention provides a method for generating test vectors of a chip, which can generate target test vectors of the chip to be tested according to associated operation information by acquiring the associated operation information generated in the process that test cases run on the chip to be tested in real time, realize the real-time acquisition of the associated operation information and the generation of the target test vectors in any process of the test case running, does not need to specially set a clock frequency signal, does not need to independently add a complex log recording module and other special processing operations in each test case, does not need to carry out secondary conversion and special processing on the test vectors through manual operation or scripts, takes far shorter time for generating the test vectors than the existing method, can contain more complex test contents, and solves the problems of low flexibility, low generation efficiency and limited test coverage of the test vectors in the prior art, the flexibility of test vector generation of the chip is optimized, and the generation efficiency and the test coverage range of the test vector are improved.
Example two
Fig. 2 is a flowchart of a method for generating test vectors of a chip according to a second embodiment of the present invention. The embodiment of the invention is embodied on the basis of the above embodiment, and in the embodiment of the invention, a specific optional implementation mode for acquiring the associated operation information generated in the process of running the test case on the chip to be tested in real time is provided.
As shown in fig. 2, the method of the embodiment of the present invention specifically includes:
s210, obtaining the associated operation information generated in the process that the test case runs on the chip to be tested in real time.
In an optional embodiment of the present invention, S210 may specifically include:
s211, calling a target debugging interface.
Wherein the target debug interface comprises a first interface and a second interface.
Specifically, the target debug interface may be an interface for connecting with a chip to be tested. The first interface and the second interface may be two different types of interfaces for connecting with a chip to be tested.
Correspondingly, the target debug interface may be an interface pre-deployed by the test vector generation system of the chip provided according to any embodiment of the present invention, or may be an interface shared by a test framework and/or a debug tool of the chip to be tested. The specific types of the first interface and the second interface may be determined according to the type of the interface used by the chip to be tested, and are not limited herein. By calling the target debugging interface, the connection with the chip to be tested can be established and the information passing through the target debugging interface can be monitored in real time.
Optionally, the first interface may be a JTAG (Joint Test Action Group) interface, and the second interface may be a non-JTAG interface, for example, a PCIE (Peripheral Component Interconnect Express) interface and the like.
S212, acquiring the associated operation information generated in the process that the test case runs on the chip to be tested in real time through the target debugging interface.
Correspondingly, the test case can operate the chip to be tested through the target debugging interface, for example, a JTAG interface debugging tool can be connected with the chip platform to be tested through a JTAG interface, and the test case can access the internal resources of the chip through the JTAG interface through the debugging tool to complete the test of the functions of the chip to be tested; a chip debugging tool based on a PCIE interface may also be deployed to a host connected to a chip to be tested, and the test case may perform access operation of internal resources on the connected chip to be tested through the PCIE interface by using the debugging tool. Therefore, the associated operation information generated by the operation of the test case on the chip to be tested can be obtained in real time by monitoring the operation information in the target debugging interface in real time.
Fig. 3 is a schematic flowchart illustrating a process of generating a test vector of a chip according to an embodiment of the present invention. In a specific example, as shown in fig. 3, the test case is connected to a chip to be tested through a debug tool interface, and the chip to be tested may be a field-editable logic array or a chip system platform, and supports a JTAG interface and a PCIE interface. And monitoring and recording the associated operation information by calling a debugging tool of the corresponding interface, generating a test vector with a specific vector format according to the recorded associated operation information, and finally obtaining the test vector for ATE test.
The embodiment can be embedded into a test framework or a debugging tool corresponding to interfaces supporting a JTAG interface or a PCIE and the like, when the test case starts to run on a built chip platform, all access operation information of the currently running test case to resources such as a chip register, a memory and the like can be recorded in real time, and the universality and the flexibility are greatly improved.
In an optional embodiment of the present invention, the obtaining, in real time, associated operation information generated in a process in which the test case runs on the chip to be tested may include: under a first test mode, acquiring first interface read-write operation information and first interface control operation information generated in the process that a test case runs on a chip to be tested in real time, and determining the first interface read-write operation information and the first interface control operation information as the associated operation information.
The first test mode may be a mode that may be adopted when the associated operation information is acquired through the first interface. The first interface read-write operation information may be information generated by the test case performing read-write operation on the chip to be tested through the first interface. The first interface control operation information may be information generated by the test case performing control operation on the chip to be tested through the first interface.
Correspondingly, the test case can perform read-write operation on the data in the chip to be tested through the first interface, so that the read-write operation information of the first interface is generated. For example, in the case that the first interface is a JTAG interface, the test case may perform read-write access to the register and/or the memory of the chip to be tested through the first interface, so that the read-write operation information of the first interface may include accessed address information, data information, access mode information, and the like.
Furthermore, the test case can also perform control operation on the chip to be tested through the first interface, so as to generate control operation information of the first interface. For example, in a case where the first interface is a JTAG interface, the Test case may control a JTAG TAP (Test Access Port) and/or a JTAG RESET (restart) of the chip to be tested, and the like, so that the first interface control operation information may include a corresponding operation command.
In an optional embodiment of the present invention, the obtaining, in real time, associated operation information generated in a process in which the test case runs on the chip to be tested may include: and under a second test mode, acquiring second interface read-write operation information generated in the process that the test case runs on the chip to be tested in real time, and determining the second interface read-write operation information as the associated operation information.
The second test mode may be a mode that may be adopted when the associated operation information is acquired through the second interface. The second interface read-write operation information may be information generated by the test case performing read-write operation on the chip to be tested through the second interface.
Correspondingly, the test case can perform read-write operation on the data in the chip to be tested through the second interface, so that the read-write operation information of the second interface is generated. For example, in the case that the first interface is a PCIE interface, the test case may perform read-write access to the register and/or the memory of the chip to be tested through the second interface, so that the read-write operation information of the second interface may include accessed address information, data information, access mode information, and the like.
Optionally, the first test mode or the second test mode may be adopted according to the preset of the user, the first test mode or the second test mode may also be determined to be adopted according to the interface type identification information carried in the obtained associated operation information, or a switching rule between the first test mode and the second test mode may be set according to needs, which is not limited herein.
And S220, generating a target test vector of the chip to be tested according to the associated operation information.
In an optional embodiment of the present invention, the generating a target test vector of the chip to be tested according to the associated operation information may include: generating a target signal value sequence according to the first interface read-write operation information and the first interface control operation information; and generating the target test vector of the chip to be tested according to the target signal value sequence.
The target signal value sequence may be a time domain sequence for recording input and output signals of the chip to be tested.
Correspondingly, according to the time sequence for acquiring the read-write operation information of the first interface and the control operation information of the first interface in real time, namely the generation time sequence of the read-write operation information of the first interface and the control operation information of the first interface, the read-write operation information of the first interface and the control operation information of the first interface can be converted into a target signal value sequence, so that the target signal value sequence can be used for recording input and output signals of a chip to be tested in the running process of a test case. Alternatively, the target signal value sequence may be an input-output signal sequence of JTAG IR/DR (Instruction Register/Data Register).
Further, a target test vector that can be used for ATE testing of the chip to be tested can be automatically generated according to the target signal value sequence. Optionally, a test vector file may be generated according to a vector format supported by the ATE test, and the target signal value sequence is stored in the test vector file to generate a target test vector. Illustratively, a target test vector "SIR 8 TDI (21)," SDR 16 TDI (68) TDO (2321) MASK (ffff) "may be generated according to a vector format supported by ATE testing to record IR/DR input and output signals of the chip under test.
In an optional embodiment of the present invention, the generating a target test vector of the chip to be tested according to the associated operation information may include: generating a target signal value sequence according to the read-write operation information of the second interface; and generating the target test vector according to the target signal value sequence.
The target signal value sequence may be a time domain sequence for recording input and output signals of the chip to be tested.
Correspondingly, according to the time sequence of acquiring the read-write operation information of the second interface in real time, the read-write operation information can be converted into a target signal value sequence, so that the target signal value sequence can be used for recording input and output signals of a chip to be tested in the running process of the test case. Furthermore, a target test vector which can be used for the ATE test of the chip to be tested can be automatically generated according to a vector format supported by the ATE test and the target signal value sequence.
In an optional embodiment of the present invention, the second interface read-write operation information may include: reading information of a second interface register, writing information of the second interface register, reading information of a second interface memory and writing information of the second interface memory; the generating a target signal value sequence according to the second interface read-write operation information may include: generating a register read signal subsequence according to the second interface register read information; generating a register write signal subsequence according to the second interface register write information; generating a memory read signal subsequence according to the second interface memory read information; generating a memory write signal subsequence according to the second interface memory write information; and generating the target signal value sequence according to the register read signal subsequence, the register write signal subsequence, the memory read signal subsequence and the memory write signal subsequence.
The second interface register read information may be information generated by the test case through the second interface to perform read operation on the register of the chip to be tested. The second interface register write information may be information generated by the test case performing a write operation on the register of the chip to be tested through the second interface. The second interface memory read information may be information generated by the test case performing a read operation on the memory of the chip to be tested through the second interface. The second interface memory write information may be information generated by the test case performing write operation on the memory of the chip to be tested through the second interface. The register read signal subsequence may be a time domain sequence for recording input and output signals for reading a register of the chip under test. The register write signal subsequence may be a time domain sequence for recording input and output signals for writing to a register of the chip to be tested. The memory read signal subsequence may be a time domain sequence for recording input and output signals for reading the memory of the chip under test. The memory write signal subsequence may be a time domain sequence for recording input and output signals for writing the memory of the chip under test.
Correspondingly, according to the time sequence of acquiring the read information of the second interface register in real time, the read information can be converted into a register read signal subsequence. According to the time sequence of obtaining the writing information of the second interface register in real time, the writing information can be converted into a register writing signal subsequence. According to the time sequence of acquiring the read information of the second interface memory in real time, the read information can be converted into a memory read signal subsequence. According to the time sequence of obtaining the writing information of the second interface memory in real time, the writing information can be converted into a memory writing signal subsequence.
Further, the sequence of target signal values may be generated in time order based on the register read signal subsequence, the register write signal subsequence, the memory read signal subsequence, and the memory write signal subsequence.
For example, the second interface register read information, the second interface register write information, the second interface memory read information, and the second interface memory write information may be respectively generated into corresponding JTAG IR/DR sequences according to a time sequence, so as to obtain a register read signal subsequence, a register write signal subsequence, a memory read signal subsequence, and a memory write signal subsequence, and then generate a target signal value sequence according to the time sequence from the register read signal subsequence, the register write signal subsequence, the memory read signal subsequence, and the memory write signal subsequence, so as to store the target signal value sequence into a test vector file in a vector format supported by ATE testing according to the time sequence, and generate a target test vector.
Fig. 4 is a schematic flowchart illustrating a process of generating a test vector of a chip according to an embodiment of the present invention. In a specific example, as shown in fig. 4, the read-write access operations of the register and the memory are respectively configured to create corresponding individual sub-modules, which include a register read module, a register write module, a memory read module, and a memory write module, where each sub-module is an independent JTAG signal combination sequence template, and the format type is a vector format supported by ATE testing. The information recorded by signal monitoring, such as the accessed address, data, access mode and the like, can be used as input parameters and respectively transmitted to each sub-module for test vector generation according to the operation types, the sub-modules fill the parameters according to respective templates and output respective JTAG IR/DR signal value sequence blocks, and the test vector generation module sequentially stores the output signal sequence of each sub-module into a test vector file according to the time sequence, so that the task of generating a test vector is completed.
The above embodiment can automatically generate a test vector file of the chip, where the test vector file includes a group of complete JTAG IR/DR input/output signal value combinations, and corresponds to read-write access and JTAG control operation behaviors of all resources such as registers and memories involved in the chip test case operation test process.
The embodiment of the invention provides a method for generating test vectors of a chip, which can generate target test vectors of the chip to be tested according to associated operation information by acquiring the associated operation information generated in the process that test cases run on the chip to be tested in real time, realize the real-time acquisition of the associated operation information and the generation of the target test vectors in any process of the test case running, does not need to specially set a clock frequency signal, does not need to independently add a complex log recording module and other special processing operations in each test case, does not need to carry out secondary conversion and special processing on the test vectors through manual operation or scripts, takes far shorter time for generating the test vectors than the existing method, can contain more complex test contents, and solves the problems of low flexibility, low generation efficiency and limited test coverage of the test vectors in the prior art, the flexibility of test vector generation of the chip is optimized, and the generation efficiency and the test coverage range of the test vector are improved.
EXAMPLE III
Fig. 5 is a schematic structural diagram of a test vector generation system of a chip according to a third embodiment of the present invention, and as shown in fig. 5, the apparatus includes: a signal monitoring module 310 and a vector generation module 320.
Wherein the signal monitoring module 310 is communicatively connected to the vector generation module 320. The signal monitoring module 310 is configured to obtain, in real time, associated operation information generated in a process in which a test case runs on a chip to be tested, and send the associated operation information to the vector generating module 320. The vector generating module 320 is configured to receive the correlation operation information, and generate a target test vector of the chip to be tested according to the correlation operation information.
In an optional implementation manner of the embodiment of the present invention, the signal monitoring module 310 may be specifically configured to: calling a target debugging interface; acquiring associated operation information generated in the process that a test case runs on a chip to be tested in real time through the target debugging interface; wherein the target debug interface comprises a first interface and a second interface.
In an optional implementation manner of the embodiment of the present invention, the signal monitoring module 310 may include: a first interface monitoring submodule; the first interface monitoring submodule is configured to, in a first test mode, obtain, in real time, first interface read-write operation information and first interface control operation information generated in a process in which a test case runs on a chip to be tested, determine the first interface read-write operation information and the first interface control operation information as the association operation information, and send the association operation information to the vector generation module 320.
In an optional implementation manner of the embodiment of the present invention, the vector generating module 320 may include: the first interface information processing submodule and the sequence processing submodule; the first interface information processing submodule is in communication connection with the sequence processing submodule; wherein: the first interface information processing submodule is configured to receive first interface read-write operation information and first interface control operation information sent by the first interface monitoring submodule, generate a target signal value sequence according to the first interface read-write operation information and the first interface control operation information, and send the target signal value sequence to the sequence processing submodule; and the sequence processing submodule is used for receiving the target signal value sequence and generating the target test vector of the chip to be tested according to the target signal value sequence.
In an optional implementation manner of the embodiment of the present invention, the signal monitoring module 310 may include: and the second interface monitoring submodule is configured to, in a second test mode, obtain, in real time, second interface read-write operation information generated in a process in which the test case runs on the chip to be tested, determine the second interface read-write operation information as the association operation information, and send the association operation information to the vector generation module 320.
In an optional implementation manner of the embodiment of the present invention, the vector generating module 320 may include: a second interface information processing submodule and a sequence processing submodule; the second interface information processing submodule is in communication connection with the sequence processing submodule; wherein: the second interface information processing submodule is used for receiving the second interface read-write operation information sent by the second interface monitoring submodule, generating a target signal value sequence according to the second interface read-write operation information and sending the target signal value sequence to the sequence processing submodule; and the sequence processing submodule is used for receiving the target signal value sequence and generating the target test vector according to the target signal value sequence.
In an optional implementation manner of the embodiment of the present invention, the second interface read-write operation information includes: reading information of a second interface register, writing information of the second interface register, reading information of a second interface memory and writing information of the second interface memory; the second interface information processing sub-module may include: the device comprises a register reading unit, a register writing unit, a memory reading unit, a memory writing unit and a target signal value sequence output unit; wherein: the register reading unit is used for generating a register reading signal subsequence according to the second interface register reading information; the register writing unit is used for generating a register writing signal subsequence according to the second interface register writing information; the memory reading unit is used for generating a memory reading signal subsequence according to the second interface memory reading information; the memory writing unit is used for generating a memory writing signal subsequence according to the second interface memory writing information; and the target signal value sequence output unit generates the target signal value sequence according to the register read signal subsequence, the register write signal subsequence, the memory read signal subsequence and the memory write signal subsequence.
The device can execute the method for generating the test vector of the chip provided by any embodiment of the invention, and has corresponding functional modules and beneficial effects for executing the method.
The embodiment of the invention provides a test vector generation system of a chip, which can generate a target test vector of the chip to be tested according to the associated operation information by acquiring the associated operation information generated in the process that test cases run on the chip to be tested in real time, realize the real-time acquisition of the associated operation information and the generation of the target test vector in any process of the test case running, does not need to specially set a clock frequency signal, does not need to separately add a complex log recording module and other special processing operations in each test case, does not need to carry out secondary conversion and special processing on the test vector through manual operation or scripts, takes far shorter time for generating the test vector than the prior art, can contain more complex test contents, and solves the problems of low flexibility, low generation efficiency and limited test coverage of the test vector generation in the prior art, the flexibility of test vector generation of the chip is optimized, and the generation efficiency and the test coverage range of the test vector are improved.
Example four
Fig. 6 is a schematic structural diagram of a computer device according to a fourth embodiment of the present invention. FIG. 6 illustrates a block diagram of an exemplary computer device 12 suitable for use in implementing embodiments of the present invention. The computer device 12 shown in FIG. 6 is only an example and should not bring any limitations to the functionality or scope of use of embodiments of the present invention.
As shown in FIG. 6, computer device 12 is in the form of a general purpose computing device. The components of computer device 12 may include, but are not limited to: one or more processors 16, a memory 28, and a bus 18 that connects the various system components (including the memory 28 and the processors 16).
The memory 28 may include computer system readable media in the form of volatile memory, such as Random Access Memory (RAM) 30 and/or cache memory 32. Computer device 12 may further include other removable/non-removable, volatile/nonvolatile computer system storage media. By way of example only, storage system 34 may be used to read from and write to non-removable, nonvolatile magnetic media (not shown in FIG. 6, and commonly referred to as a "hard drive"). Although not shown in FIG. 6, a magnetic disk drive for reading from and writing to a removable, nonvolatile magnetic disk (e.g., a "floppy disk") and an optical disk drive for reading from or writing to a removable, nonvolatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to bus 18 by one or more data media interfaces. Memory 28 may include at least one program product having a set (e.g., at least one) of program modules that are configured to carry out the functions of embodiments of the invention.
A program/utility 40 having a set (at least one) of program modules 42 may be stored, for example, in memory 28, such program modules 42 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each of which examples or some combination thereof may comprise an implementation of a network environment. Program modules 42 generally carry out the functions and/or methodologies of the described embodiments of the invention.
The processor 16 executes various functional applications and data processing by running the program stored in the memory 28, thereby implementing the test vector generation method for a chip according to the embodiment of the present invention: acquiring associated operation information generated in the process that a test case runs on a chip to be tested in real time; and generating a target test vector of the chip to be tested according to the associated operation information.
EXAMPLE five
The fifth embodiment of the present invention provides a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the method for generating a test vector of a chip provided in the fifth embodiment of the present invention is implemented: acquiring associated operation information generated in the process that a test case runs on a chip to be tested in real time; and generating a target test vector of the chip to be tested according to the associated operation information.
Any combination of one or more computer-readable media may be employed. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or computer device. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A method for generating test vectors of a chip is characterized by comprising the following steps:
acquiring associated operation information generated in the process that a test case runs on a chip to be tested in real time; the correlation operation information comprises read-write access information and/or control operation information of the chip to be tested; the chip to be tested is a field programmable logic array or an actual chip platform to be tested;
generating a target test vector of the chip to be tested according to the associated operation information, wherein the target test vector is used for testing the chip in an ATE stage; generating a target test vector of the chip to be tested according to the associated operation information includes:
and storing the associated operation information as a file in a target test vector format according to the generation time sequence.
2. The method according to claim 1, wherein the obtaining of the associated operation information generated in the process of running the test case on the chip to be tested in real time comprises:
calling a target debugging interface;
acquiring associated operation information generated in the process that a test case runs on a chip to be tested in real time through the target debugging interface;
wherein the target debug interface comprises a first interface and a second interface.
3. The method according to claim 1, wherein the obtaining of the associated operation information generated in the process of running the test case on the chip to be tested in real time comprises:
under a first test mode, acquiring first interface read-write operation information and first interface control operation information generated in the process that a test case runs on a chip to be tested in real time, and determining the first interface read-write operation information and the first interface control operation information as the associated operation information.
4. The method of claim 3, wherein the generating the target test vector of the chip under test according to the associated operation information comprises:
generating a target signal value sequence according to the first interface read-write operation information and the first interface control operation information;
and generating the target test vector of the chip to be tested according to the target signal value sequence.
5. The method according to claim 1, wherein the obtaining of the associated operation information generated in the process of running the test case on the chip to be tested in real time comprises:
and under a second test mode, acquiring second interface read-write operation information generated in the process that the test case runs on the chip to be tested in real time, and determining the second interface read-write operation information as the associated operation information.
6. The method of claim 5, wherein the generating the target test vector of the chip under test according to the associated operation information comprises:
generating a target signal value sequence according to the read-write operation information of the second interface;
and generating the target test vector according to the target signal value sequence.
7. The method of claim 6, wherein the reading and writing the operation information by the second interface comprises: reading information of a second interface register, writing information of the second interface register, reading information of a second interface memory and writing information of the second interface memory;
the generating a target signal value sequence according to the second interface read-write operation information includes:
generating a register read signal subsequence according to the second interface register read information;
generating a register write signal subsequence according to the second interface register write information;
generating a memory read signal subsequence according to the second interface memory read information;
generating a memory write signal subsequence according to the second interface memory write information;
and generating the target signal value sequence according to the register read signal subsequence, the register write signal subsequence, the memory read signal subsequence and the memory write signal subsequence.
8. A test vector generation system for a chip, comprising: the device comprises a signal monitoring module and a vector generating module; the signal monitoring module is in communication connection with the vector generation module; wherein:
the signal monitoring module is used for acquiring the associated operation information generated in the process that the test case runs on the chip to be tested in real time and sending the associated operation information to the vector generation module; the correlation operation information comprises read-write access information and/or control operation information of the chip to be tested; the chip to be tested is a field programmable logic array or an actual chip platform to be tested;
the vector generation module is used for receiving the correlation operation information and generating a target test vector of the chip to be tested according to the correlation operation information, wherein the target test vector is used for testing the chip in an ATE stage;
wherein the vector generation module is specifically configured to: and storing the associated operation information as a file in a target test vector format according to the generation time sequence.
9. A computer device, characterized in that the computer device comprises:
one or more processors;
storage means for storing one or more programs;
when executed by the one or more processors, cause the one or more processors to implement a method of test vector generation for a chip as claimed in any one of claims 1 to 7.
10. A computer storage medium on which a computer program is stored, which program, when being executed by a processor, carries out a method of test vector generation for a chip according to any one of claims 1 to 7.
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