CN113839670B - High-performance frequency correction method, frequency correction system and improved phase-locked loop - Google Patents
High-performance frequency correction method, frequency correction system and improved phase-locked loop Download PDFInfo
- Publication number
- CN113839670B CN113839670B CN202111141544.6A CN202111141544A CN113839670B CN 113839670 B CN113839670 B CN 113839670B CN 202111141544 A CN202111141544 A CN 202111141544A CN 113839670 B CN113839670 B CN 113839670B
- Authority
- CN
- China
- Prior art keywords
- frequency
- signal
- module
- mixing
- external reference
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000012937 correction Methods 0.000 title claims abstract description 109
- 238000000034 method Methods 0.000 title claims abstract description 50
- 238000002156 mixing Methods 0.000 claims abstract description 124
- 239000013078 crystal Substances 0.000 claims abstract description 87
- 238000001914 filtration Methods 0.000 claims abstract description 79
- 238000012545 processing Methods 0.000 claims description 52
- 230000015572 biosynthetic process Effects 0.000 claims description 25
- 238000003786 synthesis reaction Methods 0.000 claims description 25
- 238000005259 measurement Methods 0.000 claims description 11
- 238000005516 engineering process Methods 0.000 description 18
- 238000010586 diagram Methods 0.000 description 9
- 230000001276 controlling effect Effects 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 5
- 238000004458 analytical method Methods 0.000 description 4
- 230000003321 amplification Effects 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 229910052792 caesium Inorganic materials 0.000 description 2
- TVFDJXOCXUVLDH-UHFFFAOYSA-N caesium atom Chemical compound [Cs] TVFDJXOCXUVLDH-UHFFFAOYSA-N 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000000875 corresponding effect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 230000007774 longterm Effects 0.000 description 2
- 238000013139 quantization Methods 0.000 description 2
- 229910052701 rubidium Inorganic materials 0.000 description 2
- IGLNJRXAVVLDKE-UHFFFAOYSA-N rubidium atom Chemical compound [Rb] IGLNJRXAVVLDKE-UHFFFAOYSA-N 0.000 description 2
- 238000005070 sampling Methods 0.000 description 2
- 230000032683 aging Effects 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 238000000746 purification Methods 0.000 description 1
- 230000001172 regenerating effect Effects 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- 230000009897 systematic effect Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The present application relates to a high performance frequency correction method, frequency correction system and improved phase locked loop. The method comprises the following steps: acquiring an external reference frequency signal and a frequency correction quantity; the external reference frequency signal is the frequency of the atomic clock; obtaining a first mixing signal and a second mixing signal by adopting a double DDS + double mixing filtering mode according to an external reference frequency signal, a constant temperature crystal oscillator output signal and a frequency correction quantity; inputting the first mixing signal and the second mixing signal into a phase frequency detector, and filtering an output signal of the phase frequency detector by using a loop filter to obtain a voltage control signal; and controlling the voltage control end of the constant temperature crystal oscillator by adopting the voltage control signal until the output signal of the constant temperature crystal oscillator is stabilized at a preset value. In the method, the DDS clock directly adopts an input reference frequency signal without frequency multiplication, so that the quality of an output signal is improved, and the frequency correction resolution and the phase adjustment resolution are improved by adopting a double DDS plus double mixing filtering mode.
Description
Technical Field
The present application relates to the field of precision clock source technology, and in particular, to a high performance frequency correction method, frequency correction system, and improved phase locked loop.
Background
The atomic clock mainly comprises a rubidium atomic clock, a cesium atomic clock and a hydrogen atomic clock, and the frequency stability can reach the magnitude of E-12 to E-16. However, the frequency stability and the frequency accuracy are two different indexes, and the frequency stability and the frequency accuracy are called as the precision together, and the frequency accuracy is different among different atomic clocks, so that the frequency correction technology is derived. The frequency correction technology is a method of correcting the output frequency of a frequency source in a certain mode by knowing or measuring the inherent frequency deviation (within a certain range) of the frequency source, but the frequency accuracy of an atomic clock is good, the frequency correction range is smaller, but the finer correction is needed, and generally, the frequency correction range of +/-1E-18 to +/-1E-7 is enough to meet the requirement.
The method for frequency correction mainly uses two modes of PLL and DDS (Direct Digital Synthesizer) at present, the quality of PLL output signals is good, but the frequency resolution and the frequency accuracy are difficult to reach high, the phase adjustment cannot be realized, the DDS method can be very high in frequency resolution and phase adjustment resolution, but the signal quality is not good due to the influence of truncation errors and the like, and the frequency stability is difficult to be made very high.
At present, the more advanced technology is to adopt a mode of combining DDS and a phase-locked loop, frequency correction utilizes DDS technology, and frequency purification adopts PLL technology. As shown in fig. 1, a clock of a DDS is multiplied by 10MHz, a DDS output frequency is a corrected frequency, where Δ f is an absolute frequency of a frequency correction amount, and a processor calculates a corrected DDS frequency control word and sends the DDS frequency control word to generate the frequency signal. The method of combining the DDS and the phase-locked loop has three problems: (1) clock signals required by the DDS must be multiplied to improve the clock frequency, the frequency multiplication mode generally comprises two modes, namely a phase-locked loop method and a harmonic frequency multiplication method, the two frequency multiplication modes are complex to realize, and indexes have certain loss; (2) when the input frequency and the output frequency have no frequency difference, the short-term stability loss of the output frequency is small, and after the output frequency and the input frequency have frequency correction, the output short-term stability is obviously influenced due to frequency multiplication factors, and the influence degree is different along with the frequency deviation; (3) when the DDS clock frequency is too high, the quantization bit number is difficult to be very high, the DAC output performance index can be influenced, the stray and harmonic of an output signal can be increased inevitably, the output signal of the DAC has certain influence on a phase-locked loop inevitably, and therefore the quality of the output signal is influenced.
Disclosure of Invention
In view of the above, it is desirable to provide a high performance frequency correction method, a frequency correction system and an improved phase locked loop.
A high performance frequency correction method, the method comprising:
acquiring an external reference frequency signal and a frequency correction quantity; the external reference frequency signal is the frequency of an atomic clock;
obtaining a first mixing signal and a second mixing signal by adopting a double DDS + double mixing filtering mode according to the external reference frequency signal, the constant temperature crystal oscillator output signal and the frequency correction quantity; the first mixing signal is a sine wave signal with a preset frequency, and the second mixing signal is a sine wave signal with a corrected frequency;
inputting the first mixing signal and the second mixing signal into a phase frequency detector, and filtering an output signal of the phase frequency detector by using a loop filter to obtain a voltage control signal;
and controlling the voltage control end of the constant temperature crystal oscillator by using the voltage control signal until the output signal of the constant temperature crystal oscillator is stabilized at a preset value.
A high-performance frequency correction system comprises a frequency divider, a main control computer, a double-circuit DDS module, two mixing filtering branches, a phase frequency detector, a loop filter and a constant-temperature crystal oscillator; the two-way DDS module comprises a first DDS module and a second DDS module;
the frequency divider is used for receiving the external reference frequency signal, performing frequency division processing on the external reference frequency signal to obtain three paths of frequency division signals, taking the first path of frequency division signal as a main frequency signal of the main control computer, inputting the second path of frequency division signal to the first input end of the first frequency mixing filtering branch, and taking the third path of frequency division signal as a DDS clock of the two-path DDS module;
the main control computer is used for converting the frequency correction quantity into a frequency control word and sending the frequency control word to the second DDS module;
the first DDS module is used for carrying out frequency synthesis on a DDS clock to obtain a first synthesis frequency signal; the output end of the first DDS module is connected with the second input end of the first frequency mixing filtering branch circuit;
the second DDS module is configured to perform frequency synthesis according to the frequency control word and the DDS clock to obtain a second synthesized frequency signal, and an output end of the second DDS module is connected to a second input end of the second mixing filter branch;
the first frequency mixing and filtering branch is used for carrying out frequency mixing and filtering processing on the received second path of frequency division signals and the first synthesized frequency signals and outputting first frequency mixing signals to a first input end of the phase frequency detector;
the second frequency mixing and filtering branch is used for carrying out frequency mixing and filtering processing on a second path of frequency division signals input by the first input end and constant temperature crystal oscillator output signals input by the second input end and outputting second frequency mixing signals to the second input end of the phase frequency detector;
the output end of the phase frequency detector is connected with the input end of the loop filter, the output end of the loop filter is connected with the voltage control end of the constant temperature crystal oscillator, the output end of the constant temperature crystal oscillator is used as the system output end, and when the system is stable, a frequency signal with corrected frequency is output.
An improved phase-locked loop comprises a phase frequency detector, a loop filter, a constant temperature crystal oscillator and a feedback loop, wherein the feedback loop comprises a frequency division module; the frequency mixing and filtering module comprises a frequency mixer and a filtering module;
the improved phase-locked loop further comprises an external reference frequency processing module, wherein an input end of the external reference frequency processing module acquires an external reference frequency signal and a frequency correction quantity, the external reference frequency processing module is used for carrying out frequency synthesis and frequency mixing filtering processing on the external reference frequency signal by adopting a two-way DDS + frequency mixing filtering mode according to the external reference frequency signal and the frequency correction quantity to obtain a first homologous external reference and a second homologous external reference, and the first homologous external reference is a frequency signal with a determined frequency value; the second homologous external reference is a frequency signal containing frequency correction information;
the first input end of the frequency mixer is connected with the output end of the constant-temperature crystal oscillator, the second input end of the frequency mixer is connected with the second output end of the external reference frequency processing module, the output end of the frequency mixer is connected with the input end of the filtering module, and the output end of the filtering module is connected with the second input end of the phase frequency detector; the first input end of the phase frequency detector is connected with the first output end of the external reference frequency processing module, the output end of the phase frequency detector is connected with the input end of the loop filter, and the output end of the loop filter is connected with the voltage control module of the constant temperature crystal oscillator.
The high-performance frequency correction method, the frequency correction system and the improved phase-locked loop comprise the following steps: acquiring an external reference frequency signal and a frequency correction quantity; the external reference frequency signal is the frequency of the atomic clock; obtaining a first mixing signal and a second mixing signal by adopting a double DDS + double mixing filtering mode according to an external reference frequency signal, a constant temperature crystal oscillator output signal and a frequency correction quantity; inputting the first mixing signal and the second mixing signal into a phase frequency detector, and filtering an output signal of the phase frequency detector by using a loop filter to obtain a voltage control signal; and controlling the voltage control end of the constant temperature crystal oscillator by adopting the voltage control signal until the output signal of the constant temperature crystal oscillator is stabilized at a preset value. In the method, the DDS clock directly adopts an input reference frequency signal without frequency multiplication, so that the quality of an output signal is improved, and the frequency correction resolution and the phase adjustment resolution are improved by adopting a double DDS plus double mixing filtering mode.
Drawings
Fig. 1 is a schematic diagram of a conventional frequency correction method;
FIG. 2 is a flow diagram of an embodiment of a high performance frequency correction method;
FIG. 3 is a schematic flow chart of a two-way DDS + two-way mixing filtering step in another embodiment;
FIG. 4 is a functional block diagram of a high performance frequency correction system in accordance with another embodiment;
fig. 5 is an improved phase-locked loop structure in another embodiment;
FIG. 6 is a system diagram of a high accuracy frequency correction method in another embodiment;
fig. 7 is a block diagram of a mixer according to another embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
In one embodiment, as shown in fig. 2, a high performance frequency correction method is provided, the method comprising the steps of:
step 100: an outer reference frequency signal and a frequency correction amount are obtained.
The external reference frequency signal is the frequency of the atomic clock; the atomic clock may be a rubidium atomic clock, a cesium atomic clock, a hydrogen atomic clock, or other types of atomic clocks.
The frequency correction is required to be 1E-18 to 1E-7 according to the current frequency correction technology, since 1E-7 and 1E-18 are relative quantities, for example: the absolute frequency quantity converted into the frequency correction quantity with respect to 10MHz is: 10-11Hz-1Hz。
Step 102: and obtaining a first mixing signal and a second mixing signal by adopting a double DDS + double mixing filtering mode according to the external reference frequency signal, the constant temperature crystal oscillator output signal and the frequency correction quantity.
The double DDS + double mixing filtering mode is that the main control computer generates frequency control words according to the received frequency correction quantity, and performs frequency synthesis, mixing and filtering processing, namely a first mixing signal and a second mixing signal, by adopting a mode of combining a double DDS module with a double mixing filtering branch circuit according to an external reference frequency signal, a constant temperature crystal oscillator output signal and the frequency control words. The first mixing signal is a sine wave signal with a preset frequency, and the second mixing signal is a sine wave signal with a corrected frequency.
The two-way DDS module comprises two DDS modules, wherein the frequency of the output signal of the first DDS module is 0.7MHz, the frequency of the output signal of the second DDS module is 0.7 MHz-delta f, and the delta f is the absolute frequency quantity of the frequency correction quantity. Because the DDS output frequency is lower, the clock frequency can directly adopt the input reference frequency signal, and compared with the conventional method (the DDS clock needs frequency multiplication), the method has obvious superiority on the quality of the output signal.
The absolute frequency quantity of the frequency correction quantity is: 10-11Hz-1Hz, therefore frequencyThe minimum frequency resolution of the absolute frequency quantity of the rate correction quantity should be 10-11Hz, thus needs to satisfy 107/2N≤10-11It can be calculated that N is more than or equal to log21018Since N can only be integers, the minimum N value is 60, and N is the power of 2, the frequency control word can be 64 bits, the frequency resolution has a certain margin, and the error of the control frequency precision is reduced by 264-6016 times, the frequency is convenient to control accurately. The frequency adjustment resolution reaches 5.4E-20, and the phase adjustment resolution is superior to the femtosecond precision.
When the external reference frequency signal is 10MHz, the frequency of the first mixing signal is 10.7MHz, and the frequency of the second mixing signal is 10.7MHz- Δ f ', where Δ f' is the difference between the absolute frequency amount of the frequency correction and the actual frequency correction of the system.
Step 104: and inputting the first mixing signal and the second mixing signal into the phase frequency detector, and filtering an output signal of the phase frequency detector by adopting a loop filter to obtain a voltage control signal.
The loop filter is a low pass filter. The voltage control signal is a voltage signal.
And inputting the first mixing signal and the second mixing signal into a phase frequency detector to obtain a signal with the frequency delta f', and performing low-pass filtering on the signal to obtain a voltage control signal for controlling the constant-temperature crystal oscillator.
Step 106: and controlling the voltage control end of the constant temperature crystal oscillator by adopting the voltage control signal until the frequency of the output signal of the constant temperature crystal oscillator is stabilized at a preset value.
Preferably, the preset value is 10MHz + Δ f.
When the difference value delta f' between the absolute frequency quantity delta f of the frequency correction quantity and the actual frequency correction quantity of the system is 0, the frequency of the output signal of the constant temperature crystal oscillator is stabilized at a preset value.
In the above method for high performance frequency correction, the method includes: acquiring an external reference frequency signal and a frequency correction quantity; the external reference frequency signal is the frequency of the atomic clock; obtaining a first mixing signal and a second mixing signal by adopting a double DDS + double mixing filtering mode according to an external reference frequency signal, a constant temperature crystal oscillator output signal and a frequency correction quantity; inputting the first mixing signal and the second mixing signal into a phase frequency detector, and filtering an output signal of the phase frequency detector by using a loop filter to obtain a voltage control signal; and controlling the voltage control end of the constant temperature crystal oscillator by adopting the voltage control signal until the output signal of the constant temperature crystal oscillator is stabilized at a preset value. In the method, the DDS clock directly adopts an input reference frequency signal without frequency multiplication, so that the quality of an output signal is improved, and the frequency correction resolution and the phase adjustment resolution are improved by adopting a double DDS plus double mixing filtering mode.
In one embodiment, as shown in the flowchart of fig. 3, step 102 specifically includes the following steps:
step 200: and frequency division is carried out on the external reference frequency signal to obtain three paths of frequency division signals.
Step 201: the first path of frequency division signal is used as the main frequency of a main control computer, and the second path of frequency division signal is used as a DDS clock of a double-path DDS module; the double-circuit DDS module comprises a first DDS module and a second DDS module.
Step 202: and processing the second path of frequency division signal by a first DDS module to obtain a first digital synthesis frequency.
Step 203: and performing frequency mixing processing on the first digital synthesis frequency and the third frequency division signal through a first frequency mixer, and performing narrow-band-pass filtering processing on the signal after the frequency mixing processing to obtain a first frequency mixing signal.
Step 204: and converting the frequency correction quantity into a frequency control word through a main control machine, issuing the frequency control word to a second DDS module, and processing a second path of frequency division signal through the second DDS module to obtain a second digital synthesis frequency.
Step 205: and carrying out frequency mixing processing on the second digital synthesis frequency and the constant-temperature crystal oscillator output signal through a second frequency mixer, and carrying out narrow-band-pass filtering processing on the signal after frequency mixing processing to obtain a second frequency mixing signal.
In one embodiment, step 200 is preceded by: and detecting the external reference frequency signal to obtain an external reference frequency value.
In one embodiment, step 200 comprises: when the external reference frequency value is 5MHz, carrying out frequency doubling processing on the external reference frequency signal to obtain a frequency-doubled external reference frequency signal; and frequency division is carried out on the frequency-multiplied external reference frequency signal to obtain three paths of frequency division signals.
The conventional frequency correction equipment only can be fixed aiming at 10MHz or 5MHz, but can not be compatible with the conventional frequency correction equipment, the method considers the 10MHz and 5MHz input conditions in the design, can automatically detect and identify input signals, and automatically switches output signals, so that the output and the input are matched.
In one embodiment, step 205 comprises: when the external reference frequency value is 5MHz, the output end of the constant temperature crystal oscillator is subjected to frequency division by two and then output, and a constant temperature crystal oscillator output signal subjected to frequency division by two is obtained; and performing frequency mixing processing on the second digital synthesis frequency and the constant-temperature crystal oscillator output signal subjected to the frequency division by two through a second frequency mixer, and performing narrow-band-pass filtering processing on the signal subjected to the frequency mixing processing to obtain a second frequency mixing signal.
It should be understood that although the various steps in the flow charts of fig. 2-3 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not limited to being performed in the exact order illustrated and, unless explicitly stated herein, may be performed in other orders. Moreover, at least some of the steps in fig. 2-3 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternating with other steps or at least some of the sub-steps or stages of other steps.
In one embodiment, as shown in fig. 4, a high performance frequency correction system is provided, which includes a frequency divider, a main controller, a two-way DDS module, two mixing and filtering branches, a phase frequency detector, a loop filter, and a constant temperature crystal oscillator; the double-circuit DDS module comprises a first DDS module and a second DDS module. In fig. 4, the frequency of the external reference frequency signal is 10MHz for example, and the frequency calculation and marking are performed on each signal in the signal stream.
And the frequency divider is used for receiving the external reference frequency signal, performing frequency division processing on the external reference frequency signal to obtain three paths of frequency division signals, taking the first path of frequency division signal as a main frequency signal of the main control computer, inputting the second path of frequency division signal to the first input end of the first frequency mixing filtering branch, and taking the third path of frequency division signal as a DDS clock of the two-path DDS module.
And the main control machine is used for converting the frequency correction quantity into a frequency control word and sending the frequency control word to the second DDS module.
The first DDS module is used for carrying out frequency synthesis on a DDS clock to obtain a first synthesis frequency signal; the output end of the first DDS module is connected with the second input end of the first frequency mixing filtering branch circuit.
And the second DDS module is used for carrying out frequency synthesis according to the frequency control word and the DDS clock to obtain a second synthesis frequency signal, and the output end of the second DDS module is connected with the second input end of the second mixing filtering branch.
And the first frequency mixing and filtering branch is used for carrying out frequency mixing and filtering processing on the received second path of frequency division signal and the first synthesized frequency signal and outputting the first frequency mixing signal to a first input end of the phase frequency detector.
And the second frequency mixing and filtering branch is used for carrying out frequency mixing and filtering processing on the second path of frequency division signals input by the first input end and the constant temperature crystal oscillator output signals input by the second input end and outputting second frequency mixing signals to the second input end of the phase frequency detector.
The output end of the phase frequency detector is connected with the input end of the loop filter, the output end of the loop filter is connected with the voltage control end of the constant temperature crystal oscillator, the output end of the constant temperature crystal oscillator is used as the system output end, and when the system is stable, a frequency signal with corrected frequency is output.
In one embodiment, the system further comprises a frequency measuring module, a judging module, a switching module and a frequency doubling module; the input end of the frequency measurement module is used for receiving an external reference frequency signal, the output end of the frequency measurement module is connected with the input end of the judgment module, the output end of the judgment module is connected with the control end of the switching module, the input end of the switching module receives the external reference frequency signal, the first output end of the switching module is connected with the input end of the frequency doubling module, the second output end of the judgment module is connected with the input end of the frequency division module, and the output end of the frequency doubling module is connected with the input end of the frequency division module.
In one embodiment, the system further comprises a frequency measuring module, a judging module, a switching module and a frequency halving module; the input end of the frequency measurement module is used for receiving an external reference frequency signal, the output end of the frequency measurement module is connected with the input end of the judgment module, the output end of the judgment module is connected with the control end of the switching module, the input end of the switching module is connected with the output end of the constant-temperature crystal oscillator, the first output end of the switching module is connected with the input end of the halving frequency module, the second output end of the judgment module is connected with the input end of the second frequency mixing filtering branch, and the output end of the halving frequency module is connected with the input end of the second frequency mixing filtering branch.
In one embodiment, the frequency of the external reference frequency signal is 10MHz or 5 MHz; the output frequency of the constant temperature crystal oscillator is 10 MHz.
In one embodiment, as shown in fig. 5, an improved phase-locked loop is provided, where the phase-locked loop includes a phase frequency detector, a loop filter, a constant temperature crystal oscillator, and a feedback loop, where the feedback loop includes a frequency division module, and the improved phase-locked loop is obtained by replacing the frequency division module of the feedback loop with a frequency mixing and filtering module based on a classical phase-locked loop; the frequency mixing and filtering module comprises a frequency mixer and a filtering module;
the improved phase-locked loop further comprises an external reference frequency processing module, wherein an input end of the external reference frequency processing module acquires an external reference frequency signal and frequency correction quantity, the external reference frequency processing module is used for carrying out frequency synthesis and frequency mixing filtering processing on the external reference frequency signal by adopting a two-way DDS + frequency mixing filtering mode according to the external reference frequency signal and the frequency correction quantity to obtain a first homologous external reference and a second homologous external reference, and the first homologous external reference is a frequency signal determined by a frequency value; the second homologous external reference is a frequency signal containing information of the frequency correction amount;
the first input end of the frequency mixer is connected with the output end of the constant-temperature crystal oscillator, the second input end of the frequency mixer is connected with the second output end of the external reference frequency processing module, the output end of the frequency mixer is connected with the input end of the filtering module, and the output end of the filtering module is connected with the second input end of the phase frequency detector; the first output end of the external reference frequency processing module at the first input end of the phase frequency detector is connected, the output end of the phase frequency detector is connected with the input end of the loop filter, and the output end of the loop filter is connected with the voltage control module of the constant temperature crystal oscillator.
In a specific embodiment, the frequency fine tuning and the phase fine tuning mainly aim at frequency and phase correction of a precise time source such as an atomic clock, continuous and stable output of signals needs to be kept in the process of correction, the aim is to adjust the frequency and the phase of input within a certain range, the method adopts a structure combining double mixing and a phase-locked loop, the system principle of the high-precision frequency correction method is shown in fig. 6, and the frequency value of each signal is calculated and marked by taking the external reference frequency signal as 10MHz as an example in fig. 6.
The method skillfully adopts the signals output by the double mixing filter as two input signals of the phase frequency detector in the phase-locked loop, and fixes the frequency detection frequency at 10.7MHz by utilizing the mature intermediate frequency 10.7MHz crystal filtering technology. The method is realized in the following specific mode:
after an external reference 10MHz signal needing frequency correction is input into a system, frequency distribution and amplification are carried out, the frequency distribution and amplification are carried out, one for three, the frequency distribution and amplification are respectively sent to a DDS module, a main control module and a mixer 1, the DDS module consists of two sub-modules, namely DDS1 and DDS2, an implementation mode of FPGA + DAC can be adopted, a working clock of the DDS module is a 10MHz signal sent by a frequency division module, DDS1 outputs a sine wave signal with the frequency of 0.7MHz, DDS2 outputs a sine wave signal with the frequency of (0.7 MHz-delta f), delta f is an absolute frequency quantity of frequency correction quantity, calculation is carried out according to the maximum correction quantity of 1E-7, the maximum value of an absolute value of frequency correction under the 10MHz reference frequency is 1Hz, namely, delta f is not less than 1Hz and not more than 1Hz, the frequency correction quantity is generated after the frequency correction quantity is input through a man-machine interface by a main control, and the DDS generates a frequency control word, and the frequency control word is sent to the frequency control word to the 2 module by the main control. Due to DDS inputThe clock is directly from the external reference 10MHz, so the frequency stability of the output signals of DDS1 and DDS2 is close to the frequency stability of the input 10MHz, and the loss degree mainly comes from the loss caused by the digital implementation. The two inputs of the mixer 1 are respectively the 10MHz signal of the external reference and the 0.7MHz signal generated by the DDS. The output of the mixer 1 is the sum frequency and the difference frequency of 10MHz and 0.7MHz, respectively 10.7MHz and 9.3MHz, a 10.7MHz crystal filter 1 module is connected behind the mixer 1, because the crystal filter characteristic is a band-pass filter with the center frequency of 10.7MHz and the bandwidth of several kilohertz, and 9.3MHz is not in the range of the pass band, thus, the signal passes through the crystal filter and then the 9.3MHz signal is removed, and the 10.7MHz signal is remained. The two inputs of the mixer 2 are the sine wave signal (0.7 MHz-Deltaf) generated by DDS2 and the output signal of the constant temperature crystal oscillator, and now it is assumed that the output frequency of the constant temperature crystal oscillator is foAccording to the frequency characteristic of the constant temperature crystal oscillator, the frequency shift controllable range of the 10MHz constant temperature crystal oscillator is controlled to be only a range of a few Hertz through a voltage control end, and thus the mixed signal is f1＝(fo+0.7 MHz-. DELTA.f) and f2＝(fo-0.7MHz + Δ f) two frequency signals, it is clear that f1Around 10.7MHz, with a maximum offset in the range of only a few hertz, within the passband of the crystal filter 2, and f2Is in the vicinity of 9.3MHz, in the stopband range of the crystal filter 2, so that, after passing through the crystal filter 2, the signal leaves only f1＝(fo+0.7MHz- Δ f). f. of1The signal of 10.7MHz that is outputted with the crystal filter 1 inputs the phase frequency detector together, the phase frequency detector connects with the loop filter (low-pass filter), the voltage controlled end of the crystal oscillator of constant temperature of direct control of the signal after filtering, because the input frequency of the phase frequency detector is a fixed frequency 10.7MHz, one is the signal correlated to crystal oscillator output frequency signal of constant temperature, for a certain frequency correction amount, 0.7MHz- Δ f is the known fixed frequency signal, in this way, have formed the phase-locked loop structure as shown in fig. 5.
As can be seen from FIG. 5, two homologous external reference signals 1 and 2 are derived from the input external reference 10MHz signal, and the corresponding output frequencies are 10.7MHz and 0.7MHz-Δ f, generated by DDS in combination with mixing and filtering techniques, as described in detail above. From the view of an equivalent system block diagram, the system is an improved phase-locked loop structure, and the difference is mainly that a frequency division module of a feedback loop is replaced by a frequency mixing and filtering module, and from the view of the whole function, the frequency mixing and filtering system forms a complete phase-locked loop structure, and according to the characteristics of the phase-locked loop, the phase-locked loop meets the relationship that two input frequencies of a phase frequency detector are equal and phases are close, namely the relationship is shown as the formula (1). Therefore, the output frequency f of the constant temperature crystal oscillator can be easily calculatedoComprises the following steps: f. ofo10MHz + Δ f, Δ f is the absolute frequency quantity of the frequency correction.
fo+0.7MHz-Δf＝10.7MHz (1)
In the embodiment, a traditional phase-locked loop structure is skillfully transformed, the DDS technology is utilized to conveniently adjust the frequency resolution, the mixing technology and the mature 10.7MHz intermediate frequency filtering technology are utilized to construct a skillful and precise frequency correction technology, and the specific implementation and technical index analysis are as follows.
Some key devices in the middle of the structural block diagram need certain requirements for selection, it is obvious from the structural block diagram of the system that the corrected frequency is output by a constant-temperature crystal oscillator, the characteristic of the constant-temperature crystal oscillator is that the short-term stability is better, the long-term stability is influenced by aging, temperature drift, time drift and the like rather than being too good, the structural characteristic of the phase-locked loop is not difficult to see, the short-stability characteristic output by the constant-temperature crystal oscillator follows the characteristic of the constant-temperature crystal oscillator, the long-stability characteristic follows the characteristic of external reference, and the demarcation point is the size of the loop bandwidth, namely the bandwidth of the low-pass filter. The method needs a constant-temperature crystal oscillator with better short stability as a voltage-controlled source, the short stability (instable in seconds or instable in milliseconds) of the constant-temperature crystal oscillator is better than that of an input reference signal, the input signal is an atomic clock, the short stability of the atomic clock is generally about 1E-12 magnitude, and the scheme selects the constant-temperature crystal oscillator with instable in seconds of E-13 magnitude as the voltage-controlled clock source.
The loop bandwidth is determined by the loop filter, the charge pump phase-locked loop structure is adopted in the embodiment, the noise of the phase-locked loop is required to be low, the loop filter adopts a passive second-order resistance-capacitance low-pass filter, the loop wiring is required to be short, and the interference is avoided as much as possible.
The mixer in this embodiment is a non-linear device, and therefore may bring a certain influence on the quality of a signal, and generally may be implemented by using an active multiplier or a passive double-balanced mixing technology, because the active multiplier may bring extra noise interference, the embodiment uses the passive double-balanced mixing technology, and a structural block diagram of the mixer is shown in fig. 7, where ports 1 and 2, ports 7 and 8 correspond to two paths of signal inputs, ports 3 and 4 are generally grounded or fixed reference levels, and ports 5 and 6 are output signals. The crystal filter in the scheme is a crystal filter with the center frequency of 10.7MHz, the requirements are that the insertion loss of a pass band is small, the attenuation of a stop band is large, at present, the insertion loss of a better crystal filter on the market can be not more than 2dB, the attenuation of the stop band at the far end is better than 80dB, the bandwidth can be thousands of hertz, the narrow-band characteristic can filter various harmonics, interferences and aliasing signals to the maximum extent, the signals are purified to the maximum extent, and the characteristics can meet the requirements of the system.
Besides, the DDS technology is a more critical link in the scheme, firstly, the DDS always comes from an input reference clock signal, namely a 10MHz reference signal, a sine wave signal about 0.7MHz is generated by a 10MHz clock, the sampling rate of the DDS is far greater than the Nyquist sampling theorem, the ratio of the clock frequency to the output frequency is greater than 14 times, reconstruction of the sine wave signal is well met, certainly, a DAC of a DDS module is a more critical device, the effective quantization bit can reach more than 16 bits, the performance requirement is stable, the drift is small, the data rate meets the requirement superior to 10^7(SA/S), a seven-order elliptic filter is connected after the DAC in the DDS module outputs, stepped waves related to the clock frequency are filtered to the maximum extent, and signal aliasing of a mixing link is avoided. In addition, the clock of the DDS module is derived from an external 10MHz sine wave signal, and the sine wave signal needs to be converted into a square wave signal as the clock, and here, a high-performance sine wave-to-square wave device, such as a chip like LTC6957, can be used, so that the smaller the clock jitter is, the better the clock jitter is.
From the above analysis, all reference frequency signals in the improved pll are derived from the inputThe long-term frequency stability of the input reference 10MHz signal is inherited to the input reference 10MHz, and the short-term stability is ensured by the constant temperature crystal oscillator, so that the short stability and the long stability of the output signal can be ensured. On the premise that the system can work stably, a specific method for frequency correction is specifically analyzed. From the system structure, there are two DDS output signals, DDS1 and DDS2, and theoretical analysis shows that, DDS1 outputs fixed 0.7MHz, DDS2 outputs 0.7MHz- Δ f, and Δ f is the absolute frequency quantity of the frequency correction quantity. The bit width of the frequency control word needs to be considered, which can be easily obtained by the DDS principle, and the frequency resolution of the DDS output signal is as follows: df is fS/2N(fSFor the clock frequency, here 10MHz, N is the bit width of the frequency control word), the amount of frequency correction is 1E-18 to 1E-7 according to the current technical requirement of frequency correction, since 1E-7 and 1E-18 are relative amounts, the conversion to absolute frequency amount with respect to 10MHz is: 10-11Hz-1Hz, so that the minimum frequency resolution should be 10-11Hz, thus needs to satisfy 107/2N≤10-11It can be calculated that N is more than or equal to log21018Since N can only be integers, the minimum N value is 60, and N is the power of 2, the frequency control word can be 64 bits, the frequency resolution has a certain margin, and the error of the control frequency precision is reduced by 264-6016 times, the frequency is convenient to control accurately. However, in the case of using a frequency-multiplied 100MHz clock according to a conventional DDS method, if the same frequency resolution is reached, the bit width of the frequency control word needs 64 bits at the minimum, and the bit width of the frequency control word using 64 bits has no margin, which just meets the requirements of the system. Therefore, the present method is more fine in frequency control than the conventional method.
From the above analysis, it can be seen that the DDS frequency control word of the system can be defined as 64 bits, and the DDS output frequency fo(DDS)And a frequency control word fcMagnitude, clock frequency fsAnd the relation of the bit width N of the frequency control word is as follows: f. ofo(DDS)＝fc·fs/2NSince the output bit of DDS1 is fixed at 0.7MHz, the frequency control of DDS1 can be easily calculatedThe system word is fC1＝0.7×106×264/(10×106) The fractional part has a value of 0.12, and since the frequency control word can only take an integer, the error of the output frequency can be calculated as: Δ f1＝0.12×10*106/264＝6.5×10-14(Hz) the frequency error is 1 x 10 greater than the minimum frequency resolution requirement-11(Hz) is at least 2 orders of magnitude lower, and the effect of this error is almost negligible. The output frequency of the DDS2 is adjustable around 0.7MHz, and the frequency correction is implemented in this link, and it is analyzed how the input frequency correction corresponds to the frequency control word output by the DDS 2. In general, the frequency correction is expressed in relative terms, according to the range of adjustment 1E-18 to 1E-7, now according to the 10MHz reference signal, assuming a frequency correction of fEIf the absolute frequency of the frequency correction is Δ f 107·fEThe frequency control word corresponding to DDS2 is shown in equation (2). Changing Δ f to 107·fEFormula (3) is obtained by substituting formula (2), and the frequency control word of DDS2 can be obtained by formula (3) directly according to the frequency correction amount. The maximum frequency control error value is: 5.4X 10-13Hz, relative frequency error of 5.4X 10-20And is an order of magnitude better than the minimum frequency correction resolution 1E-18. The influence on the systematic error is small, and the influence on the error can be ignored.
fC2＝(0.7×106-Δf)×264/(10×106) (2)
fC2＝(0.7×106-107×fE)×264/(10×106) (3)
The frequency adjustment is realized by adjusting the frequency to realize the phase adjustment method and realize the precise and continuous phase adjustment technology, the 64-bit frequency control word in DDS2 is utilized, the amount of the phase locking and adjusting frequency is calculated according to the total phase adjustment amount and the adjustment completion time, the adjustment is divided into lead and lag, the adjustment is realized by adjusting the frequency up and down, the integral of the frequency to the time is the phase, the frequency adjustment amount can be determined after the integral time and the total adjustment phase are determined, the original frequency is recovered after the adjustment is completed, and the phase difference is not changed any more.
Generally, the phase adjustment amount is required to be 1 μ s and the resolution is 1 ps. The phase adjustment is realized by frequency adjustment, the frequency control word of the DDS is changed, and the phase adjustment can be calculated by returning to the original frequency after a period of time. The adjustment can be realized in two ways, the first way is to fix the adjustment frequency value and realize the phase modulation by adjusting the time length, and the second way is to fix the adjustment time length, calculate the frequency required to be adjusted and also realize the phase modulation. The two modes have advantages and disadvantages, the first mode has longer adjusting time if the phase adjusting amount is too large, and the second mode has larger frequency adjusting amount if the phase adjusting amount is too large, thereby influencing the frequency stability index. The phase is obtained by integrating the frequency, so that the phase adjustment can be obtained according to the frequency adjustment and the adjustment time, i.e.
(Δ T is the length of the adjustment period,
is phase adjustment amount), and then is converted into a time value according to the phase value, and the conversion relationship is as follows:
for phase-shift time value, fsIs 10MHz, can be easily obtained,
generally, the phase adjustment can be adjusted in four steps of 10 seconds, 100 seconds and 1000 seconds according to the magnitude of the phase adjustment amount, and the phase adjustment range of the 1000 second step is as follows: phase modulation of 10ns-1us, 100 second gearThe whole range is as follows: the phase adjustment range of 100ps-10ns and 10 second gear is as follows: 1ps to 100ps, from which the maximum frequency adjustment value can be calculated, for example, 1us adjustment value, since it is the maximum adjustment phase, the frequency adjustment value is the maximum frequency adjustment value of the system,
bringing in to obtain Δ fmaxThe frequency adjustment range of the oven controlled crystal oscillator is several hertz (Hz), so that the phase adjustment can be realized in the whole adjustment range. The phase adjustment resolution is determined according to the gear 10 second adjustment time with the shortest time and the frequency adjustment resolution,
the phase modulation resolution is better than one thousandth of a femtosecond.
The constant temperature crystal oscillator generally outputs fixed 10MHz, but the common frequency input by the atomic clock is 10MHz or 5MHz, if 5MHz is input, the input 5MHz reference signal firstly passes through a frequency multiplier (the frequency multiplication can be realized by two inputs of a common multiplier or a frequency mixer being the same 5 MHz), the frequency multiplied signal is changed into a 10MHz signal, the other processing methods are the same method, but the output signal of the constant temperature crystal oscillator needs to be subjected to frequency division to output a 5MHz frequency correction signal, and in order to improve the quality of the frequency division output signal, a regenerative frequency division technology can be adopted. Since the frequency correction is performed by the relative frequency correction method, and the frequency correction amount of 5MHz is also applied to the frequency correction method of 10MHz, both the frequency correction method and the phase correction method can be applied. An input signal frequency measuring module is added in the actual design, the frequency measuring module adopts equal precision measuring technology to judge whether the frequency is normal or not, and judges whether the frequency is 5MHz or 10MHz, and further, the input frequency is directly input or input through a frequency doubling module, an alternative relay can be adopted for selection, and the output signal can also be output by adopting a relay to control whether the input frequency is directly output by a constant temperature crystal oscillator or output by a frequency dividing module.
The method for correcting the frequency has the advantages that:
(1) the phase adjustment amount reaches 1 mu s, the phase modulation resolution is better than one thousandth of femtosecond, and the phase modulation resolution is improved by 3 orders of magnitude compared with the conventional method;
(2) frequency adjustment amount: 1E-7; resolution ratio: 5.4E-20, an order of magnitude higher than achieved by conventional methods.
(3) The system background test results are as follows: the second stability index is superior to 3E-13, the 10 second stability reaches 3.2E-14, the 100 second stability reaches 3.5E-15, the 1000 second stability reaches 3.8E-16, the stability shows a linear descending trend approximately according to time, under the condition of frequency correction, the stability measurement result is approximately equal to that without frequency correction, the additional stability loss completely meets the requirement of atomic clock frequency correction, and the conventional method has the influence of factors such as frequency doubling, the stability of the input frequency stability index is obviously reduced under the condition of frequency correction, some indexes even reach more than one order of magnitude of reduction, when the frequency of the external reference frequency signal is 10MHz, the links such as frequency doubling and the like are avoided, the influence of the corrected frequency is hardly caused, and the output frequency stability indexes are higher.
(4) The phase noise of the output signal of the system is mainly determined by the phase noise of the constant temperature crystal oscillator, the phase noise index can reach-110 dBc/Hz at the position of 1Hz, and can reach-165 dBc/Hz at the position of 100KHz, the phase noise is far better than the phase noise which can be reached by the output signal of the DDS, and meanwhile, the phase noise of the output signal of the atomic clock can be improved.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (9)
1. A method of high performance frequency correction, the method comprising:
acquiring an external reference frequency signal and a frequency correction quantity; the external reference frequency signal is the frequency of an atomic clock;
obtaining a first mixing signal and a second mixing signal by adopting a double DDS + double mixing filtering mode according to the external reference frequency signal, the constant temperature crystal oscillator output signal and the frequency correction quantity; the first mixing signal is a sine wave signal with a preset frequency, and the second mixing signal is a sine wave signal with a corrected frequency;
inputting the first mixing signal and the second mixing signal into a phase frequency detector, and filtering an output signal of the phase frequency detector by using a loop filter to obtain a voltage control signal;
the voltage control end of the constant temperature crystal oscillator is controlled by the voltage control signal until the output signal of the constant temperature crystal oscillator is stabilized at a preset value;
wherein: according to the external reference frequency signal, the constant temperature crystal oscillator output signal and the frequency correction quantity, a first mixing signal and a second mixing signal are obtained in a double DDS + double mixing filtering mode, and the method comprises the following steps:
frequency division is carried out on the external reference frequency signal to obtain three paths of frequency division signals;
the first path of frequency division signal is used as the main frequency of a main control computer, and the second path of frequency division signal is used as a DDS clock of a double-path DDS module; the two-way DDS module comprises a first DDS module and a second DDS module;
processing the second path of frequency division signal by a first DDS module to obtain a first digital synthesis frequency;
performing frequency mixing processing on the first digital synthesis frequency and the third frequency division signal through a first frequency mixer, and performing narrow-band-pass filtering processing on the signal after the frequency mixing processing to obtain a first frequency mixing signal;
converting the frequency correction quantity into a frequency control word through a main control machine, issuing the frequency control word to a second DDS module, and processing a second path of frequency division signal through the second DDS module to obtain a second digital synthesis frequency;
and carrying out frequency mixing processing on the second digital synthesis frequency and the constant-temperature crystal oscillator output signal through a second frequency mixer, and carrying out narrow-band-pass filtering processing on the signal after frequency mixing processing to obtain a second frequency mixing signal.
2. The method of claim 1, wherein the frequency-dividing the external reference frequency signal to obtain three frequency-divided signals, comprises:
and detecting the external reference frequency signal to obtain an external reference frequency value.
3. The method of claim 2, frequency-dividing the outer reference frequency signal to obtain three frequency-divided signals, comprising:
when the external reference frequency value is 5MHz, carrying out frequency doubling processing on the external reference frequency signal to obtain a frequency-doubled external reference frequency signal; and frequency division is carried out on the frequency-multiplied external reference frequency signal to obtain three paths of frequency division signals.
4. The method of claim 2, wherein mixing the second digital synthesis frequency with the constant temperature crystal oscillator output signal by a second mixer, and performing narrowband bandpass filtering on the mixed signal to obtain a second mixed signal, comprises:
when the external reference frequency value is 5MHz, the output end of the constant temperature crystal oscillator is subjected to frequency division by two and then output, and a constant temperature crystal oscillator output signal subjected to frequency division by two is obtained; and performing frequency mixing processing on the second digital synthesis frequency and the constant-temperature crystal oscillator output signal subjected to the frequency division by two through a second frequency mixer, and performing narrow-band-pass filtering processing on the signal subjected to the frequency mixing processing to obtain a second frequency mixing signal.
5. A high-performance frequency correction system is characterized by comprising a frequency divider, a main control computer, a double-circuit DDS module, two frequency mixing filtering branches, a phase frequency detector, a loop filter and a constant temperature crystal oscillator; the two-way DDS module comprises a first DDS module and a second DDS module;
the frequency divider is used for receiving the external reference frequency signal, performing frequency division processing on the external reference frequency signal to obtain three paths of frequency division signals, taking the first path of frequency division signal as a main frequency signal of the main control computer, inputting the second path of frequency division signal to the first input end of the first frequency mixing filtering branch, and taking the third path of frequency division signal as a DDS clock of the two-path DDS module;
the main control computer is used for converting the frequency correction quantity into a frequency control word and sending the frequency control word to the second DDS module;
the first DDS module is used for carrying out frequency synthesis on a DDS clock to obtain a first synthesis frequency signal; the output end of the first DDS module is connected with the second input end of the first frequency mixing filtering branch circuit;
the second DDS module is configured to perform frequency synthesis according to the frequency control word and the DDS clock to obtain a second synthesized frequency signal, and an output end of the second DDS module is connected to a second input end of the second mixing filter branch;
the first frequency mixing and filtering branch is used for carrying out frequency mixing and filtering processing on the received second path of frequency division signals and the first synthesized frequency signals and outputting first frequency mixing signals to a first input end of the phase frequency detector;
the second frequency mixing and filtering branch is used for carrying out frequency mixing and filtering processing on a second path of frequency division signals input by the first input end and constant temperature crystal oscillator output signals input by the second input end and outputting second frequency mixing signals to the second input end of the phase frequency detector;
the output end of the phase frequency detector is connected with the input end of the loop filter, the output end of the loop filter is connected with the voltage control end of the constant temperature crystal oscillator, the output end of the constant temperature crystal oscillator is used as the system output end, and when the system is stable, a frequency signal with corrected frequency is output.
6. The system of claim 5, further comprising a frequency measurement module, a determination module, a switching module, and a frequency doubling module;
the input end of the frequency measurement module is used for receiving an external reference frequency signal, the output end of the frequency measurement module is connected with the input end of the judgment module, the output end of the judgment module is connected with the control end of the switching module, the input end of the switching module receives the external reference frequency signal, the first output end of the switching module is connected with the input end of the frequency doubling module, the second output end of the judgment module is connected with the input end of the frequency division module, and the output end of the frequency doubling module is connected with the input end of the frequency division module.
7. The system of claim 5, further comprising a frequency measurement module, a determination module, a switching module, and a divide-by-two module;
the input end of the frequency measurement module is used for receiving an external reference frequency signal, the output end of the frequency measurement module is connected with the input end of the judgment module, the output end of the judgment module is connected with the control end of the switching module, the input end of the switching module is connected with the output end of the constant-temperature crystal oscillator, the first output end of the switching module is connected with the input end of the frequency-halving module, the second output end of the judgment module is connected with the input end of the second frequency-mixing filtering branch, and the output end of the frequency-halving module is connected with the input end of the second frequency-mixing filtering branch.
8. The system according to any of claims 5-6, wherein the frequency of the external reference frequency signal is 10MHz or 5 MHz; the output frequency of the constant-temperature crystal oscillator is 10 MHz.
9. An improved phase-locked loop comprises a phase frequency detector, a loop filter, a constant temperature crystal oscillator and a feedback loop, wherein the feedback loop comprises a frequency division module; the frequency mixing and filtering module comprises a frequency mixer and a filtering module;
the improved phase-locked loop further comprises an external reference frequency processing module, wherein an input end of the external reference frequency processing module acquires an external reference frequency signal and a frequency correction quantity, the external reference frequency processing module is used for carrying out frequency synthesis and frequency mixing filtering processing on the external reference frequency signal by adopting a two-way DDS + frequency mixing filtering mode according to the external reference frequency signal and the frequency correction quantity to obtain a first homologous external reference and a second homologous external reference, and the first homologous external reference is a frequency signal with a determined frequency value; the second homologous external reference is a frequency signal containing frequency correction information;
the first input end of the frequency mixer is connected with the output end of the constant-temperature crystal oscillator, the second input end of the frequency mixer is connected with the second output end of the external reference frequency processing module, the output end of the frequency mixer is connected with the input end of the filtering module, and the output end of the filtering module is connected with the second input end of the phase frequency detector; the first input end of the phase frequency detector is connected with the first output end of the external reference frequency processing module, the output end of the phase frequency detector is connected with the input end of the loop filter, and the output end of the loop filter is connected with the voltage control module of the constant temperature crystal oscillator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111141544.6A CN113839670B (en) | 2021-09-28 | 2021-09-28 | High-performance frequency correction method, frequency correction system and improved phase-locked loop |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111141544.6A CN113839670B (en) | 2021-09-28 | 2021-09-28 | High-performance frequency correction method, frequency correction system and improved phase-locked loop |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113839670A CN113839670A (en) | 2021-12-24 |
| CN113839670B true CN113839670B (en) | 2022-05-13 |
Family
ID=78970917
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111141544.6A Active CN113839670B (en) | 2021-09-28 | 2021-09-28 | High-performance frequency correction method, frequency correction system and improved phase-locked loop |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113839670B (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7545224B2 (en) * | 2007-04-12 | 2009-06-09 | Teradyne, Inc. | Cost effective low noise single loop synthesizer |
| WO2015074133A1 (en) * | 2013-11-25 | 2015-05-28 | Nanowave Technologies Inc. | Digitally compensated phase locked oscillator |
| CN103957006B (en) * | 2014-04-15 | 2017-05-03 | 西安天伟电子***工程有限公司 | S wave band low-phase noise frequency comprehensive generator |
| CN105978562B (en) * | 2016-05-12 | 2019-02-05 | 中国电子科技集团公司第四十一研究所 | Super Low phase noise and the high-frequency narrow-band of ultra-high frequency resolution ratio synthesis source circuit and method |
| CN108736889B (en) * | 2018-04-24 | 2022-04-01 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Low spurious/low phase noise frequency synthesizer |
-
2021
- 2021-09-28 CN CN202111141544.6A patent/CN113839670B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN113839670A (en) | 2021-12-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7250823B2 (en) | Direct digital synthesis (DDS) phase locked loop (PLL) frequency synthesizer and associated methods | |
| US7432751B2 (en) | High performance signal generation | |
| CN106385255B (en) | A kind of polycyclic apparatus for frequency synthesizing that low noise high-resolution is tunable and method | |
| US4198604A (en) | Heterodyne phase lock system | |
| CN108736889A (en) | Low spurious Low phase noise frequency synthesizer | |
| CN105187060B (en) | The phase-locked loop circuit and its implementation of a kind of low phase noise | |
| CN104135280B (en) | Harmonic generation and mixing frequency source circuit | |
| US20090274255A1 (en) | Method and apparatus for stabilizing clock | |
| TW201318349A (en) | Clock data recovery circuit | |
| CN105978562B (en) | Super Low phase noise and the high-frequency narrow-band of ultra-high frequency resolution ratio synthesis source circuit and method | |
| CN105429641A (en) | Lock protection type high-performance broadband microwave frequency synthesizer | |
| JP2022522305A (en) | Circuits and methods for identifying the ratio between two frequencies | |
| US8682273B2 (en) | RF digital spur reduction | |
| CN113794473B (en) | Generalized frequency synthesizer and synthesis method | |
| CN113839670B (en) | High-performance frequency correction method, frequency correction system and improved phase-locked loop | |
| EP0708522A1 (en) | Phase modulator capable of individually defining modulation degree and modulation frequency | |
| CN105356878B (en) | A kind of implementation method and device of improved tricyclic wideband frequency synthesizer | |
| CN112234985B (en) | Frequency phase fine tuning system | |
| RU195894U1 (en) | Frequency synthesizer | |
| CN103501174A (en) | Low-noise reference signal generator and signal generation method | |
| CN106899293A (en) | Frequency synthesizer | |
| CN102420606B (en) | Low phase-noise and small step-frequency synthesized realizing method | |
| CN108092663B (en) | Frequency generating device and frequency generating method | |
| RU185004U1 (en) | High Frequency Purity Hybrid Frequency Synthesizer | |
| CN217546022U (en) | Voltage presetting device for digital phase-locked loop, frequency synthesizer and electronic communication device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |