CN105978562B - Super Low phase noise and the high-frequency narrow-band of ultra-high frequency resolution ratio synthesis source circuit and method - Google Patents
Super Low phase noise and the high-frequency narrow-band of ultra-high frequency resolution ratio synthesis source circuit and method Download PDFInfo
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
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Abstract
The invention discloses a kind of super Low phase noises and the high-frequency narrow-band of ultra-high frequency resolution ratio synthesis source circuit and method, comprising: phase-locked loop reference signal generation circuit and N2Secondary integral multiple point frequency generation circuit is connect with mixing feedback phase demodulation loop respectively；Phase-locked loop reference signal generation circuit is used to generate the phase-locked loop reference signal of high frequency resolution, N2Secondary integral multiple point frequency generation circuit is used to generate the N of reference signal2Secondary integral multiple point-frequency signal；The phase error that phase discriminator generates is converted to voltage signal and adjusts voltage controlled oscillator until loop-locking.The invention has the advantages that: high-frequency narrow-band synthetic source of the invention, any synthetic source within available frequency >=1GHz, bandwidth 100MHz, and frequency resolution reaches 0.1mHz, can obtain ultralow index of mutually making an uproar, take into account remote near-end noise.
Description
Technical field
The present invention relates to high-frequency narrow-band synthetic source design field more particularly to a kind of super Low phase noises and ultra-high frequency point
The high-frequency narrow-band synthesis source circuit and method of resolution.
Background technique
In various high-frequency narrow-band synthetic sources design at this stage, to the bandwidth of synthetic source, frequency range type requirements are more and more,
Higher want is proposed to the phase noise of high-frequency narrow-band synthetic source, frequency resolution, spuious, harmonic wave, volume and cost simultaneously
It asks.
It is main to be obtained by two schemes in current high-frequency narrow-band synthetic source design:
The first scheme is to select the benchmark frequency point (usually 100MHz) of high target, and frequency-doubled signal and DDS are directly counted
The signal that word synthetic technology obtains is obtained by way of mixing.DDS Direct Digital output frequency relative bandwidth compared with
Width, theory are the 50% of input frequency, and reality output remains to reach 40%, while frequency switching time is short, frequency resolution pole
Height can be easily met bandwidth within 100MHz, the narrowband synthetic source design requirement of 0.1mHz resolution ratio.But due to DDS
Using digital structure, inevitably introduce it is spuious, wherein there are three main sources: phase accumulator phase truncation error
Caused by it is spuious caused by spuious and DAC non-ideal characteristic caused by spuious, amplitude quantization error, and when output frequency band is wider than
When wide, can not also it be filtered out using filter, it can severe exacerbation output signal；The signal obtained by the way of frequency multiplication, it is far and near
It mutually makes an uproar and can deteriorate in end；Therefore, this method is difficult to obtain good spectrum signal performance.Meanwhile frequency is higher and bandwidth is wider,
Broadband filter cost for DDS filtering is higher, will increase circuit cost.
Second scheme is the benchmark frequency point (usually 100MHz) and a narrowband VCO for selecting high target, passes through monocycle
The mode of locking phase obtains.Phase-locked loop circuit is mainly by phase discriminator (PD), loop filter (LPF), voltage controlled oscillator (VCO) and meter
Modulus frequency divider (N) composition.First by the output signal of VCO by counting frequency dividing in circuit design, it is input to phase discriminator.Phase discriminator
In input reference signal, phase discriminator export the error signal directly proportional to two kinds of signal phase differences simultaneously.The phase that LPF exports PD
Bit error signal is converted to voltage signal, and send to the input terminal of VCO the output frequency for adjusting VCO, when the letter of frequency-dividing counter
When number identical as reference signal, loop-locking.The synthetic source that this method obtains, output frequency proximal end (in loop bandwidth) phase
Position noise is determined that distal end (outside loop bandwidth) phase noise is determined by VCO itself by reference, deteriorates formula according to phase noise,
It is mutually made an uproar with the worsening of relations of 20lgN, therefore, for high band synthetic source, is difficult to obtain in this way and preferably mutually make an uproar
Index, while it being limited to the minimum frequency dividing ratio of frequency-dividing counter N, under high-frequency signal, it is extremely difficult to higher frequency resolution.
In conclusion the prior art mainly has the deficiency of following three aspect:
First: the scheme for adding DDS Direct Digital to be mixed using integer frequency, stray indexes mistake
Height seriously affects the performance of high frequency output signal spectrum.
Second: using monocycle locking phase scheme, the ultra-high frequency resolution ratio of 0.1mHz can not be obtained.
Third: two schemes can not obtain proximal end (in loop bandwidth) good phase noise specifications.
Summary of the invention
The present invention to solve the above-mentioned problems, proposes the high-frequency narrow-band conjunction of a kind of super Low phase noise and ultra-high frequency resolution ratio
At source circuit and method, output frequency >=1GHz, bandwidth≤100MHz can be obtained, frequency resolution can be accurate to 0.1mHz's
High-frequency narrow-band synthetic source, when output frequency is 3GHz, phase noise specifications reach -128dBc@10kHz.
To achieve the above object, the present invention adopts the following technical solutions:
A kind of high-frequency narrow-band synthesis source circuit of super Low phase noise and ultra-high frequency resolution ratio, comprising: phase-locked loop is with reference to letter
Number generation circuit and N2Secondary integral multiple point frequency generation circuit is connect with mixing feedback phase demodulation loop respectively；
The phase-locked loop reference signal generation circuit is used to generate the phase-locked loop reference signal of high frequency resolution, institute
State N2Secondary integral multiple point frequency generation circuit is used to generate the N of reference signal2Secondary integral multiple point-frequency signal；
The mixing feedback phase demodulation loop includes voltage controlled oscillator, the N of reference signal2Secondary integral multiple point-frequency signal with it is described
The feedback signal of phase-locked loop, the feedback signal and process of the phase-locked loop are obtained after the feedback signal mixing of voltage controlled oscillator
N3Phase-locked loop reference signal after integral frequency divisioil carries out phase demodulation, and the phase error of generation is converted to voltage signal and adjusts voltage-controlled vibration
Device is swung until loop-locking.
Further, the phase-locked loop reference signal generation circuit includes:
First power splitter, the second power splitter, quadrupler, DDS, the first amplifilter, the second amplifilter, N1Times
Frequency device and the first frequency mixer；The output end of first power splitter is separately connected the input terminal and N of the second power splitter2Secondary integral multiple
Point frequency generation circuit, the output end of second power splitter respectively with quadrupler and N1Frequency multiplier connection, the quadrupler
After being sequentially connected in series DDS and the first amplifilter, it is connect with an input terminal of the first frequency mixer；The N1Frequency multiplier series connection the
After two amplifilters, it is connect with another input terminal of the first frequency mixer；
Further, the second power splitter of the phase-locked loop reference signal generation circuit is by the first power splitter output end
Reference signal is divided into two-way, wherein reference signal is carried out digital frequency division after quadruple all the way generates signal FDDS, in addition one
N is passed through on road1Signal F is obtained after secondary integer frequencyN, the signal FDDSWith signal FNIt carries out mixing and obtains phase-locked loop reference signal
FR；
Further, the N2Secondary integral multiple point frequency generation circuit obtains required N using multiple integer frequency mode2
Secondary integral multiple point-frequency signal.
Further, the N2Secondary integral multiple point frequency generation circuit obtains required N by the way of being repeatedly mixed2It is secondary
Integral multiple point-frequency signal.
Further, the N2Secondary integral multiple point frequency generation circuit uses multiple integer frequency mode and multiple mixing schemes
The mode combined obtains required N2Secondary integral multiple point-frequency signal.
Further, the mixing feedback phase demodulation loop includes:
Frequency-dividing counter, phase discriminator, loop filter, oscillator, third power splitter, third amplifilter, the 4th are put
Big filter, the second frequency mixer and the 5th amplifilter；
The input terminal of the phase discriminator is connect with frequency-dividing counter and the 5th amplifilter respectively, and the phase discriminator is successively
It is divided into two-way after serial loop filter, oscillator and power splitter, wherein exporting finally by third amplifilter all the way
High-frequency narrow-band synthesizes source signal；In addition it is sequentially connected in series the 4th amplifilter, the second frequency mixer and the 5th amplifilter all the way；
Another input terminal and N of second frequency mixer2The output end of secondary integral multiple point frequency generation circuit connects, and described count is divided
The input terminal of frequency device is connect with the output end of phase-locked loop reference signal generation circuit.
A kind of implementation method of super Low phase noise and the high-frequency narrow-band of ultra-high frequency resolution ratio synthesis source circuit, comprising:
Reference signal is divided into two-way, wherein all the way for generating phase-locked loop reference signal, in addition all the way for generating ginseng
Examine the N of signal2Secondary integral multiple point-frequency signal；
The N of reference signal2Secondary integral multiple point-frequency signal generates locking phase with the feedback signal of voltage controlled oscillator after being mixed
The feedback signal of loop, the feedback signal of the phase-locked loop carry out phase demodulation with the phase-locked loop reference signal after frequency dividing,
The phase error of generation is converted to voltage signal and adjusts the output of voltage controlled oscillator until loop-locking.
The beneficial effects of the present invention are:
(1) high-frequency narrow-band synthetic source of the invention, any synthesis within available frequency >=1GHz, bandwidth 100MHz
Source, and frequency resolution reaches 0.1mHz, can obtain ultralow index of mutually making an uproar, take into account remote near-end noise.
(2) present invention has greatly saved circuit cost, simultaneously on the basis of obtaining high quality narrowband synthetic source
The versatility of scheme is high.
Detailed description of the invention
Fig. 1 is electrical block diagram of the present invention；
Wherein, 1. first power splitter, 2. second power splitters, 3.N1Frequency multiplier, 4. first filtering and amplifying circuits, 5. quadruples
Device, 6.DDS Digital synthesis circuit, 7. second filtering and amplifying circuits, 8. first frequency mixers, 9. frequency-dividing counters, 10.N2Secondary integer
Point frequency generation circuit, 11. phase discriminators, 12. loop filters, 13. voltage controlled oscillators, 14. third power splitters, 15. thirds are put again
Big filter circuit, 16. the 4th filtering and amplifying circuits, 17. second frequency mixers, 18. the 5th filtering and amplifying circuits.
Specific embodiment
The invention will be further described with embodiment with reference to the accompanying drawing.
A kind of high-frequency narrow-band synthesis source circuit of super Low phase noise and ultra-high frequency resolution ratio, as shown in Figure 1, comprising: locking phase
Loop reference signal generation circuit, N2Secondary integral multiple point frequency generation circuit 10, mixing feedback phase demodulation loop；
Phase-locked loop reference signal generation circuit and N2Secondary integral multiple point frequency generation circuit 10 respectively be mixed feedback phase demodulation
Loop connection；
Phase-locked loop reference signal generation circuit is used to generate the phase-locked loop reference signal of high frequency resolution, N2It is secondary whole
Several times point frequency generation circuit 10 is used to generate the N of 100MHz reference signal2Secondary integral multiple point-frequency signal；
Mixing feedback phase demodulation loop includes voltage controlled oscillator 13, the N of reference signal2Secondary integral multiple point-frequency signal and voltage-controlled vibration
Swing device 13 feedback signal mixing after obtain phase-locked loop feedback signal, the feedback signal of phase-locked loop with pass through N3Integer point
Phase-locked loop reference signal after frequency carries out phase demodulation, and the phase error of generation is converted to voltage signal and adjusts voltage controlled oscillator 13 directly
To loop-locking.
Phase-locked loop reference signal generation circuit includes: power splitter, quadrupler 5, DDS (Direct
DigitalSynthesizer, Direct Digital Synthesizer) Digital synthesis circuit, the first amplifilter, the second amplification
Filter, N1Frequency multiplier 3 and the first frequency mixer 8；The output end of power splitter respectively with quadrupler 5 and N1Frequency multiplier 3 connects, and four
After frequency multiplier 5 is sequentially connected in series DDS Digital synthesis circuit 6 and the first amplifilter, connect with an input terminal of the first frequency mixer 8
It connects；N1Frequency multiplier 3 is connected after the second amplifilter, is connect with another input terminal of the first frequency mixer 8.
Reference signal is divided into two-way by phase-locked loop reference signal generation circuit, wherein reference signal is passed through four times all the way
Digital frequency division is carried out after frequency generates signal FDDS, in addition pass through N all the way1Signal F is obtained after secondary integer frequencyN, signal FDDSAnd signal
FNIt carries out mixing and obtains phase-locked loop reference signal FR。
N2Secondary integral multiple point frequency generation circuit 10 can mainly be obtained by three kinds of modes:
One, the mode of direct frequency doubling, passes through NX、NY、NZAfter multiple integer frequency, the point-frequency signal F of needs is generatedM, it is proposed that
Frequency multiplication number controls within 5 grades.
Two, by being repeatedly mixed the point-frequency signal F for obtaining and needingM。
Three, using common monocycle locking phase scheme, Direct frequency synthesizer.
But because final output signal FOThe phase noise of proximal end is mainly by signal FMIt determines, three phaselocked loop of employing mode
If, FMBecause the digital noise in phaselocked loop leads to FMIt will not obtain ultralow in-band phase noise index.And use one times of scheme
Frequency mode, signal phase noise objective can be according to 20lgN2Deteriorated；And mixing schemes are the power spectrums of two input signals
The sum of degree, in contrast two mixing scheme of employing mode can obtain best phase noise specifications.In conclusion " 100MHz
N2Secondary integral multiple point frequency generation circuit 10 " is in actual use, preferential to select two mixing schemes of scheme, secondly it is contemplated that side
One frequency multiplication mode of case, because selecting mode three that can't obtain index in good band, this programme is forbidden to use mode three.
And in actual circuit application, the F that the mode that mixing and frequency multiplication combine is needed is usually takenMSignal.
Mixing feedback phase demodulation loop include: frequency-dividing counter 9, phase discriminator 11, loop filter 12, oscillator, power splitter,
Third amplifilter 15, the 4th amplifilter 16, the second frequency mixer 17 and the 5th amplifilter 18；
The input terminal of phase discriminator 11 is connect with frequency-dividing counter 9 and the 5th amplifilter 18 respectively, and phase discriminator 11 is successively
It is divided into two-way after serial loop filter 12, oscillator and power splitter, wherein all the way most by the output of third amplifilter 15
Whole high-frequency narrow-band synthesizes source signal；In addition it is sequentially connected in series the 4th amplifilter 16 all the way, the second frequency mixer 17 and the 5th is put
Big filter 18；Another input terminal and N of second frequency mixer 172The output end of secondary integral multiple point frequency generation circuit 10 connects
It connects, the input terminal of frequency-dividing counter 9 is connect with the output end of phase-locked loop reference signal generation circuit.
It is that 100MHz passes through two function on the basis of the benchmark frequency point 100MHz of high target that the present invention, which chooses reference signal,
Divide device that reference signal is divided into three tunnels, the first via send Digital synthesis circuit to carry out digital frequency division after quadruple and generates FDDS, the
Two tunnel reference signals pass through N1After secondary integer frequency with FDDSMixing obtains FR.Third road reference signal passes through the " N of 100MHz2It is secondary
Integral multiple point frequency generation circuit 10 " generates FMIt is mixed with the feedback signal of VCO (voltage controlled oscillator 13) and obtains the anti-of phase-locked loop
Feedback signal FB, reference signal FRBy N3After integral frequency divisioil, it is sent to phase discriminator 11 and feedback signal FBThe phase of phase demodulation, generation is missed
Difference is converted to voltage signal by loop filter 12 and adjusts VCO until loop-locking.The program is by introducing DDS digit synthesis
Circuit 6 makes output signal resolution ratio up to 0.1mHz, by the control of 6 output signal bandwidth of DDS Digital synthesis circuit within 25MHz,
By adding multiple filter, can be very good to filter out the spuious of output signal proximal end.By using " the N of 100MHz2Secondary integer
The method that point frequency generation circuit 10 " is mixed with the feedback signal of VCO again, such FONear-end noise is mainly by mixed frequency signal FM
Determine, eliminate the deterioration of mutually making an uproar of 20lgN in monocycle locking phase loop bandwidth, obtain it is extremely low make an uproar index with interior phase, adopt simultaneously
The spurious signal (spurious signal generated including DDS Digital synthesis circuit 6) that distal end (band is outer) is filtered out with phaselocked loop scheme, obtains
The outer spectral purity of good band.
The specific working principle is as follows for circuit of the present invention:
After reference frequency 100MHz signal first passes around the first power splitter 1 and the second power splitter 2, three tunnels are generated with reference to letter
Number, first via 100MHz signal generates 400MHz signal by quadrupler 5, by 6 Direct Digital of DDS Digital synthesis circuit point
After frequency, 110MHz or so, the signal F of 25MHz bandwidth are generatedDDS, its band stray letter is filtered out by the second filtering and amplifying circuit 7
Number.Second road 100MHz signal passes through N1After secondary integer frequency, the first filtering and amplifying circuit 4, with FDDSSignal mixing, obtains FR,
FRFrequency resolution reaches 0.1mHz, carries out N by frequency-dividing counter 93After integral frequency divisioil, it is sent to phase discriminator 11 and feedback signal FB
Phase demodulation；Third road 100MHz signal is sent to the " N of 100MHz2Secondary integral multiple point frequency generation circuit 10 " generates N2The letter of × 100MHz
Number FM, it is mixed with the feedback signal of VCO, generates the feedback signal F of phase-locked loopB, feedback signal FB≤ 100MHz, is sent to
Phase discriminator 11 participates in phase demodulation；The phase error that phase discriminator 11 generates is converted to tuning voltage by loop filter 12 and adjusts VCO,
The output signal of final VCO obtains final high-frequency narrow-band synthesis source signal by third amplifilter 15.After loop-locking,
Output signal meets formula (1).
In addition, 100MHz reference signal is after quadruple, DDS digital frequency division, the F of generationDDSSignal near-end noise can obtain
To certain deterioration, and the loop reference signal F obtained by frequency mixerRBy N3Loop phase demodulation is directly participated in after integral frequency divisioil,
Therefore F must be ensuredRPhase noise specifications by 100MHz N1Secondary frequency-doubled signal determines, just can guarantee by N in this way3Integer
Relative to 100MHz reference signal after frequency dividing, mutually making an uproar for phase discrimination signal will not generate obvious deterioration.That is N1Specific value should expire
Sufficient formula (2).
N100MHz+20lgN1≤NDDS (2)
In formula (2), N100MHzFor the phase noise of benchmark signal 100MHz, NDDSFor the proximal end phase noise of DDS,
It can be obtained by DDS databook in actual use.
(1) present invention, which is mixed, feeds back phase demodulation loop, within bandwidth 100MHz, frequency resolution 0.1mHz.The loop passes through
The N of 100MHz1Secondary frequency multiplication is mixed with DDS signal, and the signal of generation passes through N3Reference signal is used as after integral frequency divisioil, VCO's
The N of feedback signal and 100MHz2Secondary integral multiple signal is mixed to obtain loop feedback signal, passes through phase demodulation, loop filtering, electricity
Pressure tuning, the final high-frequency narrow-band synthetic source for obtaining Low phase noise and ultra-high frequency resolution ratio.
(2) N of 100MHz of the present invention2Secondary integral multiple point frequency generation circuit 10, by two different schemes, according to reality
The difference of situation selects simplest scheme, final to obtain the signal F neededMIt is mixed, is eliminated with the feedback signal of VCO
It mutually makes an uproar deterioration in phaselocked loop internal cause frequency dividing bring band, realizes and ultralow make an uproar index with interior phase.
(3) phase-locked loop reference signal F of the present inventionRGeneration circuit passes through analysis DDS and reference signal N1Secondary frequency-doubled signal
Proximal end phase noise specifications, ensure final output signal FOIn-band phase noise index will not be brought because introducing DDS
Deteriorate.The output signal F so that final is mixed by introducing DDSOObtain the ultra-high frequency resolution ratio of 0.1mHz.
Above-mentioned, although the foregoing specific embodiments of the present invention is described with reference to the accompanying drawings, not protects model to the present invention
The limitation enclosed, those skilled in the art should understand that, based on the technical solutions of the present invention, those skilled in the art are not
Need to make the creative labor the various modifications or changes that can be made still within protection scope of the present invention.
Claims (3)
1. a kind of super Low phase noise and the high-frequency narrow-band of ultra-high frequency resolution ratio synthesize source circuit, characterized in that include: phase-locked loop
Reference signal generation circuit and N2Secondary integral multiple point frequency generation circuit is connect with mixing feedback phase demodulation loop respectively；
The phase-locked loop reference signal generation circuit is used to generate the phase-locked loop reference signal of high frequency resolution, the N2
Secondary integral multiple point frequency generation circuit is used to generate the N of reference signal2Secondary integral multiple point-frequency signal；
The mixing feedback phase demodulation loop includes voltage controlled oscillator, the N of reference signal2Secondary integral multiple point-frequency signal with it is described voltage-controlled
Oscillator feedback signal mixing after obtain phase-locked loop feedback signal, the feedback signal of the phase-locked loop with pass through N3It is whole
Phase-locked loop reference signal after number frequency dividing carries out phase demodulation, and the phase error of generation is converted to voltage signal and adjusts voltage controlled oscillator
Until loop-locking；
The phase-locked loop reference signal generation circuit includes:
First power splitter, the second power splitter, quadrupler, DDS, the first amplifilter, the second amplifilter, N1Frequency multiplier
With the first frequency mixer；The output end of first power splitter is separately connected the input terminal and N of the second power splitter2Secondary integral multiple point frequency
Generation circuit, the output end of second power splitter respectively with quadrupler and N1Frequency multiplier connection, the quadrupler is successively
It connects after DDS and the first amplifilter, is connect with an input terminal of the first frequency mixer；The N1Frequency multiplier series connection second is put
After big filter, it is connect with another input terminal of the first frequency mixer；
The reference signal of first power splitter output end is divided by the second power splitter of the phase-locked loop reference signal generation circuit
Two-way, wherein reference signal is carried out digital frequency division after quadruple all the way generates signal FDDS, in addition pass through N all the way1It is secondary whole
Signal F is obtained after several times frequencyN, the signal FDDSWith signal FNIt carries out mixing and obtains phase-locked loop reference signal FR；
The N2Secondary integral multiple point frequency generation circuit is using multiple mixing schemes or multiple integer frequency mode and multiple mixing side
The mode that formula combines obtains required N2Secondary integral multiple point-frequency signal:
N100MHz+20lgN1≤NDDS(2), in formula (2), N100MHzFor the phase noise of benchmark signal 100MHz, NDDSFor DDS
Proximal end phase noise；
After loop-locking, output signal meets formula
2. a kind of super Low phase noise as described in claim 1 and the high-frequency narrow-band of ultra-high frequency resolution ratio synthesize source circuit, special
Sign is that the mixing feedback phase demodulation loop includes:
Frequency-dividing counter, phase discriminator, loop filter, oscillator, third power splitter, third amplifilter, the 4th amplification filter
Wave device, the second frequency mixer and the 5th amplifilter；
The input terminal of the phase discriminator is connect with frequency-dividing counter and the 5th amplifilter respectively, and the phase discriminator is sequentially connected in series
It is divided into two-way after loop filter, oscillator and power splitter, wherein exporting final high frequency by third amplifilter all the way
Narrowband synthesizes source signal；In addition it is sequentially connected in series the 4th amplifilter, the second frequency mixer and the 5th amplifilter all the way；It is described
Another input terminal and N of second frequency mixer2The output end of secondary integral multiple point frequency generation circuit connects, the frequency-dividing counter
Input terminal connect with the output end of phase-locked loop reference signal generation circuit.
3. a kind of realization of the high-frequency narrow-band synthesis source circuit of super Low phase noise as described in claim 1 and ultra-high frequency resolution ratio
Method, characterized in that include:
Reference signal is divided into two-way, wherein all the way for generating phase-locked loop reference signal, in addition all the way for generating benchmark letter
Number N2Secondary integral multiple point-frequency signal；
The N of reference signal2Secondary integral multiple point-frequency signal generates phase-locked loop with the feedback signal of voltage controlled oscillator after being mixed
Feedback signal, the feedback signal of the phase-locked loop carry out phase demodulation with the phase-locked loop reference signal after frequency dividing, generation
Phase error is converted to voltage signal and adjusts the output of voltage controlled oscillator until loop-locking.
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| CN106533439B (en) * | 2017-01-09 | 2023-06-06 | 成都西蒙电子技术有限公司 | Low phase noise frequency synthesizer |
| CN107196653B (en) * | 2017-04-18 | 2020-04-21 | 中国电子科技集团公司第四十一研究所 | Broadband low-phase noise frequency synthesizer |
| CN109120259A (en) * | 2018-08-06 | 2019-01-01 | 西安众思创融电子科技有限公司 | A kind of ultra-fine stepping low phase noise superelevation spurious reduction frequency source of small size |
| CN113422604B (en) * | 2021-08-24 | 2021-11-16 | 深圳市鼎阳科技股份有限公司 | Frequency synthesizer |
| CN113839670B (en) * | 2021-09-28 | 2022-05-13 | 星汉时空科技(长沙)有限公司 | High-performance frequency correction method, frequency correction system and improved phase-locked loop |
| CN115395950B (en) * | 2022-08-01 | 2023-08-15 | 北京华力睿源电子有限公司 | Frequency synthesizer |
| CN117459061B (en) * | 2023-12-25 | 2024-04-09 | 成都威频通讯技术有限公司 | Signal synthesizer |
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|---|---|---|---|---|
| US7250823B2 (en) * | 2005-05-25 | 2007-07-31 | Harris Corporation | Direct digital synthesis (DDS) phase locked loop (PLL) frequency synthesizer and associated methods |
| CN101064510B (en) * | 2007-04-19 | 2010-07-21 | 电子科技大学 | Low phase spurious frequency synthesis method |
| CN104393871A (en) * | 2014-12-02 | 2015-03-04 | 贵州航天计量测试技术研究所 | Frequency synthesizer for driving phase-locked loop after up-converting DDS |
| CN105577184A (en) * | 2015-12-17 | 2016-05-11 | 中国电子科技集团公司第四十一研究所 | Frequency synthesis device for LTE-Advanced signal analyzer |
| CN105553475B (en) * | 2015-12-18 | 2018-11-20 | 中国电子科技集团公司第四十一研究所 | High frequency points frequency source combiner circuit based on digital frequency division and harmonic mixing |
-
2016
- 2016-05-12 CN CN201610319585.2A patent/CN105978562B/en not_active Expired - Fee Related
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