CN113835333A

CN113835333A - Time-to-digital conversion device and time-to-digital conversion method

Info

Publication number: CN113835333A
Application number: CN202111150506.7A
Authority: CN
Inventors: 孙雨薇; 柯毅; 董舒; 刘德珩
Original assignee: Wuhan Silicon Integrated Co Ltd
Current assignee: Wuhan Silicon Integrated Co Ltd
Priority date: 2021-09-29
Filing date: 2021-09-29
Publication date: 2021-12-24
Anticipated expiration: 2041-09-29
Also published as: CN113835333B

Abstract

The application discloses a time-to-digital conversion device and a time-to-digital conversion method, wherein the time-to-digital conversion device comprises a timing stop processing module, a synchronous module, a coarse timing module, a fine timing module and a calculation module, and the timing stop mark signal output by the timing stop processing module and the timing stop synchronous signal output by the synchronous module correspondingly control the coarse timing result of the coarse timing module and the fine timing result of the fine timing module, so that the metastable state influence caused by the asynchronous signal of the timing stop signal can be relieved or eliminated, and the accuracy of the time-to-digital conversion result is improved; even if the coarse timing result and the fine timing result are influenced by the metastable state in the time-to-digital conversion process, the metastable state influence on the timing result can be further reduced or eliminated through the subtraction operation of the coarse timing result and the fine timing result, and the accuracy of the time-to-digital conversion result is further improved.

Description

Time-to-digital conversion device and time-to-digital conversion method

Technical Field

The present invention relates to the field of time-to-digital conversion technologies, and in particular, to a time-to-digital conversion apparatus and a time-to-digital conversion method.

Background

A Time-to-Digital converter (TDC) is a measuring device based on high precision and short Time intervals, and is not only in the engineering fields of telecommunication communication, chip design, Digital oscilloscope and the like, but also in the theoretical research of atomic physics, astronomical observation and the like, and in the aerospace military technical fields of laser ranging, satellite positioning and the like, and relates to high precision Time interval measurement.

However, the time result of the time-to-digital converter in the conventional solution is easily affected by the metastable state of the timing stop signal, for example, as shown in fig. 1 and fig. 2, the Coarse count starts in response to the rising edge of the clock signal clk in the test signal and the rising edge of the timing start signal start-trig, and stops in response to the falling edge of the timing start signal start-trig in the test signal, so that the Coarse count result Coarse-cnt, i.e. an integer number of cycles of the clock signal clk, can be obtained; the fine counting starts in response to the falling edge of the timing start signal start-trig in the test signal, and stops in response to the rising edge of the timing stop signal stop-signal in the test signal, so that a fine counting result Delay-chain-cnt, i.e. a fraction of a period of the clock signal clk, can be obtained, and then a time result Rslt obtained after encoding and calculation is the sum of the Coarse counting result Coarse-cnt and the fine counting result Delay-chain-cnt.

The timing stop signal stop-signal is an asynchronous signal, and when the count is stopped in response to the rising edge of the timing stop signal stop-signal, the latch process in the time-to-digital converter is easy to generate a metastable state, so that the time result Rslt generates an error.

It should be noted that the above description of the background art is only for the convenience of clear and complete understanding of the technical solutions of the present application. The technical solutions referred to above are therefore not considered to be known to the person skilled in the art, merely because they appear in the background of the present application.

Disclosure of Invention

The application provides a time-to-digital conversion device and a time-to-digital conversion method, which are used for relieving or eliminating the problem that inaccurate or wrong counting is easy to occur in a time-to-digital conversion result.

In a first aspect, the present application provides a time-to-digital conversion apparatus, which includes a timing stop processing module, a synchronization module, a coarse timing module, a fine timing module, and a calculation module, where the timing stop processing module is configured to generate a timing stop flag signal according to a timing stop signal, a reset signal, and a timing stop synchronization signal, and a pulse start time of the timing stop flag signal is the same as a pulse start time of the timing stop signal; the synchronization module is electrically connected with the timing stop processing module and is used for generating a timing stop synchronization signal according to the clock signal, the reset signal and the timing stop mark signal; the coarse timing module is electrically connected with the synchronization module, starts coarse timing in response to the pulse starting time of the timing starting signal and one pulse starting time of the clock signal, stops coarse timing in response to the pulse starting time of the timing stopping synchronization signal and the other pulse starting time of the clock signal, and obtains a coarse timing result based on the clock number of the clock signal between the start of coarse timing and the stop of coarse timing; the fine timing module is electrically connected with the timing stop processing module and the synchronization module, starts fine timing in response to the pulse start time of the timing stop mark signal, stops fine timing in response to the pulse start time of the timing stop synchronization signal, and obtains a fine timing result based on the clock number of the clock signal between the start of fine timing and the stop of fine timing; the calculation module is electrically connected with the coarse timing module and the fine timing module and used for determining the timing result of the time-to-digital conversion device according to the clock signal, the difference value of the coarse timing result and the fine timing result.

In some embodiments, the timing stop processing module includes a first flip-flop and an or gate, an input terminal of the first flip-flop is connected to a high-potential signal, a trigger terminal of the first flip-flop is connected to a timing stop signal, and a non-inverting output terminal of the first flip-flop outputs a timing stop flag signal; one input end of the OR gate is connected with the timing stop synchronous signal, the other input end of the OR gate is connected with the reset signal, and the output end of the OR gate is electrically connected with the reset end of the first trigger.

In some embodiments, the synchronization module includes at least one flip-flop, the at least one flip-flop is sequentially connected in series, an input terminal of a first flip-flop of the at least one flip-flop is electrically connected to a non-inverting output terminal of the first flip-flop, a non-inverting output terminal of a last flip-flop of the at least one flip-flop is electrically connected to an input terminal of the or gate, the flip-flop terminals of the at least one flip-flop are all connected to the clock signal, and the reset terminals of the at least one flip-flop are all connected to the reset signal.

In some embodiments, the synchronization module includes a second flip-flop and a third flip-flop, an input terminal of the second flip-flop is electrically connected to a non-inverting output terminal of the first flip-flop, a trigger terminal of the second flip-flop is connected to the clock signal, and a reset terminal of the second flip-flop is connected to the reset signal; the input end of the third trigger is electrically connected with the positive phase output end of the second trigger, the trigger end of the third trigger is connected with the clock signal, the reset end of the third trigger is connected with the reset signal, and the in-phase output end of the third trigger is electrically connected with one input end of the OR gate.

In some embodiments, the fine timing module includes a delay chain unit, a fine timing latch unit and a coding unit, the delay chain unit is electrically connected to the output end of the timing stop processing module, and is used for multi-stage delay transmission of potential signals; the fine timing latch unit is electrically connected with the delay chain unit and the synchronization module and is used for latching the potential transmission state of the potential signal after multistage delay transmission according to the timing stop synchronization signal; the coding unit is electrically connected with the fine timing latch unit and the calculating module and is used for obtaining a fine timing result according to the potential transmission state.

In some embodiments, the fine timing module includes a fine timing control unit, a delay chain unit, a fine timing latch unit, and a coding unit, where the fine timing control unit is electrically connected to the output end of the timing stop processing module and the output end of the synchronization module, and is configured to output a corresponding potential signal according to the timing stop flag signal and the timing stop synchronization signal; the delay chain unit is electrically connected with the fine timing control unit and is used for transmitting the potential signal in a multi-stage delay manner; the fine timing latch unit is electrically connected with the delay chain unit and the synchronization module and is used for latching the potential transmission state of the potential signal after multistage delay transmission according to the timing stop synchronization signal; the coding unit is electrically connected with the fine timing latch unit and the calculating module and is used for obtaining a fine timing result according to the potential transmission state.

In some embodiments, the delay chain unit includes a plurality of adders, the plurality of adders are connected in series in sequence, a first input terminal of a first adder in the plurality of adders is electrically connected to an output terminal of the fine timing control unit, a second input terminal of the plurality of adders is connected to a high potential signal, a third input terminal of the plurality of adders is connected to a low potential signal, a summation output terminal of the plurality of adders is electrically connected to the fine timing latch unit, and a carry output terminal of a previous adder in the plurality of adders is electrically connected to a first input terminal of a next adder in the plurality of adders; the data input and output by each adder is binary data, the output result of the summation output end of each adder is the low order of the sum of the binary data accessed by the first input end of each adder, the binary data accessed by the second input end of each adder and the binary data accessed by the third input end of each adder, and the output result of the carry output end of each adder is the high order of the sum of the binary data accessed by the first input end of each adder, the binary data accessed by the second input end of each adder and the binary data accessed by the third input end of each adder.

In some embodiments, the fine timing control unit includes a first digital selector and a second digital selector, a first input terminal of the first digital selector is connected to the high-potential signal, a second input terminal of the first digital selector is connected to the low-potential signal, and a selection control terminal of the first digital selector is electrically connected to an output terminal of a first adder of the plurality of adders; the first input end of the second digital selector is connected with a high-potential signal, the second input end of the second digital selector is electrically connected with the summation output end of the last adder in the adders, the third input end of the second digital selector is electrically connected with the output end of the first digital selector, the first selection control end of the second digital selector is electrically connected with the output end of the timing stop processing module, and the second selection control end of the second digital selector is electrically connected with the output end of the synchronization module.

In some embodiments, the fine timing control unit includes a third digital selector, a first input terminal of the third digital selector is connected to the high-voltage signal, a second input terminal of the third digital selector is electrically connected to an output terminal of any one of the adders, and a selection control terminal of the third digital selector is electrically connected to an output terminal of the timing stop processing module.

In some embodiments, the fine timing latch unit includes a plurality of fourth flip-flops, trigger terminals of the plurality of fourth flip-flops are electrically connected to the output terminal of the synchronization module, reset terminals of the plurality of fourth flip-flops are all connected to the reset signal, non-inverting output terminals of the plurality of fourth flip-flops are electrically connected to the fine timing latch unit, and input terminals of a fourth flip-flop are electrically connected to a summation output terminal of an adder.

In some embodiments, the fine timing module further includes a counting unit, a reset terminal of the counting unit is connected to the reset signal, a latch terminal of the counting unit is electrically connected to the output terminal of the synchronization module, and an output terminal of the counting unit is electrically connected to the calculating module, and is configured to calculate the number of cycle periods in which the potential signal is transmitted in the plurality of adders.

In some embodiments, the counting unit includes a first counter, a reset terminal of the first counter is connected to the reset signal, a clock terminal of the first counter is electrically connected to a summing output terminal of any adder in the plurality of adders, and an output terminal of the first counter is electrically connected to the counting module, and is configured to count according to a rising edge and a falling edge to count a number of cycle periods in which the potential signal is transmitted in the plurality of adders.

In some embodiments, the counting unit includes a second counter and a third counter, a reset terminal of the second counter is connected to the reset signal, a clock terminal of the second counter is electrically connected to a summation output terminal of any one of the adders, and an output terminal of the second counter is electrically connected to the calculating module, and is configured to count according to a rising edge to calculate a first number of cycle periods during which the potential signal is transmitted in the adders; the reset end of the third counter is connected with a reset signal, the clock end of the third counter is electrically connected with the summation output end of any adder, and the output end of the third counter is electrically connected with the calculation module and used for counting according to the inverted rising edge so as to calculate the number of second cycle periods of the transmission of the potential signals in the adders; the calculation module obtains the number of the cycle periods according to the sum of the first cycle period number and the second cycle period number.

In some embodiments, the fine timing module further includes a counting unit, a reset terminal of the counting unit is connected to the reset signal, a clock terminal of the counting unit is electrically connected to an output terminal of any one of the adders, a latch terminal of the counting unit is electrically connected to an output terminal of the synchronization module, and an output terminal of the counting unit is electrically connected to the calculating module, and is configured to calculate the number of cycle periods in which the potential signal is transmitted in the adders.

In some embodiments, the counting unit includes a first counter, a reset terminal of the first counter is connected to the reset signal, a clock terminal of the first counter is electrically connected to a summing output terminal of any adder of the plurality of adders, a latch terminal of the first counter is electrically connected to an output terminal of the synchronization module, and an output terminal of the first counter is electrically connected to the counting module, and is configured to count according to a rising edge and a falling edge to count a number of cycle periods in which the potential signal is transmitted in the plurality of adders.

In some embodiments, the counting unit includes a second counter and a third counter, a reset terminal of the second counter is connected to the reset signal, a clock terminal of the second counter is electrically connected to a summation output terminal of any one of the adders, a latch terminal of the second counter is electrically connected to an output terminal of the synchronization module, and an output terminal of the second counter is electrically connected to the counting module, and is configured to count according to a rising edge to count a first number of cycle periods in which the potential signal is transmitted in the adders; the reset end of the third counter is connected with a reset signal, the clock end of the third counter is electrically connected with the summation output end of any adder, the latch end of the third counter is electrically connected with the output end of the synchronization module, and the output end of the third counter is electrically connected with the calculation module and used for counting according to the inverted rising edge so as to calculate the number of second cycle periods of the transmission of the potential signals in the adders; the calculation module obtains the number of the cycle periods according to the sum of the first cycle period number and the second cycle period number.

In a second aspect, the present application provides a time-to-digital conversion method, including: generating a timing stop flag signal according to the timing stop signal, the reset signal and the timing stop synchronization signal, wherein the pulse start time of the timing stop flag signal is the same as the pulse start time of the timing stop signal; generating a timing stop synchronization signal according to the clock signal, the reset signal and the timing stop flag signal; starting coarse clocking in response to a pulse start time of the clocking start signal, one pulse start time of the clock signal, and stopping coarse clocking in response to a pulse start time of the clocking stop synchronization signal, another pulse start time of the clock signal, the coarse clocking result being obtained based on a clock number of the clock signal between the starting of the coarse clocking and the stopping of the coarse clocking; starting the fine clocking in response to the pulse start time of the clocking stop flag signal, stopping the fine clocking in response to the pulse start time of the clocking stop synchronization signal, and obtaining a fine clocking result based on the number of clocks of the clock signal between the starting of the fine clocking and the stopping of the fine clocking; and determining the timing result of the time-to-digital conversion device according to the clock signal, the difference value of the coarse timing result and the fine timing result.

In some embodiments, the step of generating the timing stop flag signal according to the timing stop signal, the reset signal, and the timing stop synchronization signal includes: constructing an input end of a first trigger to be accessed with a high-potential signal and a trigger end of the first trigger to be accessed with a timing stop signal; one input end of the OR gate is connected with a timing stop synchronous signal, the other input end of the OR gate is connected with a reset signal, and the output end of the OR gate is electrically connected with the reset end of the first trigger; and configuring the non-inverting output end of the first trigger to output a timing stop flag signal.

In some embodiments, the step of generating the timing stop synchronization signal according to the clock signal, the reset signal, and the timing stop flag signal includes: the input end of a second trigger is electrically connected with the positive phase output end of the first trigger, the trigger end of the second trigger is connected with a clock signal, and the reset end of the second trigger is connected with a reset signal; the input end of a third trigger is electrically connected with the normal phase output end of the second trigger, the trigger end of the third trigger is connected with a clock signal, the reset end of the third trigger is connected with a reset signal, and the in-phase output end of the third trigger is electrically connected with one input end of an OR gate; and configuring the in-phase output end of the third trigger to output a timing stop synchronization signal.

According to the time-to-digital conversion device and the time-to-digital conversion method, the timing stop mark signal output by the timing stop processing module and the timing stop synchronous signal output by the synchronous module correspondingly control the coarse timing result of the coarse timing module and the fine timing result of the fine timing module, so that the probability of metastable state generation caused by the fact that the timing stop signal is an asynchronous signal can be reduced, and the accuracy of the time-to-digital conversion result is improved; meanwhile, the calculation module can determine that the difference value of the coarse timing result and the fine timing result is the timing result of the time-to-digital conversion device, and even if the coarse timing result and the fine timing result are influenced by the metastable state in the time-to-digital conversion process, the metastable state influence on the timing result can be further counteracted through the subtraction operation of the coarse timing result and the fine timing result, so that the accuracy of the time-to-digital conversion result is further improved.

Drawings

The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a time-to-digital converter in a conventional technical solution.

FIG. 2 is a timing diagram of the time-to-digital converter shown in FIG. 1.

Fig. 3 is a schematic structural diagram of a time-to-digital conversion apparatus according to an embodiment of the present application.

FIG. 4 is a timing diagram illustrating the generation of meta-stability in a flip-flop according to an embodiment of the present invention.

Fig. 5 is a schematic flowchart of a delay chain unit according to an embodiment of the present application.

Fig. 6 is a schematic structural diagram of a delay chain unit according to an embodiment of the present application.

Fig. 7 is a timing diagram of the time-to-digital conversion apparatus shown in fig. 3.

Fig. 8 is a schematic structural diagram of a second time-to-digital conversion apparatus according to an embodiment of the present application.

Fig. 9 is a timing diagram of the time-to-digital conversion apparatus shown in fig. 8.

Fig. 10 is a schematic structural diagram of the fine timing control unit shown in fig. 8.

Fig. 11 is a schematic structural diagram of a third time-to-digital conversion apparatus according to an embodiment of the present application.

Fig. 12 is a schematic structural diagram of the fine timing control unit shown in fig. 11.

Fig. 13 is a schematic flowchart of a counting unit according to an embodiment of the present application.

Fig. 14 is a timing diagram of a counting unit according to an embodiment of the present disclosure.

Fig. 15 is a flowchart illustrating a time-to-digital conversion method according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Referring to fig. 3 to 14, as shown in fig. 3 and 7, or fig. 8 and 9, the present embodiment provides a time-to-digital conversion apparatus, which includes a timing Stop processing module 100, a synchronization module 200, a coarse timing module 300, a fine timing module 400 and a calculation module 500, wherein the timing Stop processing module 100 is configured to generate a timing Stop flag signal Stop _ flag according to a timing Stop signal Stop _ signal, a reset signal RST and a timing Stop synchronization signal Stop _ flag _ d2, a pulse start time of the timing Stop flag signal Stop _ flag is the same as a pulse start time of the timing Stop signal Stop _ signal, and a pulse duration of the timing Stop flag signal Stop _ flag is smaller than a pulse duration of the timing Stop signal Stop _ signal; the synchronization module 200 is electrically connected to the timing Stop processing module 100, and configured to generate a timing Stop synchronization signal Stop _ flag _ d2 according to the clock signal CLK, the reset signal RST and the timing Stop flag signal Stop _ flag, where a pulse start time of the timing Stop synchronization signal Stop _ flag _ d2 is the same as a pulse end time of the timing Stop flag signal Stop _ flag; the Coarse timing module 300 is electrically connected to the synchronization module 200, starts Coarse timing in response to a pulse Start time of the Start timing signal Start _ trig and a pulse Start time of the clock signal CLK, stops Coarse timing in response to a pulse Start time of the Stop timing synchronization signal Stop _ flag _ d2 and another pulse Start time of the clock signal CLK, and obtains a Coarse timing result Coarse _ rst based on a clock number of the clock signal CLK between the Start of Coarse timing and the Stop of Coarse timing; the fine timing module 400 is electrically connected to the timing Stop processing module 100 and the synchronization module 200, starts fine timing in response to the pulse start time of the timing Stop flag signal Stop _ flag, stops fine timing in response to the pulse start time of the timing Stop synchronization signal Stop _ flag _ d2, and obtains a fine timing result based on the clock number of the clock signal CLK between the start of fine timing and the Stop of fine timing; the calculating module 500 is electrically connected to the Coarse timing module 300 and the fine timing module 400, and is configured to determine a timing result of the time-to-digital conversion apparatus according to the clock signal CLK, a difference between the Coarse timing result Coarse _ rst and the fine timing result.

It can be understood that, in the time-to-digital conversion apparatus provided in this embodiment, the Coarse timing result Coarse _ rst of the Coarse timing module 300 and the fine timing result of the fine timing module 400 are correspondingly controlled by the timing Stop flag signal Stop _ flag outputted by the timing Stop processing module 100 and the timing Stop synchronization signal Stop _ flag _ d2 outputted by the synchronization module 200, so that the metastable state probability caused by the asynchronous signal of the timing Stop signal Stop _ signal can be reduced, and the accuracy of the time-to-digital conversion result can be improved; meanwhile, the calculation module 500 may determine that the difference between the Coarse timing result Coarse _ rst and the fine timing result is the timing result of the time-to-digital conversion apparatus, and even if the Coarse timing result Coarse _ rst and the fine timing result are influenced by the metastable state in the time-to-digital conversion process, the metastable state influence on the timing result may be further counteracted through the subtraction operation of the Coarse timing result Coarse _ rst and the fine timing result, thereby further improving the accuracy of the time-to-digital conversion result.

Here, the fine timing result shown in fig. 3 may also be represented as the fine timing result Delay _ chain _ cnt shown in fig. 7. The Coarse clocking result Coarse _ rst may be an integer number of clock cycles of the clock signal CLK. The fine timing result may not include the decimal clock period of the clock signal CLK, may also include the decimal clock period of the clock signal CLK, and may also include the integer number of clock periods of the clock signal CLK and the decimal number of clock periods of the clock signal CLK.

As shown in fig. 3, in one embodiment, the timing Stop processing module 100 includes a first flip-flop D1 and an OR gate OR, an input terminal of the first flip-flop D1 is connected to a high signal, a trigger terminal of the first flip-flop D1 is connected to a timing Stop signal Stop _ signal, and a non-inverting output terminal of the first flip-flop D1 outputs a timing Stop flag signal Stop _ flag; one input end of the OR gate OR is connected to the timing Stop synchronization signal Stop _ flag _ D2, the other input end of the OR gate OR is connected to the reset signal RST, and the output end of the OR gate OR is electrically connected to the reset end of the first flip-flop D1.

It is to be understood that it is thus possible to configure that the rising edge of the timing Stop signal Stop _ signal is at the same timing as the rising edge of the timing Stop flag signal Stop _ flag, and the falling edge of the timing Stop flag signal Stop _ flag is at the same timing as the rising edge of the timing Stop synchronization signal Stop _ flag _ d 2.

In one embodiment, the synchronization module 200 includes at least one flip-flop, the at least one flip-flop is sequentially connected in series, an input terminal of a first flip-flop of the at least one flip-flop is electrically connected to a non-inverting output terminal of the first flip-flop D1, a non-inverting output terminal of a last flip-flop of the at least one flip-flop is electrically connected to an input terminal of the OR gate OR, the flip-flop terminals of the at least one flip-flop are all connected to the clock signal CLK, and the reset terminal of the at least one flip-flop is all connected to the reset signal RST.

It is to be understood that, every time a trigger is passed in this way, the timing Stop flag signal Stop _ flag is delayed for a period of time until the rising edge of the delay timing Stop synchronizing signal Stop _ flag _ d2 reaches the falling edge of the timing Stop flag signal Stop _ flag, and then the timing result is obtained by the calculation step based on the timing result.

In one embodiment, the synchronization module 200 includes a second flip-flop D2 and a third flip-flop D3, an input terminal of the second flip-flop D2 is electrically connected to a non-inverting output terminal of the first flip-flop D1, a trigger terminal of the second flip-flop D2 is connected to the clock signal CLK, and a reset terminal of the second flip-flop D2 is connected to the reset signal RST; the input terminal of the third flip-flop D3 is electrically connected to the non-inverting output terminal of the second flip-flop D2, the trigger terminal of the third flip-flop D3 is connected to the clock signal CLK, the reset terminal of the third flip-flop D3 is connected to the reset signal RST, and the non-inverting output terminal of the third flip-flop D3 is electrically connected to an input terminal of the OR gate OR.

As shown in fig. 3, in one embodiment, the fine timing module 400 includes a delay chain unit 420, a fine timing latch unit 430, and an encoding unit 440, where the delay chain unit 420 is electrically connected to the output end of the timing stop processing module 100, and is used for multi-stage delay transmission of the potential signal; the fine timing latch unit 430 is electrically connected to the delay chain unit 420 and the synchronization module 200, and is configured to latch a potential transmission state of the potential signal after multi-stage delay transmission according to the timing Stop synchronization signal Stop _ flag _ d 2; the encoding unit 440 is electrically connected to the fine timing latch unit 430 and the calculating module 500, and is configured to obtain a fine timing result according to the potential transmission state.

It can be understood that, as shown in the timing diagram of the flip-flop in fig. 4, if the clock signal CLK does not satisfy the setup time Tsu and the hold time Th of the flip-flop in data transmission, or the recovery time (recovery time) of the release of the reset signal RST with respect to the active clock edge during reset is not satisfied, a metastable state may be generated, where the output Q of the flip-flop is in an indeterminate state for a relatively long time after the active clock edge, and the Q is in an oscillating state between 0 and 1 instead of being equal to the value of the data input D. This time is called the resolution time (Tmet). After the resolution time, the Q end will stabilize to 0 or 1, but stabilize to 0 or 1, which is random and has no necessary relation with the input.

In view of this, the second flip-flop D2 and the third flip-flop D3 are disposed in the synchronization block 200, and the influence of the metastable state on the timing accuracy can be further reduced through the delay processing of the two stages of flip-flops.

As shown in fig. 8 or fig. 11, in one embodiment, the fine timing module 400 includes a fine timing control unit 410, a delay chain unit 420, a fine timing latch unit 430 and an encoding unit 440, wherein the fine timing control unit 410 is electrically connected to the output terminal of the timing Stop processing module 100 and the output terminal of the synchronization module 200, and is configured to output corresponding potential signals according to the timing Stop flag signal Stop _ flag and the timing Stop synchronization signal Stop _ flag _ d 2; the delay chain unit 420 is electrically connected with the fine timing control unit 410, and is used for transmitting the potential signal in a multi-stage delay manner; the fine timing latch unit 430 is electrically connected to the delay chain unit 420 and the synchronization module 200, and is configured to latch a potential transmission state of the potential signal after multi-stage delay transmission according to the timing Stop synchronization signal Stop _ flag _ d 2; the encoding unit 440 is electrically connected to the fine timing latch unit 430 and the calculating module 500, and is configured to obtain a fine timing result according to the potential transmission state.

It is to be understood that, as shown in fig. 5, the delay chain unit 420 may be formed by an inverter and a buffer, and when the initial potential state, i.e., the timing Stop flag signal Stop _ flag, is low or 0, each potential state in the delay chain unit 420 may be all 0 or 1, taking the initial state all 0 as an example: when the timing Stop flag signal Stop _ flag is at high level or 1, the level signal 1 starts to propagate in the delay chain unit 420, the level signal 1 is inverted to the level signal 0 after propagating to bit (N-1), and the level signal 0 starts to propagate in the delay chain unit 420. When the rising edge of the timing Stop synchronizing signal Stop _ flag _ d2 arrives, the fine timing latch unit 430 correspondingly latches 0 and 1 in the delay chain unit 420 according to the potential transmission state after multi-stage delay transmission, i.e., the rising edge time of the timing Stop synchronizing signal Stop _ flag _ d2, and the encoding unit 440 obtains the timing result of the delay chain unit 420 according to the positions and the number of 0 and 1 in the fine timing latch unit 430.

In the embodiment with the counting unit 450, the sum of the counting result of the delay chain unit 420 and the counting result of the counting unit 450 is the fine timing result of the fine timing module 400.

Where the triangular symbols in fig. 5 may be characterized as buffers for delay. The triangle symbol of the cusp plus circle in fig. 5 may be characterized as an inverter for potential inversion.

As shown in fig. 6, in one embodiment, the delay chain unit 420 includes a plurality of adders 421, the plurality of adders 421 are sequentially connected in series, a first input terminal of a first adder in the plurality of adders 421 is electrically connected to an output terminal of the fine timing control unit 410, second input terminals of the plurality of adders 421 are connected to a high voltage signal, third input terminals of the plurality of adders 421 are connected to a low voltage signal, a summation output terminal of the plurality of adders 421 is electrically connected to the fine timing latch unit 430, and a carry output terminal of a previous adder in the plurality of adders 421 is electrically connected to a first input terminal of a next adder in the plurality of adders 421; the data input and output by each adder is binary data, the output result of the summation output end of each adder is the low order of the sum of the binary data accessed by the first input end of each adder, the binary data accessed by the second input end of each adder and the binary data accessed by the third input end of each adder, and the output result of the carry output end of each adder is the high order of the sum of the binary data accessed by the first input end of each adder, the binary data accessed by the second input end of each adder and the binary data accessed by the third input end of each adder.

It can be understood that, by using the delay chain unit 420 formed by buffers, inverters, etc., the delay of the routing between the buffers and the inverters, and between the buffers and the buffers is difficult to control. In the embodiment, the adding carry chain unit formed by the adder has small time delay, compact structure and simple realization.

As shown in fig. 3, in one embodiment, the fine timing latch unit 430 includes a plurality of fourth flip-flops D4, trigger terminals of the plurality of fourth flip-flops D4 are electrically connected to the output terminal of the synchronization module 200, reset terminals of the plurality of fourth flip-flops D4 are all connected to the reset signal RST, non-inverting output terminals of the plurality of fourth flip-flops D4 are electrically connected to the fine timing latch unit 430, and input terminals of a fourth flip-flop D4 are electrically connected to a summing output terminal of an adder.

It will be appreciated that each fourth flip-flop D4 is configured to latch a potential state accordingly.

As shown in fig. 3 and 7, the operation process of the time-to-digital conversion apparatus in the above embodiment is as follows:

the clock signal CLK and the Start timing signal Start _ trig are synchronous signals, and the rising edges of the clock signal CLK and the Start timing signal Start _ trig arrive at the same time and Start coarse timing. The rising edge of the timing Stop signal Stop _ signal comes at the same time as the rising edge of the timing Stop flag signal Stop _ flag and starts the fine timing. When the rising edge of the timing Stop synchronization signal Stop _ flag _ d2 comes, the falling edge of the timing Stop flag signal Stop _ flag is generated; at the same time, the coarse timer and the fine timer are stopped at the same time. The timing result is the difference between the coarse timing and the fine timing. Wherein Stop _ flag _ D1 is a signal output from the non-inverting output terminal of the second flip-flop D2.

As shown in fig. 8, in one embodiment, the fine timing module 400 further includes a counting unit 450, a reset terminal of the counting unit 450 receives the reset signal RST, a clock terminal of the counting unit 450 is electrically connected to a summing output terminal of any adder of the adders 421, and an output terminal of the counting unit 450 is electrically connected to the calculating module 500 for calculating the number of cycle periods of the potential signal transmitted in the adders 421.

In one embodiment, the counting unit 450 includes a first counter, a reset terminal of the first counter is connected to the reset signal RST, a clock terminal of the first counter is electrically connected to a summing output terminal of any adder in the adders 421, and an output terminal of the first counter is electrically connected to the calculating module 500, and is configured to count according to a rising edge and a falling edge to calculate the number of cycle periods of the potential signal transmitted in the adders 421.

In one embodiment, the counting unit 450 includes a second counter and a third counter, a reset terminal of the second counter is connected to the reset signal RST, a clock terminal of the second counter is electrically connected to a summation output terminal of any adder in the adders 421, and an output terminal of the second counter is electrically connected to the calculating module 500, and is configured to count according to a rising edge to calculate a first number of cycle periods of the potential signal transmitted in the adders 421; the reset end of the third counter is connected to the reset signal RST, the clock end of the third counter is electrically connected to the summation output end of any adder, and the output end of the third counter is electrically connected to the calculation module 500, and is configured to count according to the inverted rising edge to calculate the number of second cycle periods in which the potential signal is transmitted in the plurality of adders 421; the calculating module 500 obtains the number of the cycle periods according to the sum of the first number of the cycle periods and the second number of the cycle periods.

As shown in fig. 11, in one embodiment, the fine timing module 400 further includes a counting unit 450, a reset terminal of the counting unit 450 is connected to the reset signal RST, a clock terminal of the counting unit 450 is electrically connected to a summing terminal of any one of the adders 421, a latch terminal of the counting unit 450 is electrically connected to an output terminal of the synchronization module 200, and an output terminal of the counting unit 450 is electrically connected to the calculating module 500 for calculating the number of cycle periods of the potential signal transmitted in the adders 421.

Among them, the counting unit 450 may latch the current counting result in response to the timing Stop synchronization signal Stop _ flag _ d 2.

It is understood that when the fine timing module 400 does not include the counting unit 450, the number of adders in the delay chain unit 420, i.e. the adder carry chain, needs to cover at least one clock cycle of the clock signal CLK, for example, two clock cycles, so that the potential state transmitted in the delay chain unit 420 may not be repeatedly and completely recorded, and if the number is small, data overflow may be caused, and the timing result may be affected. In this case, as the frequency of the clock signal CLK decreases, a larger number of adders are required. That is, the number of adders is related to the frequency of the clock signal CLK, the delay of each adder. Wherein, as the delay of each adder increases, the more adders are required.

In this embodiment, a counting scheme combining the counting unit 450 and the short adder chain may be adopted, where the counting unit 450 adds 1 to each time a potential state input into the delay chain unit 420 is transmitted for one cycle, and the short adder chain only needs to record the potential state within one cycle of the clock signal CLK, and the result of the two is the fine timing result after the superposition. Therefore, the length of the delay chain unit 420 can be reduced to adapt to the clock frequency of different systems. For the delay chain unit 420 with N bits length, i.e. including N adders, when the output signal of the fine timing control unit 410 is transmitted from the output signal of the 1 st adder [0] in the delay chain unit 420 to the output signal of the nth adder [ N-1] in the delay chain unit 420, it is considered that the signal has propagated for a time period of one delay chain, i.e. N adders, and then the count result of the counting unit 450 is incremented by 1.

The first specific counting method for implementing the counting unit 450 may be: the N-bit (bits) length delay chain unit 420 takes the output signal of the nth adder [ N-1] in the delay chain unit 420 as the counting clock of the counting unit 450, and the timing Stop synchronization signal Stop _ flag _ d2 triggers the fine timing latch unit 430 to latch, but because the output signal of the nth adder [ N-1] and the timing Stop synchronization signal Stop _ flag _ d2 in the delay chain unit 420 are asynchronous signals, a metastable state may exist during latching, which results in the counting unit 450 counting more or less than 1. Therefore, after the timing Stop synchronization signal Stop _ flag _ d2 triggers the fine timing latch unit 430 to latch, the encoding unit 440 can check the latch result, and determine whether the counting unit 450 counts more or less 1 by checking whether the delay chain unit 420 is transmitting 0 or 1, thereby ensuring the counting accuracy of the counting unit 450.

A first specific counting method for implementing the counting unit 450 may be: when the rising edge of the timing Stop synchronization signal Stop _ flag _ d2 arrives, the delay chain unit 420 stops counting, and the fine timing control unit 410 keeps the value of the 1 st adder output signal hermometer [0] in the delay chain unit 420 unchanged. The output signal of the adder 1 in the delay chain unit 420, the electrometer [0], is used as the clock signal CLK of the counting unit 450, and the counting unit 450 counts at the rising edge and the falling edge of the clock signal CLK respectively. For the Nbits delay chain unit 420, any one of the output signals from the 2 nd adder [1] in the delay chain unit 420 to the nth adder [ N-1] in the delay chain unit 420 is generated after the delay of the output signal from the 1 st adder [0] in the delay chain unit 420, and therefore, the output signals from the any one adder [0] in the delay chain unit 420 to the nemeter [ N-1] can be used as the clock signal CLK of the counting unit 450.

As shown in fig. 9, the operation of the time-to-digital conversion apparatus shown in fig. 8 is as follows:

the clock signal CLK and the Start timing signal Start _ trig are synchronous signals, and the rising edges of the clock signal CLK and the Start timing signal Start _ trig arrive at the same time and Start coarse timing. The rising edge of the timing Stop signal Stop _ signal comes at the same time as the rising edge of the timing Stop flag signal Stop _ flag and starts the fine timing. When the rising edge of the timing Stop synchronization signal Stop _ flag _ d2 comes, the falling edge of the timing Stop flag signal Stop _ flag is generated; at the same time, the coarse timer and the fine timer are stopped at the same time. The timing result is the difference between the coarse timing and the fine timing.

Wherein, the count result CNT of the count unit 450 is 0 before the fine timing is not started, and both the rising edge and the falling edge of the output signal nemometer [0] of the 1 st adder in the delay chain unit 420 are counted, then before the rising edge of the timing Stop synchronization signal Stop _ flag _ d2 arrives, the sum of the rising edge and the falling edge of the output signal nemometer [0] of the 1 st adder in the delay chain unit 420, that is, the count result of the count unit 450 is 8, then the count result minus 1 is the number of cycle periods that the delay chain unit 420 has transmitted, that is, 7, correspondingly, the fine timing result includes the length of 7 entire delay chains and the length of a fractional delay chain.

As shown in fig. 10, in one embodiment, the fine timing control unit 410 includes a first digital selector MUX1 and a second digital selector MUX2, a first input terminal of the first digital selector MUX1 receives a high voltage signal, a second input terminal of the first digital selector MUX1 receives a low voltage signal, and a selection control terminal of the first digital selector MUX1 is electrically connected to an output terminal of a first adder in the plurality of adders 421; the first input terminal of the second digital selector MUX2 is connected to the high-level signal, the second input terminal of the second digital selector MUX2 is electrically connected to the output terminal of the last adder of the plurality of adders 421, the third input terminal of the second digital selector MUX2 is electrically connected to the output terminal of the first digital selector MUX1, the first selection control terminal of the second digital selector MUX2 is electrically connected to the output terminal of the timing stop processing module 100, and the second selection control terminal of the second digital selector MUX2 is electrically connected to the output terminal of the synchronization module 200.

It is to be understood that, when the timing Stop flag signal Stop _ flag is 0 and the timing Stop synchronization signal Stop _ flag _ d2 is 0, the channel 0 is opened, the output signal of the fine timing control unit 410 is maintained at 1, and the delay chain unit 420 is stabilized. When the Stop timing flag signal Stop _ flag is 1, the channel 1 is turned on, the output signal of the fine timing control unit 410 is the output signal of the nth adder [ N-1] in the delay chain unit 420, the inversion is started, and the signal starts to propagate in the delay chain unit 420. When the Stop timing synchronization signal Stop _ flag _ d2 is 1, the channel 2/3 is turned on to keep the value of the 1 st adder output signal hermometer [0] in the delay chain unit 420 unchanged, and the delay chain unit 420 stops signal propagation, so that the delay chain unit 420 does not turn over any more.

As shown in fig. 12, the fine timing control unit 411 may include a digital selector MUX3, in the nbits delay chain unit 420, the output signal of the nth adder [ N-1] in the delay chain unit 420 is used as the counting clock of the counting unit 450, and the counting unit 450 is latched when the rising edge of the Stop timing synchronization signal Stop _ flag _ d2 arrives, but because the output signal of the nth adder [ N-1] in the delay chain unit 420 and the Stop timing synchronization signal Stop _ flag _ d2 are asynchronous signals, there may be a metastable state during latching, which may result in the counting unit 450 counting more or less 1. Therefore, when the rising edge of the timing Stop synchronization signal Stop _ flag _ d2 arrives, the latch result in the fine timing latch unit 430 can be used to determine whether the delay chain unit 420 is transmitting 0 or 1, so that it can be determined whether the count unit 450 counts more or less 1, and the accuracy of the count of cnt can be ensured.

As shown in fig. 13 and 14, the parity of the count result CNT is related to the potential transfer state when the delay chain unit 420 is latched, and when the rising edge of the timing Stop synchronization signal Stop _ flag _ d2 arrives, the fine count Latch unit latches (Latch) the potential transferred in the delay chain unit 420, and thus, it is possible to determine whether the delay chain unit 420 is pass 0 or pass 1 according to the Latch data of the fine count Latch unit. When the count result CNT is Odd (Odd) in the case of Send 0, the count result CNT is correct if the count result CNT is Odd; if the count result CNT is Even (Even), 1 should be added to the count result CNT. When the number of the counting result CNT is 1, the counting result CNT is an even number, and if the counting result CNT is the even number, the counting result CNT is correct; if the counting result CNT is odd, 1 should be added to the counting result CNT. In this way, the correct final count result Rslt can be obtained.

Specifically, the count result CNT is obtained as follows:

the first method comprises the following steps: the counting unit 450 includes a first counter, a reset terminal of the first counter is connected to the reset signal RST, a clock terminal of the first counter is electrically connected to a summation output terminal of any adder of the adders 421, a latch terminal of the first counter is electrically connected to an output terminal of the synchronization module 200, and an output terminal of the first counter is electrically connected to the calculating module 500, and is configured to count according to a rising edge and a falling edge to calculate the number of cycle periods of the potential signal transmitted in the adders 421.

For example, the trigger end of the first counter is connected to the output signal of the 64 th adder [63] in the delay chain unit 420, and the output signal of the 64 th adder [63] is used as the counting clock of the first counter, and the rising edge and the falling edge of the output signal of the 64 th adder [63] are counted respectively, and the actual number of the cycle period is the counting result CNT-1.

In the second method, the counting unit 450 includes a second counter and a third counter, a reset end of the second counter is connected to the reset signal RST, a clock end of the second counter is electrically connected to a summation output end of any adder in the adders 421, a latch end of the second counter is electrically connected to an output end of the synchronization module 200, and an output end of the second counter is electrically connected to the calculating module 500, and is configured to count according to a rising edge to calculate a first number of cycle periods of transmission of the potential signal in the adders 421; the reset end of the third counter is connected to the reset signal RST, the clock end of the third counter is electrically connected to the summation output end of any adder, the latch end of the third counter is electrically connected to the output end of the synchronization module 200, and the output end of the third counter is electrically connected to the calculation module 500, and is configured to count according to the inverted rising edge to calculate the number of second cycle periods in which the potential signal is transmitted in the plurality of adders 421; the calculating module 500 obtains the number of the cycle periods according to the sum of the first number of the cycle periods and the second number of the cycle periods.

For example, the trigger end of the second counter is connected to the output signal of the 64 th adder [63] of the delay chain unit 420, which is used as the counting clock of the second counter, and the rising edge count counts for 4. The trigger end of the third counter is connected to the output signal, the electrometer [63], of the 64 th adder in the inverted delay chain unit 420, which is used as the counting clock of the third counter, and the rising edge count is counted for 3. The actual number of cycle periods is the count result CNT-1.

In one embodiment, the first flip-flop D1, the second flip-flop D2, the third flip-flop D3, and at least one of the flip-flops may each be a D flip-flop; alternatively, the plurality of fourth flip-flops D4 may each be a D flip-flop.

As shown in fig. 15, in one embodiment, the present embodiment provides a time-to-digital conversion method, which includes the following steps:

step S10: and generating a timing Stop flag signal Stop _ flag according to the timing Stop signal Stop _ signal, the reset signal RST and the timing Stop synchronization signal Stop _ flag _ d2, wherein the pulse start time of the timing Stop flag signal Stop _ flag is the same as the pulse start time of the timing Stop signal Stop _ signal, and the pulse duration of the timing Stop flag signal Stop _ flag is less than the pulse duration of the timing Stop signal Stop _ signal.

Step S20: the timing Stop synchronizing signal Stop _ flag _ d2 is generated based on the clock signal CLK, the reset signal RST and the timing Stop flag signal Stop _ flag, and the pulse start time of the timing Stop synchronizing signal Stop _ flag _ d2 is the same as the pulse end time of the timing Stop flag signal Stop _ flag.

Step S30: the Coarse clocking is started in response to the pulse Start time of the clocking Start signal Start _ trig, one pulse Start time of the clock signal CLK, and the Coarse clocking is stopped in response to the pulse Start time of the clocking Stop synchronizing signal Stop _ flag _ d2, the other pulse Start time of the clock signal CLK, and the Coarse clocking result Coarse _ rst is obtained based on the number of clocks of the clock signal CLK between the Start of the Coarse clocking and the Stop of the Coarse clocking.

Step S40: the minute counting is started in response to the pulse start time of the count Stop flag signal Stop _ flag, stopped in response to the pulse start time of the count Stop synchronizing signal Stop _ flag _ d2, and a minute counting result is obtained based on the number of clocks of the clock signal CLK between the start of the minute counting and the Stop of the minute counting.

And step S50: and determining the timing result of the time-to-digital conversion device according to the clock signal CLK, the difference value of the Coarse timing result Coarse _ rst and the fine timing result.

It can be understood that, in the time-to-digital conversion method provided in this embodiment, the Coarse timing result Coarse _ rst and the fine timing result are correspondingly controlled by the timing Stop flag signal Stop _ flag and the timing Stop synchronization signal Stop _ flag _ d2, so that the metastable state influence caused by the asynchronous signal serving as the timing Stop signal Stop _ signal can be alleviated or eliminated, and the accuracy of the time-to-digital conversion result is improved; meanwhile, the difference value between the Coarse timing result Coarse _ rst and the fine timing result can be determined as the timing result of the time-to-digital conversion device, and even if the Coarse timing result Coarse _ rst and the fine timing result are influenced by a metastable state in the time-to-digital conversion process, the metastable state influence on the timing result can be further reduced or eliminated through the subtraction operation of the Coarse timing result Coarse _ rst and the fine timing result, so that the accuracy of the time-to-digital conversion result is further improved.

In one embodiment, the step of generating the timing Stop flag signal Stop _ flag according to the timing Stop signal Stop _ signal, the reset signal RST and the timing Stop synchronization signal Stop _ flag _ d2 includes: an input end of a first trigger D1 is connected with a high-potential signal, and a trigger end of a first trigger D1 is connected with a timing Stop signal Stop _ signal; one input end of the OR gate is connected with the timing Stop synchronizing signal Stop _ flag _ D2, the other input end of the OR gate is connected with the reset signal RST, and the output end of the OR gate is electrically connected with the reset end of the first trigger D1; and a non-inverting output terminal of the first flip-flop D1 is configured to output the timing Stop flag signal Stop _ flag.

In one embodiment, the step of generating the timing Stop synchronization signal Stop _ flag _ d2 according to the clock signal CLK, the reset signal RST and the timing Stop flag signal Stop _ flag includes: the input end of a second flip-flop D2 is electrically connected with the non-inverting output end of a first flip-flop D1, the trigger end of the second flip-flop D2 is connected with a clock signal CLK, and the reset end of the second flip-flop D2 is connected with a reset signal RST; the input end of a third flip-flop D3 is electrically connected with the non-inverting output end of a second flip-flop D2, the trigger end of the third flip-flop D3 is connected with a clock signal CLK, the reset end of the third flip-flop D3 is connected with a reset signal RST, and the non-inverting output end of the third flip-flop D3 is electrically connected with one input end of an OR gate; and a non-inverting output terminal of the third flip-flop D3 is configured to output a timing Stop synchronizing signal Stop _ flag _ D2.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The time-to-digital conversion apparatus and the time-to-digital conversion method provided in the embodiments of the present application are described in detail above, and specific examples are applied in the present application to explain the principle and the implementation of the present application, and the description of the above embodiments is only used to help understand the technical solutions and the core ideas of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A time-to-digital conversion apparatus, comprising:

the timing stop processing module is used for generating a timing stop mark signal according to a timing stop signal, a reset signal and a timing stop synchronous signal, wherein the pulse starting time of the timing stop mark signal is the same as the pulse starting time of the timing stop signal;

the synchronization module is electrically connected with the timing stop processing module and is used for generating the timing stop synchronization signal according to a clock signal, the reset signal and the timing stop mark signal;

the coarse timing module is electrically connected with the synchronization module, starts coarse timing in response to the pulse starting time of a timing starting signal and one pulse starting time of the clock signal, stops coarse timing in response to the pulse starting time of the timing stopping synchronization signal and the other pulse starting time of the clock signal, and obtains a coarse timing result based on the clock number of the clock signal between the start coarse timing and the stop coarse timing;

a fine timing module electrically connected to the timing stop processing module and the synchronization module, starting fine timing in response to a pulse start time of the timing stop flag signal, stopping fine timing in response to a pulse start time of the timing stop synchronization signal, and obtaining a fine timing result based on a clock number of the clock signal between the starting fine timing and the stopping fine timing; and

and the calculation module is electrically connected with the coarse timing module and the fine timing module and used for determining the timing result of the time-to-digital conversion device according to the clock signal, the difference value of the coarse timing result and the fine timing result.

2. The time-to-digital conversion apparatus according to claim 1, wherein the timer stop processing module comprises:

the input end of the first trigger is connected with a high-potential signal, the trigger end of the first trigger is connected with the timing stop signal, and the non-inverting output end of the first trigger outputs the timing stop mark signal; and

and one input end of the OR gate is connected with the timing stop synchronizing signal, the other input end of the OR gate is connected with the reset signal, and the output end of the OR gate is electrically connected with the reset end of the first trigger.

3. The time-to-digital conversion apparatus of claim 2, wherein the synchronization module comprises:

the flip-flops are sequentially connected in series, the input end of a first flip-flop in the flip-flops is electrically connected with the positive phase output end of the first flip-flop, the positive phase output end of a last flip-flop in the flip-flops is electrically connected with one input end of the OR gate, the trigger ends of the flip-flops are all connected into the clock signal, and the reset ends of the flip-flops are all connected into the reset signal.

4. The time-to-digital conversion apparatus of claim 3, wherein the synchronization module comprises:

the input end of the second trigger is electrically connected with the positive phase output end of the first trigger, the trigger end of the second trigger is connected to the clock signal, and the reset end of the second trigger is connected to the reset signal; and

the input end of the third trigger is electrically connected with the normal phase output end of the second trigger, the trigger end of the third trigger is connected to the clock signal, the reset end of the third trigger is connected to the reset signal, and the in-phase output end of the third trigger is electrically connected with one input end of the OR gate.

5. The time-to-digital conversion apparatus of claim 1, wherein the fine timing module comprises:

the time delay chain unit is electrically connected with the output end of the timing stop processing module and is used for transmitting potential signals in a multistage time delay manner;

the fine timing latch unit is electrically connected with the delay chain unit and the synchronization module and used for latching the potential transmission state of the potential signal after multistage delay transmission according to the timing stop synchronization signal; and

and the coding unit is electrically connected with the fine timing latch unit and the calculation module and is used for obtaining the fine timing result according to the potential transmission state.

6. The time-to-digital conversion apparatus of claim 1, wherein the fine timing module comprises:

the fine timing control unit is electrically connected with the output end of the timing stop processing module and the output end of the synchronization module and used for outputting corresponding potential signals according to the timing stop mark signals and the timing stop synchronization signals;

the delay chain unit is electrically connected with the fine timing control unit and is used for transmitting the potential signal in a multi-stage delay manner;

7. The time-to-digital conversion apparatus of claim 6, wherein the delay chain unit comprises:

the adders are sequentially connected in series, a first input end of a first adder in the adders is electrically connected with an output end of the fine timing control unit, a second input end of the adders is connected with a high-potential signal, a third input end of the adders is connected with a low-potential signal, a summation output end of the adders is electrically connected with the fine timing latch unit, and a carry output end of a previous adder in the adders is electrically connected with a first input end of a next adder in the adders;

the data input and output by each adder is binary data, the output result of the summation output end of each adder is the low order bits of the sum of the binary data accessed by the first input end of the adder, the binary data accessed by the second input end of the adder and the binary data accessed by the third input end of the adder, and the output result of the carry output end of each adder is the high order bits of the sum of the binary data accessed by the first input end of the adder, the binary data accessed by the second input end of the adder and the binary data accessed by the third input end of the adder.

8. The time-to-digital conversion apparatus according to claim 7, wherein the fine timing control unit includes:

a first digital selector, a first input end of which is connected with a high potential signal, a second input end of which is connected with a low potential signal, and a selection control end of the first digital selector is electrically connected with an output end of a first adder in the adders; and

a first input end of the second digital selector is connected with a high-potential signal, a second input end of the second digital selector is electrically connected with a summation output end of the last adder in the adders, a third input end of the second digital selector is electrically connected with an output end of the first digital selector, a first selection control end of the second digital selector is electrically connected with an output end of the timing stop processing module, and a second selection control end of the second digital selector is electrically connected with an output end of the synchronization module.

9. The time-to-digital conversion apparatus according to claim 7, wherein the fine timing control unit includes:

and a first input end of the third digital selector is connected with a high-potential signal, a second input end of the third digital selector is electrically connected with an output end of any adder in the adders, and a selection control end of the third digital selector is electrically connected with an output end of the timing stop processing module.

10. The time-to-digital conversion apparatus according to claim 8 or 9, wherein the fine timing latch unit includes:

the trigger ends of the fourth triggers are electrically connected with the output end of the synchronization module, the reset ends of the fourth triggers are all connected into the reset signal, the in-phase output ends of the fourth triggers are electrically connected with the fine timing latch unit, and the input end of the fourth trigger is electrically connected with the summation output end of the adder correspondingly.

11. The time-to-digital conversion apparatus of claim 8, wherein the fine timing module further comprises:

the counting unit is connected with the reset end of the counting unit in the reset signal, the clock end of the counting unit is electrically connected with the output end of any adder in the adders, and the output end of the counting unit is electrically connected with the calculating module and used for calculating the number of cycle periods of the potential signals transmitted in the adders.

12. The time-to-digital conversion apparatus according to claim 11, wherein the counting unit includes:

the reset end of the first counter is connected to the reset signal, the clock end of the first counter is electrically connected with the summation output end of any adder in the adders, and the output end of the first counter is electrically connected with the calculation module and used for counting according to the rising edge and the falling edge so as to calculate the number of cycle periods of the transmission of the potential signal in the adders.

13. The time-to-digital conversion apparatus according to claim 11, wherein the counting unit includes:

the reset end of the second counter is connected to the reset signal, the clock end of the second counter is electrically connected with the summation output end of any adder in the adders, and the output end of the second counter is electrically connected with the calculation module and is used for counting according to a rising edge so as to calculate the number of first cycle periods of the potential signal transmitted in the adders;

a reset end of the third counter is connected to the reset signal, a clock end of the third counter is electrically connected to a summation output end of any one of the adders, and an output end of the third counter is electrically connected to the calculation module and is used for counting according to the inverted rising edge to calculate the number of second cycle periods of the transmission of the potential signal in the adders;

the calculation module obtains the number of the cycle periods according to the sum of the first number of the cycle periods and the second number of the cycle periods.

14. The time-to-digital conversion apparatus of claim 9, wherein the fine timing module further comprises:

the counting unit is connected with the reset end of the counting unit in the reset signal, the clock end of the counting unit is electrically connected with the output end of any adder in the adders, the latch end of the counting unit is electrically connected with the output end of the synchronization module, and the output end of the counting unit is electrically connected with the computing module and used for computing the number of the cycle periods transmitted by the potential signals in the adders.

15. The time-to-digital conversion apparatus according to claim 14, wherein the counting unit comprises:

the reset end of the first counter is connected to the reset signal, the clock end of the first counter is electrically connected with the summation output end of any adder in the adders, the latch end of the first counter is electrically connected with the output end of the synchronization module, and the output end of the first counter is electrically connected with the calculation module and used for counting according to the rising edge and the falling edge so as to calculate the number of cycle periods of the potential signal transmitted in the adders.

16. The time-to-digital conversion apparatus according to claim 14, wherein the counting unit comprises:

the reset end of the second counter is connected to the reset signal, the clock end of the second counter is electrically connected with the summation output end of any adder in the adders, the latch end of the second counter is electrically connected with the output end of the synchronization module, and the output end of the second counter is electrically connected with the calculation module and is used for counting according to the rising edge to calculate the number of first cycle periods of the potential signal transmitted in the adders;

a reset end of the third counter is connected to the reset signal, a clock end of the third counter is electrically connected to a summation output end of any one of the adders, a latch end of the third counter is electrically connected to an output end of the synchronization module, and an output end of the third counter is electrically connected to the calculation module and is used for counting according to the inverted rising edge to calculate the number of second cycle periods of the transmission of the potential signal in the adders;

17. A method of time-to-digital conversion, comprising:

generating a timing stop mark signal according to a timing stop signal, a reset signal and a timing stop synchronizing signal, wherein the pulse starting time of the timing stop mark signal is the same as the pulse starting time of the timing stop signal;

generating the timing stop synchronization signal according to a clock signal, the reset signal and the timing stop flag signal;

starting coarse clocking in response to a pulse start time of a clocking start signal, one pulse start time of the clock signal, and stopping coarse clocking in response to a pulse start time of the clocking stop synchronization signal, another pulse start time of the clock signal, a coarse clocking result being obtained based on a clock number of the clock signal between the starting coarse clocking and the stopping coarse clocking;

starting fine clocking in response to a pulse start time of the clocking stop flag signal, stopping fine clocking in response to a pulse start time of the clocking stop synchronization signal, and obtaining a fine clocking result based on a clock number of the clock signal between the starting fine clocking and the stopping fine clocking; and

and determining the timing result of the time-to-digital conversion device according to the clock signal, the difference value of the coarse timing result and the fine timing result.

18. The time-to-digital conversion method according to claim 17, wherein the step of generating the timing stop flag signal based on the timing stop signal, the reset signal, and the timing stop synchronization signal includes:

constructing that the input end of a first trigger is connected with a high-potential signal and the trigger end of the first trigger is connected with the timing stop signal;

one input end of the structure OR gate is connected with the timing stop synchronous signal, the other input end of the structure OR gate is connected with the reset signal, and the output end of the structure OR gate is electrically connected with the reset end of the first trigger; and

and configuring a non-inverting output end of the first trigger to output the timing stop mark signal.

19. The time-to-digital conversion method according to claim 18, wherein the step of generating the timing stop synchronization signal based on the clock signal, the reset signal, and the timing stop flag signal includes:

the input end of a second trigger is electrically connected with the positive phase output end of the first trigger, the trigger end of the second trigger is connected with the clock signal, and the reset end of the second trigger is connected with the reset signal;

constructing an input end of a third trigger to be electrically connected with a normal phase output end of the second trigger, wherein a trigger end of the third trigger is connected to the clock signal, a reset end of the third trigger is connected to the reset signal, and a same phase output end of the third trigger is electrically connected with an input end of the OR gate; and

and configuring the in-phase output end of the third trigger to output the timing stop synchronization signal.