CN113810053B - Bypass window switching method applied to successive approximation type analog-to-digital converter - Google Patents

Bypass window switching method applied to successive approximation type analog-to-digital converter Download PDF

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CN113810053B
CN113810053B CN202111072372.1A CN202111072372A CN113810053B CN 113810053 B CN113810053 B CN 113810053B CN 202111072372 A CN202111072372 A CN 202111072372A CN 113810053 B CN113810053 B CN 113810053B
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capacitor array
capacitor
reference voltage
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CN113810053A (en
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吴建辉
周畅
黄琳琳
黄毅
罗斯婕
李红
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Southeast University
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Southeast University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
    • H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

The invention discloses a bypass window switching method applied to a successive approximation type analog-to-digital converter. The method comprises three stages of sampling, conversion and code spelling, wherein differential input voltages VIP and VIN are connected to a top plate of a capacitor array through a sampling switch, a comparator compares the voltages of the top plate of the capacitor array to obtain a corresponding digital code, and the connection of a bottom plate of the capacitor array is controlled according to the digital code; the invention firstly switches to generate a bypass window on the top polar plate of the capacitor, and N-bit digital codes are obtained after the code spelling by only N-2 times of comparison in the window, and N-bit digital codes are obtained after the code spelling by N+1 times of comparison outside the window. Compared with the traditional switching algorithm, the CDAC power consumption is reduced, the DAC power consumption is reduced in the window by the input voltage, half of the capacitance area is saved, and the energy efficiency and area compromise is realized.

Description

Bypass window switching method applied to successive approximation type analog-to-digital converter
Technical Field
The invention relates to a bypass window switching method applied to a successive approximation type analog-to-digital converter, and belongs to the technical field of capacitive digital-to-analog converters of the successive approximation type analog-to-digital converter.
Background
Sensors that can operate for a long period of time are required in the fields of the internet of things, wearable devices, etc., and the use of Analog-to-digital converter (ADC) by sensor interfaces is extremely frequent. Due to the requirements for lifetime, the ADC needs to achieve low power consumption. Successive approximation analog-to-digital converters (Successive approximation register analog-to-digital converter, SARADC) are widely used at low voltages due to their high degree of digitization and energy efficiency. The generally used SARADC architecture includes sampling switches, capacitive digital-to-analog converters (Capacitance digital to analog converter, CDAC), comparators, SAR logic, and output circuits, while at low speeds, the switching power consumption of the CDAC consumes a significant proportion of the overall power consumption.
In prior studies, various switching algorithms have been proposed to reduce the switching power consumption of CDAC. However, they introduce additional inter-stage errors [1] and multiple comparators [2] while reducing switching power consumption, and ultimately, either the reduction in digital-to-analog converter (Digital to analog converter, DAC) power consumption is not ideal or higher requirements are placed on the design criteria of other modules, such as comparators.
[1]H.-Y.Tai,Y.-S.Hu,H.-W.Chen,and H.-S.Chen,“A 0.85fJ/conversion step 10b 200kS/s subranging SAR ADC in 40nmCMOS,”in IEEE ISSCC Dig.Tech.Papers,Feb.2014,pp.196–197.
[2]G.-Y.Huang,S.-J.Chang,C.-C.Liu,and Y.-Z.Lin,“A1-μW 10-bit 200-kS/s SAR ADC with a bypass window for biomedical applications,”in IEEE J.Solid-State Circuits,vol.47,no.11,pp.2783–2795,Nov.2012.
Disclosure of Invention
The invention aims to: in order to solve the compromise of how to realize lower power consumption and introduce additional errors in the design of SAR ADC, the invention provides a bypass window switching method applied to a successive approximation type analog-to-digital converter, wherein the first switching can generate + -2 on a capacitance top polar plate by using capacitance switching -3 The voltage change of Vref judges whether the input voltage is in a window, if so, the previous two times of high-order capacitance switching are skipped, the conversion period of the SAR ADC is shortened, and the power consumption is reduced; if the switching capacitor is out of the window, the switching capacitor is continuously compared according to the digital code, and continuous capacitor switching back is avoided through the spelling code, so that power consumption is reduced.
The technical scheme is as follows: in order to achieve the above object, the invention provides a bypass window switching method applied to a successive approximation analog-to-digital converter, wherein the analog-to-digital converter comprises a sampling switch, a capacitor array, a comparator, a digital control logic circuit and a code spelling device, wherein the capacitor array comprises an upper capacitor array and a lower capacitor array which have identical structures; the differential input voltage, namely the positive input voltage and the negative input voltage, are respectively connected to the top electrode plates of the upper capacitor array and the lower capacitor array through sampling switches; the top polar plate of the upper capacitor array is connected with the non-inverting input end of the comparator, and the top polar plate of the lower capacitor array is connected with the inverting input end of the comparator; the differential output end of the comparator is connected to the digital control logic circuit, the digital control logic circuit generates control signals to control the bottom polar plates of the upper capacitor array and the lower capacitor array to be connected to corresponding levels, and the code spelling device spells each digital code output by the digital control logic circuit to generate converted digital codes;
The upper capacitor array comprises a first upper sub-capacitor array, a second upper sub-capacitor array and a second upper sub-capacitor array; the lower capacitor array comprises a first lower sub-capacitor array, a second lower sub-capacitor array and a second lower sub-capacitor array;
the bypass window switching method applied to the successive approximation type analog-to-digital converter comprises the following steps of:
step A, sampling:
all capacitance bottom plates of a first upper sub-capacitance array and a second upper sub-capacitance array of the upper capacitance array are connected to a ground level, and all capacitance bottom plates of the second upper sub-capacitance array are connected to a reference voltage; all capacitance bottom plates of a first lower sub-capacitance array and a second lower sub-capacitance array of the lower capacitance array are connected to the ground level, and all capacitance bottom plates of the second lower sub-capacitance array are connected to the reference voltage;
step B, a conversion stage:
step B1, disconnecting the sampling switch, and then directly comparing the most significant bit of the positive input voltage and the negative input voltage of the top plates of the upper capacitor array and the lower capacitor array by the comparator to obtain a digital code D N Wherein N represents the bit number of the analog-to-digital converter, and the digital control logic circuit is used for controlling the digital control logic circuit according to the digital code D N Controlling the connection position of the bottom electrode plates of the capacitors in the upper capacitor array and the lower capacitor array;
step B2, the comparator obtains a digital code D by comparing the voltages of the top electrode plates of the upper capacitor array and the lower capacitor array obtained in the step B1 WIN According to the digital code D N And D WIN Judging whether the differential input voltage is in the bypass window or not, thereby controlling the connection of the capacitor bottom plates in the upper capacitor array and the lower capacitor arrayA location;
step B3, the comparator obtains a digital code D in the bypass window by comparing the voltages of the top electrode plates of the upper capacitor array and the lower capacitor array obtained in the step B2 N-4 According to digital code D within a bypass window N 、D WIN And D N-4 Controlling the connection position of the bottom electrode plates of the capacitors in the upper capacitor array and the lower capacitor array; obtaining digital codes D outside the bypass window N-1 According to digital code D outside the bypass window N 、D WIN And D N-1 Controlling the connection position of the bottom electrode plates of the capacitors in the upper capacitor array and the lower capacitor array;
step B4, the comparator obtains a digital code D in the bypass window by comparing the voltages of the top electrode plates of the upper capacitor array and the lower capacitor array obtained in the step B3 N-5 According to the digital code D in the bypass window N 、D WIN 、D N-4 And D N-5 Controlling the connection position of the bottom electrode plates of the capacitors in the upper capacitor array and the lower capacitor array; deriving digital codes D outside the bypass window N-2 According to digital code D outside the bypass window N 、D WIN 、D N-1 And D N-2 Controlling the connection position of the bottom electrode plates of the capacitors in the upper capacitor array and the lower capacitor array;
step B5, the comparator obtains a digital code D in the bypass window by comparing the voltages of the top electrode plates of the upper capacitor array and the lower capacitor array obtained in the step B4 N-Kiw-1 Wherein K is iw For the number of steps of conversion in the window, K is 5.ltoreq.K iw N-3 is less than or equal to the numerical code D N-Kiw-1 Controlling the connection position of the bottom electrode plates of the capacitors in the upper capacitor array and the lower capacitor array; and repeating the operation in the bypass window in the step B5 until the digital code D is obtained 1 The method comprises the steps of carrying out a first treatment on the surface of the Outside the bypass window, two limit cases, D N D WIN D N-1 D N-2 =0000 or 1111, the digital code D will be skipped N-Kow1+2 Obtaining the digital code D N-Kow1+1 ，K ow1 For the number of steps of conversion under the limit condition outside the bypass window, K is more than or equal to 5 ow1 N-1 is less than or equal to, according to digital code D N-Kow1+1 Control the connection position of the bottom electrode plate of the capacitor in the upper capacitor array and the lower capacitor arraySetting and repeating the operation of the step B5 outside the bypass window until the digital code D is obtained 1 The method comprises the steps of carrying out a first treatment on the surface of the Other non-limiting conditions, digital codes D are obtained N-Kow2+2 ，K ow2 For the number of steps of conversion under non-limiting conditions outside the bypass window, K is more than or equal to 5 ow2 N is less than or equal to D according to digital code N-Kow2+2 Controlling the connection position of the bottom electrode plates of the capacitors in the upper capacitor array and the lower capacitor array, and repeating the operation of the step B5 outside the bypass window until the digital code D is obtained 1 ；
Step C, code spelling stage:
the digital control logic circuit outputs the digital codes of the comparator to the code spelling device, and the code spelling device carries out code spelling on each digital code to obtain the converted N-bit digital codes.
Wherein, the liquid crystal display device comprises a liquid crystal display device,
the second upper sub-capacitor array and the second upper sub-capacitor array are split capacitor arrays with high four-bit capacitor, wherein the capacitance value of the second upper most-bit capacitor is 2 N-3 C, the capacitance value of the last high-order capacitor of the second capacitor is 2 N- 4 C, the capacitance value of the last low-order capacitor of the second capacitor is 2 N-5 C, the capacitance value of the second upper lowest-order capacitor is 2 N-6 C, wherein N represents the number of bits of the analog-to-digital converter, and C is a unit capacitance value; the first upper sub-capacitor array is a low-order capacitor, wherein the first upper N-9-order capacitor is a virtual capacitor, the capacitance value is 1C, and the capacitance value of the first upper N-4-order capacitor is 2 N-6 C, the capacitance value of the first upper N-5 bit capacitor is 2 N-7 C, the capacitance value of the first upper N-6 bit capacitor is 2 N-8 C, the capacitance value of the first upper N-7 bit capacitor is 2 N-9 And C, the capacitance value of the first upper N-8 bit capacitor is 1C.
The digital control logic circuit in step B1 is used for controlling the digital code D N The connection position of the bottom electrode plates of the capacitors in the upper capacitor array and the lower capacitor array is controlled, and the method specifically comprises the following steps:
Case one: if D N The second upper low-order capacitor bottom plate is connected to the ground level by the reference voltage, the second lower low-order capacitor bottom plate is connected to the reference voltage by the ground level, and the differential power is provided on the capacitor array top platePressure reduction 2 (-3) V ref Forming a 0-2 (-3) V ref Wherein V is ref Is the reference voltage;
and a second case: if D N The second last low-order capacitance bottom plate is connected to the reference voltage by the ground level, the second last low-order capacitance bottom plate is connected to the ground level by the reference voltage, and the differential voltage on the capacitance array top plate is increased by 2 (-3) V ref Forming a 0 to-2 (-3) V ref Is provided.
Step B2 is described according to the digital code D N And D WIN Judging whether the differential input voltage is in the bypass window or not, thereby controlling the connection position of the capacitor bottom polar plates in the upper capacitor array and the lower capacitor array, and specifically comprising:
case one: if D N D WIN =11, explaining that the differential input voltage is in the bypass window 0-2 (-3) V ref In addition, the second upper highest capacitance bottom electrode plate is connected to the ground level by the reference voltage, the second lower highest capacitance bottom electrode plate is connected to the reference voltage by the ground level, and the differential voltage on the capacitance array top electrode plate is reduced by 2 (-1) V ref ；
And a second case: if D N D WIN =10, explaining that the differential input voltage is within the bypass window 0-2 (-3) V ref Within, skip the digital code D N-1 、D N-2 The second upper lowest capacitance bottom plate is connected to the reference voltage by the ground level, the second lower lowest capacitance bottom plate is connected to the ground level by the reference voltage, and the differential voltage on the capacitance array top plate is increased by 2 (-4) V ref ；
And a third case: if D N D WIN =01, explaining that the differential input voltage is in the bypass window 0 to-2 (-3) V ref Within, skip the digital code D N-1 、D N-2 The second upper lowest-order capacitance bottom electrode plate is connected to the ground level by the reference voltage, the second lower lowest-order capacitance bottom electrode plate is connected to the reference voltage by the ground level, and the differential voltage on the capacitance array top electrode plate is reduced by 2 (-4) V ref ；
Case four: if D N D WIN =00, illustrating that the differential input voltage is at bypass windows 0 to-2 (-3) V ref In addition, the second upper highest capacitance bottom plate is connected to the reference voltage by the ground level, the second lower highest capacitance bottom plate is connected to the ground level by the reference voltage, and the differential voltage on the capacitance array top plate is increased by 2 (-1) V ref 。
Step B3, according to the digital code D within the bypass window N 、D WIN And D N-4 The connection position of the bottom electrode plates of the capacitors in the upper capacitor array and the lower capacitor array is controlled, specifically:
case one: if D N D WIN D N-4 =101, the first lower N-4 bit capacitor bottom plate is connected to the reference voltage from ground, the differential voltage on the capacitor array top plate is reduced by 2 (-5) V ref ；
And a second case: if D N D WIN D N-4 The first upper N-4 bit capacitor bottom plate is connected to the reference voltage from ground, the differential voltage on the capacitor array top plate increases by 2 =100 (-5) V ref ；
And a third case: if D N D WIN D N-4 011, the first lower N-4 bit capacitor bottom plate is connected to the reference voltage by ground level, the differential voltage on the capacitor array top plate is reduced by 2 (-5) V ref ；
Case four: if D N D WIN D N-4 =010, the first upper N-4 bit capacitor bottom plate is connected to the reference voltage by ground level, the differential voltage on the capacitor array top plate increases by 2 (-5) V ref ；
Step B3, according to the digital code D outside the bypass window N 、D WIN And D N-1 The connection position of the bottom electrode plates of the capacitors in the upper capacitor array and the lower capacitor array is controlled, specifically:
case five: if D N D WIN D N-1 The second upper capacitor bottom plate is connected to ground level by reference voltage, the second lower upper capacitor bottom plate is connected to ground level by reference voltageThe bottom electrode plate of the capacitor is connected to the reference voltage by the ground level, and the differential voltage on the top electrode plate of the capacitor array is reduced by 2 (-2) V ref ；
Case six: if D N D WIN D N-1 The second upper capacitor bottom plate is connected to the reference voltage by the ground level, the second lower capacitor bottom plate is connected to the ground level by the reference voltage, and the differential voltage on the capacitor array top plate is increased by 2 =110 (-2) V ref ；
Case seven: if D N D WIN D N-1 The second upper capacitor bottom plate is connected to ground by a reference voltage, the second lower capacitor bottom plate is connected to reference voltage by ground, and the differential voltage on the capacitor array top plate is reduced by 2 =001 (-2) V ref ；
Case eight: if D N D WIN D N-1 The second upper capacitor bottom plate is connected to the reference voltage by the ground level, the second lower capacitor bottom plate is connected to the ground level by the reference voltage, and the differential voltage on the capacitor array top plate is increased by 2 (-2) V ref 。
Step B4, according to the digital code D in the bypass window N 、D WIN 、D N-4 And D N-5 The connection position of the bottom electrode plates of the capacitors in the upper capacitor array and the lower capacitor array is controlled, and the method specifically comprises the following steps:
case one: if D N D WIN D N-4 D N-5 =1011, the first lower N-5 bit capacitor bottom plate is connected to the reference voltage from ground, the differential voltage on the capacitor array top plate is reduced by 2 (-6) V ref ；
And a second case: if D N D WIN D N-4 D N-5 The first upper N-5 bit capacitor bottom plate is connected to the reference voltage from ground, the differential voltage on the capacitor array top plate increases by 2 =1010 (-6) V ref ；
And a third case: if D N D WIN D N-4 D N-5 =1001, first N-5 bit capacitor bottom plate is groundedLevel-connected to reference voltage, differential voltage on top plate of capacitor array is reduced by 2 (-6) V ref ；
Case four: if D N D WIN D N-4 D N-5 The first upper N-5 bit capacitor bottom plate is connected to the reference voltage by ground, the differential voltage on the capacitor array top plate increases by 2 =1000 (-6) V ref ；
Case five: if D N D WIN D N-4 D N-5 The first lower N-5 bit capacitor bottom plate is connected to the reference voltage from ground, the differential voltage on the capacitor array top plate is reduced by 2 =0111 (-6) V ref ；
Case six: if D N D WIN D N-4 D N-5 The first upper N-5 bit capacitor bottom plate is connected to the reference voltage from ground, the differential voltage on the capacitor array top plate increases by 2 =0110 (-6) V ref ；
Case seven: if D N D WIN D N-4 D N-5 =0101, the first lower N-5 bit capacitor bottom plate is connected to the reference voltage from ground, the differential voltage on the capacitor array top plate is reduced by 2 (-6) V ref ；
Case eight: if D N D WIN D N-4 D N-5 The first upper N-5 bit capacitor bottom plate is connected to the reference voltage from ground level, the differential voltage on the capacitor array top plate increases by 2 =0100 (-6) V ref ；
Step B4, according to the digital code D outside the bypass window N 、D WIN 、D N-1 And D N-2 The connection position of the bottom electrode plates of the capacitors in the upper capacitor array and the lower capacitor array is controlled, and the method specifically comprises the following steps:
case nine: if D N D WIN D N-1 D N-2 =1111, skip D N-3 The second upper lowest-order capacitance bottom electrode plate is connected to the ground level by the reference voltage, the second lower lowest-order capacitance bottom electrode plate is connected to the reference voltage by the ground level, and the differential voltage on the capacitance array top electrode plate is reduced by 2 (-4) V ref ；
Case ten: if D N D WIN D N-1 D N-2 The second upper low-order capacitor bottom plate is connected to the reference voltage by the ground level, the second lower low-order capacitor bottom plate is connected to the ground level by the reference voltage, and the differential voltage on the capacitor array top plate is increased by 2 =1110 (-3) V ref ；
Case eleven: if D N D WIN D N-1 D N-2 =1101, the second next higher capacitor bottom plate is connected to the reference voltage from ground, the differential voltage on the capacitor array top plate is reduced by 2 (-3) V ref ；
Twelve cases: if D N D WIN D N-1 D N-2 The second upper low-order capacitor bottom plate is connected to the reference voltage by the ground level, the second lower low-order capacitor bottom plate is connected to the ground level by the reference voltage, and the differential voltage on the capacitor array top plate is increased by 2 =1100 (-3) V ref ；
Thirteen cases: if D N D WIN D N-1 D N-2 0011, the second last low-order bottom plate is connected to ground by a reference voltage, the second next high-order bottom plate is connected to reference voltage by ground, and the differential voltage on the top plate of the capacitor array is reduced by 2 (-3) V ref ；
Fourteen cases: if D N D WIN D N-1 D N-2 0010, the second upper capacitor bottom plate is connected to the reference voltage by the ground level, the differential voltage on the capacitor array top plate increases by 2 (-3) V ref ；
Fifteen cases: if D N D WIN D N-1 D N-2 The second last low-order capacitor bottom plate is connected to ground by a reference voltage, the second last low-order capacitor bottom plate is connected to reference voltage by ground, and the differential voltage on the capacitor array top plate is reduced by 2 =0001 (-3) V ref ；
Sixteen cases: if D N D WIN D N-1 D N-2 =0000, skip D N-3 The second upper lowest capacitance bottom plate is connected to the reference voltage by the ground level, the second lower lowest capacitance bottom plate is connected to the ground level by the reference voltage, and the differential voltage on the capacitance array top plate is increased by 2 (-4) V ref 。
Step B5 is described according to the digital code D N-Kiw-1 The connection position of the bottom electrode plates of the capacitors in the upper capacitor array and the lower capacitor array is controlled, specifically:
case one: voltage within bypass window, D N-Kiw-1 When=1, the first lower N-K iw The bottom polar plate of the-1-bit capacitor is connected to the reference voltage by the ground level, and K is more than or equal to 5 iw N-3, differential voltage on the top plate of the capacitor array is reduced by 2 (-Kiw-2) V ref The method comprises the steps of carrying out a first treatment on the surface of the Otherwise, D N-Kiw-1 When=0, the first upper N-K iw The 1-bit capacitor bottom plate is connected to the reference voltage from the ground level, the differential voltage on the capacitor array top plate increases by 2 (-Kiw-2) V ref ；
Step B5 is described according to the digital code D N-Kow1+1 The connection position of the bottom electrode plates of the capacitors in the upper capacitor array and the lower capacitor array is controlled, specifically:
and a second case: the voltage outside the bypass window, the limit case including D N D WIN D N-1 D N-2 =0000 or 1111, d N-Kow1+1 When=1, the first lower N-K ow1 The +1 bit capacitance bottom polar plate is connected to the reference voltage by the ground level, and K is more than or equal to 5 ow1 N-1, differential voltage on top plate of capacitor array is reduced by 2 (-Kow1) V ref The method comprises the steps of carrying out a first treatment on the surface of the Otherwise, D N-Kow1+1 When=0, the first upper N-K ow1 The +1 bit capacitor bottom plate is connected to the reference voltage by the ground level, the differential voltage on the capacitor array top plate increases by 2 (-Kow1) V ref ；
Step B5 is described according to the digital code D N-Kow2+2 The connection position of the bottom electrode plates of the capacitors in the upper capacitor array and the lower capacitor array is controlled, specifically:
And a third case: voltage outside the bypass window, not limited, D N-Kow2+2 When=1, K ow2 =5, secondThe bottom electrode plate of the second upper lowest-order capacitor is connected to the ground level by a reference voltage, the bottom electrode plate of the second lower lowest-order capacitor is connected to the reference voltage by the ground level, and the differential voltage on the top electrode plate of the capacitor array is reduced by 2 (-Kow2+1) V ref The method comprises the steps of carrying out a first treatment on the surface of the When 6 is less than or equal to K ow2 N is less than or equal to N, the first N-K ow2 The +2 bit capacitor bottom plate is connected to the reference voltage by the ground level, the differential voltage on the capacitor array top plate is reduced by 2 (-Kow2+1) V ref The method comprises the steps of carrying out a first treatment on the surface of the Otherwise, D N-Kow2+2 When=0, K ow2 When=5, the second upper lowest capacitance bottom plate is connected to the reference voltage from the ground level, the second lower lowest capacitance bottom plate is connected to the ground level from the reference voltage, and the differential voltage on the capacitance array top plate is increased by 2 (-Kow2+1) V ref The method comprises the steps of carrying out a first treatment on the surface of the When 6 is less than or equal to K ow2 N is less than or equal to N, N-K is on the first ow2 The +2 bit capacitor bottom plate is connected to the reference voltage by the ground level, the differential voltage on the capacitor array top plate increases by 2 (-Kow2+1) V ref 。
And C, the spelling device carries out spelling on each digital code to obtain converted N-bit digital codes, which comprises the following specific steps:
case one: at-2 (-3) V ref 2～2 (-3) V ref Inside the bypass window, let D N-1 ＝D WIN 、D N-2 ＝D WIN And D N-3 ＝D WIN The code spelling device outputs the converted N-bit digital code;
and a second case: outside the bypass window, if under limit conditions D N D WIN D N-1 D N-2 =1111 or 0000, let D N-3 ＝D WIN The code spelling device outputs the converted N-bit digital code;
and a third case: outside the bypass window, if not limited, D N When=1, the corresponding digital code D N-3 D is added at the position WIN The value of (2) is calculated by carry, and the code spelling device outputs the converted N-bit digital code; d (D) N When=0, the corresponding digital code D N-3 To subtract D WIN And there is borrowing calculation, the spelling device outputs the converted N-bit digital code.
The beneficial effects are that: by adopting the technical scheme, the invention has the following beneficial effects:
the invention firstly switches to generate + -2 on the top polar plate of the capacitor -3 Voltage variation of Vref, generating a + -2 -3 Vref window, thus judge whether the differential input voltage is within window, can skip the conversion step of the most significant bit (most significant bit, MSB), MSB-1 in window, save a large amount of power consumption; compared with the traditional switching algorithm, the method provided by the invention has the advantages that the DAC power consumption is reduced by 87.29% on average, the DAC power consumption of the input voltage in a window can be reduced by 95.56%, the capacitance area is saved by 50%, and the energy efficiency and area compromise is realized.
Drawings
FIG. 1 is a schematic diagram of the structure of SARADC employed in the method of the present invention to achieve 10-bit resolution;
FIG. 2 is a schematic diagram of the switching of the method of the present invention applied to 6-bit SARADC, and FIG. 2 (a) is a schematic diagram of the switching of steps B1 to B3 and D 6 D WIN D 5 In the case of =111, the switching from B4 to step B5 is schematically indicated as D in fig. 2 (B) 6 D WIN D 5 ＝110、D 6 D WIN D 2 ＝101、D 6 D WIN D 2 Switch switching schematic of B4 to step B5 in case of =100;
fig. 3 is a graph of MATLAB simulation results of the method of the present invention applied to 10-bit sar ADC for switching energy consumption as a function of ADC input signal.
The drawings are as follows: a sampling switch 1, a capacitor array 2, a comparator 3, a digital control logic circuit 4, a code spelling device 5, an upper capacitor array 2-1, a lower capacitor array 2-2, a first upper sub-capacitor array DAC P1 Second one of the upper sub-capacitor array DACs P2a Second and second upper sub-capacitor array DAC P2b The method comprises the steps of carrying out a first treatment on the surface of the First sub-capacitor array DAC N1 Second one of its capacitor array DACs N2a Second two-second-lower sub-capacitor array DAC N2b ；
Second one of the upper most significant capacitors C N,pa A second last high-order capacitor C N-1,pa Second last low-order capacitor C N-2,pa A second one of the upper minimum capacitors C N-3,pa The method comprises the steps of carrying out a first treatment on the surface of the Second oneThe highest capacitance C on two N,pb Second and last high-order capacitor C N-1,pb Second and last low-order capacitor C N-2,pb Second upper least significant capacitor C N-3,pb ；
Second one of the lower most significant capacitors C N,na The second next higher capacitor C N-1,na Second lower capacitor C N-2,na Second one of the lower-most capacitors C N-3,na The method comprises the steps of carrying out a first treatment on the surface of the Second two lower most significant capacitors C N,nb Second, its next high-order capacitance C N-1,nb Second, second next lower capacitor C N-2,nb Second two lower minimum capacitors C N-3,nb ；
First upper N-4 bit capacitor C N-4,p First upper N-5 bit capacitor C N-5,p First upper N-6 bit capacitor C N-6,p First upper N-7 bit capacitor C N-7,p First upper N-8 bit capacitor C N-8,p First upper N-9 th bit capacitor C N-9,p ；
First lower N-4 bit capacitor C N-4,n First N-5 bit capacitor C N-5,n First N-6 bit capacitor C N-6,n First N-7 bit capacitor C N-7,n First lower N-8 bit capacitor C N-8,n First N-9 bit capacitor C N-9,n 。
Detailed Description
Embodiments of the present invention will be described below with reference to the drawings.
The invention relates to a bypass window switching method applied to a successive approximation type analog-to-digital converter, which comprises a sampling switch 1, a capacitor array 2, a comparator 3, a digital control logic circuit 4 and a code spelling device 5, wherein the capacitor array 2 comprises an upper capacitor array 2-1 and a lower capacitor array 2-2 which have identical structures; the differential input voltage, namely the positive input voltage VIP and the negative input voltage VIN, are respectively connected to the top electrode plates of the upper capacitor array 2-1 and the lower capacitor array 2-2 through the sampling switch 1; the top polar plate of the upper capacitor array 2-1 is connected with the non-inverting input end of the comparator 3, and the top polar plate of the lower capacitor array 2-2 is connected with the inverting input end of the comparator 3; the differential output end of the comparator 3 is connected to the digital control logic circuit 4, the digital control logic circuit 4 generates control signals to control the bottom polar plates of the upper capacitor array 2-1 and the lower capacitor array 2-2 to be connected to corresponding levels, and the code spelling device 5 carries out code spelling on each digital code output by the digital control logic circuit 4 to generate converted digital codes.
The upper capacitor array 2-1 includes a first upper sub-capacitor array DAC P1 Second one of the upper sub-capacitor array DACs P2a And a second sub-capacitor array DAC P2b The method comprises the steps of carrying out a first treatment on the surface of the The lower capacitor array 2-2 includes a first lower capacitor array DAC N1 Second one of its capacitor array DACs N2a And a second sub-capacitor array DAC N2b 。
Second one of the upper sub-capacitor array DACs P2a And a second sub-capacitor array DAC P2b Is a split capacitor array of high four-bit capacitors, wherein the second highest bit capacitor C N,pa Has a capacitance value of 2 N-3 C, the last high-order capacitor C of the second N-1,pa Has a capacitance value of 2 N-4 C, the last low-order capacitor C of the second N-2,pa Has a capacitance value of 2 N-5 C, the second upper lowest capacitance C N-3,pa Has a capacitance value of 2 N-6 C, wherein N represents the number of bits of the analog-to-digital converter, and C is a unit capacitance value; first upper sub-capacitor array DAC P1 Is a low-order capacitor, wherein the first upper N-9-order capacitor C N-9,p For the virtual dummy capacitor, the capacitance value is 1C, the first upper N-4 bit capacitor C N-4,p Has a capacitance value of 2 N-6 C, the first upper N-5 bit capacitor C N-5,p Has a capacitance value of 2 N-7 C, the first upper N-6 bit capacitor C N-6,p Capacitance value of 2 N-8 C, the first upper N-7 bit capacitor C N-7,p The capacitance value of (2) N-9 C, the first upper N-8 bit capacitor C N-8,p The capacitance value of (2) is 1C. Analog to digital converter number n=10.
A bypass window switching method applied to a successive approximation type analog-to-digital converter comprises the following steps:
Step A, sampling:
first upper sub-capacitor array DAC of upper capacitor array 2-1 P1 And a second one of the sub-capacitor array DACs P2a Is connected to all capacitance bottom plates ofGround level gnd, second upper two sub-capacitor array DAC P2b Is connected to the reference voltage V ref The method comprises the steps of carrying out a first treatment on the surface of the First lower capacitor array DAC of lower capacitor array 2-2 N1 And a second one of its lower capacitor array DACs N2a Is connected to ground level gnd, second two lower sub-capacitor array DAC N2b Is connected to the reference voltage V ref ；
Step B, a conversion stage:
step B1, the sampling switch 1 is turned off, and then the comparator 3 directly compares the most significant bit of the positive input voltage VIP and the negative input voltage VIN of the top plates of the upper capacitor array 2-1 and the lower capacitor array 2-2 to obtain a digital code D N Where N represents the number of analog-to-digital converter bits, and the digital control logic circuit 4 is configured to control the digital code D N Controlling the connection positions of the bottom electrode plates of the capacitors in the upper capacitor array 2-1 and the lower capacitor array 2-2; the method specifically comprises the following steps:
case one: if D N =1, the second and last low capacitance C N-2,pb The bottom polar plate is formed by reference voltage V ref Connected to ground level gnd, the second lower capacitor C N-2,na The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage reduction 2 on top plate of capacitor array 2 (-3) V ref Forming a 0-2 (-3) V ref Wherein V is ref Is the reference voltage;
and a second case: if D N =0, the last low capacitance C of the second one N-2,pa The bottom plate is connected to the reference voltage V by the ground level gnd ref Second, second next lower capacitor C N-2,nb The bottom polar plate is formed by reference voltage V ref Connected to ground gnd, the differential voltage on the top plate of capacitor array 2 increases by 2 (-3) V ref Forming a 0 to-2 (-3) V ref Is provided.
Step B2, the comparator 3 obtains a digital code D by comparing the voltages of the top electrode plates of the upper capacitor array 2-1 and the lower capacitor array 2-2 obtained in the step B1 WIN According to the digital code D N And D WIN Judging whether the differential input voltage is in a bypass window or not, so as to control the connection position of the bottom electrode plates of the capacitors in the upper capacitor array 2-1 and the lower capacitor array 2-2; the method comprises the following steps:
case one: if D N D WIN =11, explaining that the differential input voltage is in the bypass window 0-2 (-3) V ref In addition, the second upper most significant capacitor C N,pb The bottom polar plate is formed by reference voltage V ref Connected to ground level gnd, the second lower most significant capacitor C N,na The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage reduction 2 on top plate of capacitor array 2 (-1) V ref ；
And a second case: if D N D WIN =10, explaining that the differential input voltage is within the bypass window 0-2 (-3) V ref Within, skip the digital code D N-1 、D N-2 A second one of the upper minimum capacitors C N-3,pa The bottom plate is connected to the reference voltage V by the ground level gnd ref Second two lower minimum capacitors C N-3,nb The bottom polar plate is formed by reference voltage V ref Connected to ground gnd, the differential voltage on the top plate of capacitor array 2 increases by 2 (-4) V ref ；
And a third case: if D N D WIN =01, explaining that the differential input voltage is in the bypass window 0 to-2 (-3) V ref Within, skip the digital code D N-1 、D N-2 Second upper least significant capacitor C N-3,pb The bottom polar plate is formed by reference voltage V ref Connected to ground level gnd, the second lower-most capacitor C N-3,na The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage reduction 2 on top plate of capacitor array 2 (-4) V ref ；
Case four: if D N D WIN =00, illustrating that the differential input voltage is at bypass windows 0 to-2 (-3) V ref In addition, the second highest capacitance C N,pa The bottom plate is connected to the reference voltage V by the ground level gnd ref Second two lower most significant capacitors C N,nb The bottom polar plate is formed by reference voltage V ref Connected to ground levelgnd, differential voltage on top plate of capacitor array 2 increases by 2 (-1) V ref 。
Step B3, the comparator 3 obtains the digital code D in the bypass window by comparing the voltages of the top electrode plates of the upper capacitor array 2-1 and the lower capacitor array 2-2 obtained in step B2 N-4 According to digital code D within a bypass window N 、D WIN And D N-4 Controlling the connection positions of the bottom electrode plates of the capacitors in the upper capacitor array 2-1 and the lower capacitor array 2-2; the method comprises the following steps:
case one: if D N D WIN D N-4 =101, first N-4 bit capacitor C N-4,n The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage reduction 2 on top plate of capacitor array 2 (-5) V ref ；
And a second case: if D N D WIN D N-4 =100, the first upper N-4 bit capacitor C N-4,p The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage on top plate of capacitor array 2 increases by 2 (-5) V ref ；
And a third case: if D N D WIN D N-4 =011, first N-4 bit capacitor C N-4,n The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage reduction 2 on top plate of capacitor array 2 (-5) V ref ；
Case four: if D N D WIN D N-4 =010, first upper N-4 bit capacitor C N-4,p The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage on top plate of capacitor array 2 increases by 2 (-5) V ref ；
Obtaining digital codes D outside the bypass window N-1 According to digital code D outside the bypass window N 、D WIN And D N-1 Controlling the connection positions of the bottom electrode plates of the capacitors in the upper capacitor array 2-1 and the lower capacitor array 2-2; the method comprises the following steps:
case five: if D N D WIN D N-1 =111, the second and last higher capacitor C N-1,pb The bottom polar plate is formed by reference voltage V ref Connected to ground level gnd, the second next higher capacitor C N-1,na The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage reduction 2 on top plate of capacitor array 2 (-2) V ref ；
Case six: if D N D WIN D N-1 =110, the second last higher capacitor C N-1,pa The bottom plate is connected to the reference voltage V by the ground level gnd ref Second, its next high-order capacitance C N-1,nb The bottom polar plate is formed by reference voltage V ref Connected to ground gnd, the differential voltage on the top plate of capacitor array 2 increases by 2 (-2) V ref ；
Case seven: if D N D WIN D N-1 =001, the second and last higher capacitor C N-1,pb The bottom polar plate is formed by reference voltage V ref Connected to ground level gnd, the second next higher capacitor C N-1,na The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage reduction 2 on top plate of capacitor array 2 (-2) V ref ；
Case eight: if D N D WIN D N-1 =000, the second last higher capacitor C N-1,pa The bottom plate is connected to the reference voltage V by the ground level gnd ref Second, its next high-order capacitance C N-1,nb The bottom polar plate is formed by reference voltage V ref Connected to ground gnd, the differential voltage on the top plate of capacitor array 2 increases by 2 (-2) V ref 。
Step B4, the comparator 3 obtains the digital code D in the bypass window by comparing the voltages of the top electrode plates of the upper capacitor array 2-1 and the lower capacitor array 2-2 obtained in step B3 N-5 According to the digital code D in the bypass window N 、D WIN 、D N-4 And D N-5 Controlling the connection positions of the bottom electrode plates of the capacitors in the upper capacitor array 2-1 and the lower capacitor array 2-2; the method specifically comprises the following steps:
Case one: if D N D WIN D N-4 D N-5 =1011, first N-5 bit capacitor C N-5,n The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage reduction 2 on top plate of capacitor array 2 (-6) V ref ；
And a second case: if D N D WIN D N-4 D N-5 =1010, the first upper N-5 bit capacitor C N-5,p The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage on top plate of capacitor array 2 increases by 2 (-6) V ref ；
And a third case: if D N D WIN D N-4 D N-5 =1001, first N-5 bit capacitor C N-5,n The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage reduction 2 on top plate of capacitor array 2 (-6) V ref ；
Case four: if D N D WIN D N-4 D N-5 =1000, the first upper N-5 bit capacitor C N-5,p The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage on top plate of capacitor array 2 increases by 2 (-6) V ref ；
Case five: if D N D WIN D N-4 D N-5 =0111, first N-5 bit capacitor C N-5,n The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage reduction 2 on top plate of capacitor array 2 (-6) V ref ；
Case six: if D N D WIN D N-4 D N-5 =0110, the first upper N-5 bit capacitor C N-5,p The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage on top plate of capacitor array 2 increases by 2 (-6) V ref ；
Case seven: if D N D WIN D N-4 D N-5 =0101, first N-5 bit capacitor C N-5,n The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage reduction 2 on top plate of capacitor array 2 (-6) V ref ；
Case eight: if D N D WIN D N-4 D N-5 =0100, the first upper N-5 bit capacitor C N-5,p The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage on top plate of capacitor array 2 increases by 2 (-6) V ref ；
Deriving digital codes D outside the bypass window N-2 According to digital code D outside the bypass window N 、D WIN 、D N-1 And D N-2 Controlling the connection positions of the bottom electrode plates of the capacitors in the upper capacitor array 2-1 and the lower capacitor array 2-2; the method comprises the following steps:
case nine: if D N D WIN D N-1 D N-2 =1111, skip D N-3 Second upper least significant capacitor C N-3,pb The bottom polar plate is formed by reference voltage V ref Connected to ground level gnd, the second lower-most capacitor C N-3,na The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage reduction 2 on top plate of capacitor array 2 (-4) V ref ；
Case ten: if D N D WIN D N-1 D N-2 =1110, the second and last low capacitance C N-2,pb The bottom plate is connected to the reference voltage V by the ground level gnd ref Second lower capacitor C N-2,na The bottom polar plate is formed by reference voltage V ref Connected to ground gnd, the differential voltage on the top plate of capacitor array 2 increases by 2 (-3) V ref ；
Case eleven: if D N D WIN D N-1 D N-2 =1101, the second next higher capacitor C N-1,nb The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage reduction 2 on top plate of capacitor array 2 (-3) V ref ；
Twelve cases: if D N D WIN D N-1 D N-2 =1100, the second and last low capacitance C N-2,pb The bottom plate is connected to the reference voltage V by the ground level gnd ref Second lower capacitor C N-2,na The bottom polar plate is formed by reference voltage V ref Connected to ground gnd, the differential voltage on the top plate of capacitor array 2 increases by 2 (-3) V ref ；
Thirteen cases: if D N D WIN D N-1 D N-2 0011, the second last low-order capacitor C N-2,pa The bottom polar plate is formed by reference voltage V ref Connected to ground level gnd, the second next higher capacitor C N-2,nb The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage reduction 2 on top plate of capacitor array 2 (-3) V ref ；
Fourteen cases: if D N D WIN D N-1 D N-2 0010, the second upper capacitor C N-1,pb The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage on top plate of capacitor array 2 increases by 2 (-3) V ref ；
Fifteen cases: if D N D WIN D N-1 D N-2 =0001, the second last low-order capacitor C N-2,pa The bottom polar plate is formed by reference voltage V ref Connected to ground level gnd, the second next lower capacitor C N-2,nb The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage reduction 2 on top plate of capacitor array 2 (-3) V ref ；
Sixteen cases: if D N D WIN D N-1 D N-2 =0000, skip D N-3 A second one of the upper minimum capacitors C N-3,pa The bottom plate is connected to the reference voltage V by the ground level gnd ref Second two lower minimum capacitors C N-3,nb The bottom polar plate is formed by reference voltage V ref Connected to ground gnd, the differential voltage on the top plate of capacitor array 2 increases by 2 (-4) V ref 。
Step B5, the comparator 3 obtains the digital code D in the bypass window by comparing the voltages of the top electrode plates of the upper capacitor array 2-1 and the lower capacitor array 2-2 obtained in step B4 N-Kiw-1 Wherein K is iw For the number of steps of conversion in the window, K is 5.ltoreq.K iw N-3 is less than or equal to the numerical code D N-Kiw-1 Controlling the connection positions of the bottom electrode plates of the capacitors in the upper capacitor array 2-1 and the lower capacitor array 2-2;
D N-Kiw-1 when=1, the first lower N-K iw -1-bit capacitance C N-Kiw-1,n The bottom plate is connected to the reference voltage V by the ground level gnd ref ，5≤K iw N-3, differential voltage on top plate of capacitor array 2 is reduced by 2 (-Kiw-2) V ref The method comprises the steps of carrying out a first treatment on the surface of the Otherwise, D N-Kiw-1 When=0, the first upper N-K iw -1-bit capacitance C N-Kiw-1,p The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage on top plate of capacitor array 2 increases by 2 (-Kiw-2) V ref ；
And repeating the operation in the bypass window in the step B5 until the digital code D is obtained 1 ；
Outside the bypass window, two limit cases, D N D WIN D N-1 D N-2 =0000 or 1111, the digital code D will be skipped N-Kow1+2 Obtaining the digital code D N-Kow1+1 ，K ow1 For the number of steps of conversion under the limit condition outside the bypass window, K is more than or equal to 5 ow1 N-1 is less than or equal to, according to digital code D N-Kow1+1 The connection positions of the bottom electrode plates of the capacitors in the upper capacitor array 2-1 and the lower capacitor array 2-2 are controlled, specifically:
D N-Kow1+1 when=1, the first lower N-K ow1 +1 bit capacitance C N-Kow1+1,n The bottom plate is connected to the reference voltage V by the ground level gnd ref ，5≤K ow1 N-1, differential voltage on top plate of capacitor array 2 is reduced by 2 (-Kow1) V ref The method comprises the steps of carrying out a first treatment on the surface of the Otherwise, D N-Kow1+1 When=0, the first upper N-K ow1 +1 bit capacitance C N-Kow1+1,p The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage on top plate of capacitor array 2 increases by 2 (-Kow1) V ref ；
And repeating the operation of the step B5 outside the bypass window until the digital code D is obtained 1 ；
Other non-limiting conditions, digital codes D are obtained N-Kow2+2 ，K ow2 For the number of steps of conversion under non-limiting conditions outside the bypass window, K is more than or equal to 5 ow2 N is less than or equal to D according to digital code N-Kow2+2 Control the connection position of the bottom electrode plates of the capacitors in the upper capacitor array 2-1 and the lower capacitor array 2-2, specificallyThe method comprises the following steps:
voltage outside the bypass window, not limited, D N-Kow2+2 When=1, K ow2 =5, the second upper two least significant capacitors C N-3,pb The bottom polar plate is formed by reference voltage V ref Connected to ground level gnd, the second lower-most capacitor C N-3,na The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage reduction 2 on top plate of capacitor array 2 (-Kow2+1) V ref The method comprises the steps of carrying out a first treatment on the surface of the When 6 is less than or equal to K ow2 N is less than or equal to N, the first N-K ow2 +2 bit capacitance C N-Kow2+2,n The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage reduction 2 on top plate of capacitor array 2 (-Kow2+1) V ref The method comprises the steps of carrying out a first treatment on the surface of the Otherwise, D N-Kow2+2 When=0, K ow2 When=5, the second one of the upper least significant capacitors C N-3,pa The bottom plate is connected to the reference voltage V by the ground level gnd ref Second two lower minimum capacitors C N-3,nb The bottom polar plate is formed by reference voltage V ref Connected to ground gnd, the differential voltage on the top plate of capacitor array 2 increases by 2 (-Kow2+1) V ref The method comprises the steps of carrying out a first treatment on the surface of the When 6 is less than or equal to K ow2 N is less than or equal to N, N-K is on the first ow2 +2 bit capacitance C N-Kow2+2,p The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage on top plate of capacitor array 2 increases by 2 (-Kow2+1) V ref 。
And repeating the operation of the step B5 outside the bypass window until the digital code D is obtained 1 ；
Step C, code spelling stage:
the digital control logic circuit 4 outputs the digital codes of the comparator 3 to the code spelling device 5, and the code spelling device 5 carries out code spelling on each digital code to obtain converted N-bit digital codes. The method comprises the following steps:
case one: at-2 (-3) V ref 2～2 (-3) V ref Inside the bypass window, let D N-1 ＝D WIN 、D N-2 ＝D WIN And D N-3 ＝D WIN The spelling device 5 outputs the converted N-bit digital code;
and a second case: outside the bypass window, if the limit condition isUnder the condition D N D WIN D N-1 D N-2 =1111 or 0000, let D N-3 ＝D WIN The spelling device 5 outputs the converted N-bit digital code;
and a third case: outside the bypass window, if not limited, D N When=1, the corresponding digital code D N-3 D is added at the position WIN And carry calculation, the spelling device 5 outputs the converted N-bit digital code; d (D) N When=0, the corresponding digital code D N-3 To subtract D WIN And there is a borrowing calculation, the spelling machine 5 outputs the converted N-bit digital code.
Therefore, the differential output end of the comparator 3 of the method of the invention generates control signals to control the bottom plate switches of the upper capacitor array 2-1 and the lower capacitor array 2-2 after passing through the digital control logic 4, the first time of switching the capacitors generates a bypass window, judges whether the differential input voltage is in the window, and if the differential input voltage is in the window, skips the conversion period of the upper bits for the first two times, can reduce the conversion times and reduce the power consumption of CDAC, the comparator and the control logic; if the capacitor generating the bypass window is not switched back outside the window, normal conversion is continued, and the correct digital code is output through the spelling, so that the power consumption of switching of partial DACs is reduced.
The invention will be described in detail with reference to an example, since D N =1 and D N In both cases =0, the process of quantizing the poke capacitance of the most significant bit (Most Significant Bit, MSB) to the least significant bit (Least Significant Bit, LSB) is completely symmetrical, the sar adc process after 6 bits is identical, the embodiment here describes the topology of n=6, assuming D N Fig. 2 shows a schematic diagram of switching of the present invention applied to a 6-bit SAR ADC.
Step A, sampling stage
The positive input voltage VIP and the negative input voltage VIN are respectively connected to the top plates of the upper capacitor array 2-1 and the lower capacitor array 2-2 through the sampling switch 1, and the first upper sub-capacitor array DAC of the upper capacitor array 2-1 P1 And a second one of the sub-capacitor array DACs P2a Is connected to ground level gnd, second upper two sub-capacitor array DAC P2b Is connected to the reference voltage V ref The method comprises the steps of carrying out a first treatment on the surface of the First lower capacitor array DAC of lower capacitor array 2-2 N1 And a second one of its lower capacitor array DACs N2a Is connected to ground level gnd, second two lower sub-capacitor array DAC N2b Is connected to the reference voltage V ref 。
Step B, transition stage
Step B1, the sampling switch 1 of the analog-to-digital converter is turned off, and then the comparator 3 directly compares MSB bits of the positive input voltage VIP and the negative input voltage VIN of the top plates of the upper capacitor array 2-1 and the lower capacitor array 2-2 to obtain a digital code D 6 According to the digital code D 6 Controlling the connection positions of the bottom electrode plates of the capacitors in the upper capacitor array 2-1 and the lower capacitor array 2-2;
due to D 6 =1, the second and last low capacitance C 4,pb The bottom polar plate is formed by reference voltage V ref Connected to ground level gnd, the second lower capacitor C 4,na The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage reduction 2 on top plate of capacitor array 2 (-3) V ref Forming a 0-2 (-3) V ref Is a bypass window of (2);
step B2, according to the digital code D 6 And D WIN Controlling the connection positions of the bottom electrode plates of the capacitors in the upper capacitor array 2-1 and the lower capacitor array 2-2;
case one: if D 6 D WIN =11, explaining that the differential input voltage is within windows 0 to 2 (-3) V ref In addition, the second upper most significant capacitor C 6,pb The bottom polar plate is formed by reference voltage V ref Connected to ground level gnd, the second lower most significant capacitor C 6,na The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage reduction 2 on top plate of capacitor array 2 (-1) V ref ；
And a second case: if D 6 D WIN =10, explaining that the differential input voltage is within windows 0 to 2 (-3) V ref Within, skip the digital code D 5 、D 4 D at this time WIN For D 3 A second one of the upper minimum capacitors C 3,pa The bottom plate is connected to the reference voltage V by the ground level gnd ref Second two lower minimum capacitors C 3,nb The bottom polar plate is formed by reference voltage V ref Connected to ground gnd, the differential voltage on the top plate of capacitor array 2 increases by 2 (-4) V ref ；
Step B3, according to the digital code D outside the window 6 、D WIN And D 5 The connection position of the bottom electrode plates of the capacitors in the upper capacitor array 2-1 and the lower capacitor array 2-2 is controlled, and the digital code D is used in the window 6 、D WIN And D 2 Controlling the connection positions of the bottom electrode plates of the capacitors in the upper capacitor array 2-1 and the lower capacitor array 2-2;
case one: if D 6 D WIN D 5 =111, the second and last higher capacitor C 5,pb The bottom polar plate is formed by reference voltage V ref Connected to ground level gnd, the second next higher capacitor C 5,na The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage reduction 2 on top plate of capacitor array 2 (-2) V ref ；
And a second case: if D 6 D WIN D 5 =110, the second last higher capacitor C 5,pa The bottom plate is connected to V by gnd ref Second, its next high-order capacitance C 5,nb The bottom polar plate is formed by reference voltage V ref The differential voltage on the top plate of capacitor array 2 increases by 2, connected to ground gnd (-2) V ref ；
And a third case: if D 6 D WIN D 2 =101, first lower 2-bit capacitor C 2,n The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage reduction 2 on top plate of capacitor array 2 (-5) V ref The comparator obtains a digital code D by comparing the voltages of the top polar plates of the upper capacitor array 2-1 and the lower capacitor array 2-2 at the moment 1 And (3) ending the conversion;
case four: if D 6 D WIN D 2 =100, the first upper 2-bit capacitor C 2,p The bottom polar plate is groundedgnd is connected to reference voltage V ref Differential voltage on top plate of capacitor array 2 increases by 2 (-5) V ref ；
The step B4 is that the digital code D is used outside the window 6 、D WIN 、D 5 And D 4 The connection position of the bottom electrode plates of the capacitors in the upper capacitor array 2-1 and the lower capacitor array 2-2 is controlled, and the digital code D is used in the window 2 The connection position of the bottom polar plate of the capacitor is controlled, and the comparator 3 obtains a digital code D1 by comparing the voltages of the top polar plates in the upper capacitor array 2-1 and the lower capacitor array 2-2 at the moment;
Case one: if D 6 D WIN D 5 D 4 =1111, skip D 3 Second upper least significant capacitor C 3,pb The bottom polar plate is formed by reference voltage V ref Connected to ground level gnd, the second lower-most capacitor C 3,na The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage reduction 2 on top plate of capacitor array 2 (-4) V ref ；
And a second case: if D 6 D WIN D 5 D 4 =1110, the second and last low capacitance C 4,pb The bottom plate is connected to the reference voltage V by the ground level gnd ref Second lower capacitor C 4,na The bottom polar plate is formed by reference voltage V ref Connected to ground gnd, the differential voltage on the top plate of capacitor array 2 increases by 2 (-3) V ref ；
And a third case: if D 6 D WIN D 5 D 4 =1101, the second next higher capacitor C 5,na The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage reduction 2 on top plate of capacitor array 2 (-3) V ref ；
Case four: if D 6 D WIN D 5 D 4 =1100, the second and last low capacitance C 4,pb The bottom plate is connected to the reference voltage V by the ground level gnd ref Second lower capacitor C 4,na The bottom polar plate is formed by reference voltage V ref Connected to ground gnd on the top plate of capacitor array 2Is increased by 2 (-3) V ref ；
Step B5, according to the digital code D outside the window 3 Controlling the connection position of the bottom electrode plates of the capacitors in the upper capacitor array 2-1 and the lower capacitor array 2-2, and repeating the step B5 until a digital code D is obtained 1 The method comprises the steps of carrying out a first treatment on the surface of the The method comprises the following steps:
case one: voltage outside window, limit case when D 6 D WIN D 5 D 4 ＝1111，D 2 When=1, the first lower 2-bit capacitor C 2,n The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage reduction 2 on top plate of capacitor array 2 (-5) V ref The method comprises the steps of carrying out a first treatment on the surface of the Otherwise, D 2 When=0, the first upper 2-bit capacitor C 2,p The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage on top plate of capacitor array 2 increases by 2 (-5) V ref ；
And a second case: voltage outside window, not limit, D N-Kow2+2 When=1, K ow2 =5, the second upper two least significant capacitors C 3,pb The bottom polar plate is formed by reference voltage V ref Connected to ground level gnd, the second lower-most capacitor C 3,na The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage reduction 2 on top plate of capacitor array 2 (-K+1) V ref ；6≤K ow2 N+1, the first N-K ow2 +2 bit capacitance C N-Kow2+2,n The bottom plate is connected to the reference voltage V by the ground level gnd ref Differential voltage reduction 2 on top plate of capacitor array 2 (-K+1) V ref . Otherwise, D N-Kow2+2 When=0, K ow2 When=5, the second one of the upper least significant capacitors C 3,pa The bottom plate is connected to the reference voltage V by the ground level gnd ref Second two lower minimum capacitors C 3,nb The bottom polar plate is formed by reference voltage V ref Connected to ground gnd, the differential voltage on the top plate of capacitor array 2 increases by 2 (-Kow2+1) V ref ；6≤K ow2 N+1, N-K on the first ow2 +2-bit C N-Kow2+2,p The bottom plate is connected to the reference voltage by ground level gndV ref Differential voltage on top plate of capacitor array 2 increases by 2 (-Kow2+1) V ref ；
And C, the spelling device 5 carries out spelling on different digital codes, and specifically comprises the following steps:
case one: at 0 to 2 (-3) V ref Within the window, let D 5 ＝D WIN 、D 4 ＝D WIN 、D 3 ＝D WIN The correct output code is output by the code spelling device 5.
And a second case: outside the window, if under limit conditions D 6 D WIN D 5 D 4 =1111, let D 3 ＝D WIN The code spelling device 5 outputs the correct output code.
And a third case: outside the window, if not limited, the digital code D 3 To be added with D WIN And carry calculation, the spelling 5 outputs the correct digital code.
As shown in fig. 3, a graph of MATLAB simulation results of switching and reset power consumption applied to 10-bit sar ADC according to the present invention, where V is CDAC reference voltage of most switching algorithms including Vcm-based switching algorithm for convenience of comparison; the invention reduces the DAC power consumption of 87.29% on average, the input voltage can reduce the DAC power consumption of 95.56% in the window, the capacitance area of 50% is saved, and the energy efficiency and area trade-off is realized.
In summary, the method of the invention utilizes + -2 of the first handoff -3 The voltage change of Vref utilizes DAC capacitance to generate a bypass window, extra errors are avoided being introduced, the voltage in the window can skip the capacitance switching of the upper two bits, the conversion period is reduced, the voltage outside the window can improve partial nonlinearity, half of the capacitance area is saved by adopting top polar plate sampling, and a good compromise of energy efficiency and area saving is realized.
The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the spirit of the present invention.

Claims (8)

1. The bypass window switching method applied to the successive approximation type analog-to-digital converter is characterized in that the analog-to-digital converter comprises a sampling switch (1), a capacitor array (2), a comparator (3), a digital control logic circuit (4) and a code spelling device (5), wherein the capacitor array (2) comprises an upper capacitor array (2-1) and a lower capacitor array (2-2) which are identical in structure; the differential input voltage, namely a positive input Voltage (VIP) and a negative input Voltage (VIN), are respectively connected to top polar plates of the upper capacitor array (2-1) and the lower capacitor array (2-2) through a sampling switch (1); the top polar plate of the upper capacitor array (2-1) is connected with the non-inverting input end of the comparator (3), and the top polar plate of the lower capacitor array (2-2) is connected with the inverting input end of the comparator (3); the differential output end of the comparator (3) is connected to the digital control logic circuit (4), the digital control logic circuit (4) generates control signals to control the bottom polar plates of the upper capacitor array (2-1) and the lower capacitor array (2-2) to be connected to corresponding levels, and the code spelling device (5) carries out code spelling on each digital code output by the digital control logic circuit (4) to generate converted digital codes;
The upper capacitor array (2-1) comprises a first upper sub-capacitor array (DAC) P1 ) Second one of the upper sub-capacitor arrays (DAC) P2a ) And a second sub-capacitor array (DAC) P2b ) The method comprises the steps of carrying out a first treatment on the surface of the The lower capacitor array (2-2) comprises a first lower capacitor array (DAC) N1 ) Second one of its lower capacitor array (DAC) N2a ) And a second sub-capacitor array (DAC) N2b )；
The bypass window switching method applied to the successive approximation type analog-to-digital converter comprises the following steps of:
step A, sampling:
a first upper sub-capacitor array (DAC) of the upper capacitor array (2-1) P1 ) And a second one of the sub-capacitor arrays (DAC P2a ) Is connected to ground (gnd), a second sub-capacitor array (DAC) P2b ) Is connected to a reference voltage (V ref ) The method comprises the steps of carrying out a first treatment on the surface of the First lower capacitor array (DAC) of lower capacitor array (2-2) N1 ) And a second one of its lower capacitor arrays (DAC N2a ) Is connected to ground level(gnd) second sub-capacitor array (DAC) N2b ) Is connected to a reference voltage (V ref )；
Step B, a conversion stage:
step B1, the sampling switch (1) is disconnected, and then the comparator (3) directly compares the most significant bit of the positive input Voltage (VIP) and the negative input Voltage (VIN) which are kept on the top plates of the upper capacitor array (2-1) and the lower capacitor array (2-2) to obtain a digital code D N Wherein N represents the number of bits of the analog-to-digital converter, and the digital control logic circuit (4) is configured to control the digital control logic circuit according to the digital code D N Controlling the connection positions of the bottom electrode plates of the capacitors in the upper capacitor array (2-1) and the lower capacitor array (2-2);
step B2, the comparator (3) obtains a digital code D by comparing the voltages of the top electrode plates of the upper capacitor array (2-1) and the lower capacitor array (2-2) obtained from the step B1 WIN According to the digital code D N And D WIN Judging whether the differential input voltage is in a bypass window or not, so as to control the connection position of the bottom electrode plates of the capacitors in the upper capacitor array (2-1) and the lower capacitor array (2-2);
step B3, the comparator (3) obtains a digital code D in the bypass window by comparing the voltages of the top polar plates of the upper capacitor array (2-1) and the lower capacitor array (2-2) obtained in the step B2 N-4 According to digital code D within a bypass window N 、D WIN And D N-4 Controlling the connection positions of the bottom electrode plates of the capacitors in the upper capacitor array (2-1) and the lower capacitor array (2-2); obtaining digital codes D outside the bypass window N-1 According to digital code D outside the bypass window N 、D WIN And D N-1 Controlling the connection positions of the bottom electrode plates of the capacitors in the upper capacitor array (2-1) and the lower capacitor array (2-2);
step B4, the comparator (3) obtains the digital code D in the bypass window by comparing the voltages of the top polar plates of the upper capacitor array (2-1) and the lower capacitor array (2-2) obtained in the step B3 N-5 According to the digital code D in the bypass window N 、D WIN 、D N-4 And D N-5 Controlling the connection positions of the bottom electrode plates of the capacitors in the upper capacitor array (2-1) and the lower capacitor array (2-2); deriving digital codes D outside the bypass window N-2 In the followingAccording to digital code D outside the bypass window N 、D WIN 、D N-1 And D N-2 Controlling the connection positions of the bottom electrode plates of the capacitors in the upper capacitor array (2-1) and the lower capacitor array (2-2);
step B5, the comparator (3) obtains the digital code D in the bypass window by comparing the voltages of the top polar plates of the upper capacitor array (2-1) and the lower capacitor array (2-2) obtained in the step B4 N-Kiw-1 Wherein K is iw For the number of steps of conversion in the window, K is 5.ltoreq.K iw N-3 is less than or equal to the numerical code D N-Kiw-1 Controlling the connection positions of the bottom electrode plates of the capacitors in the upper capacitor array (2-1) and the lower capacitor array (2-2); and repeating the operation in the bypass window in the step B5 until the digital code D is obtained 1 The method comprises the steps of carrying out a first treatment on the surface of the Outside the bypass window, two limit cases, D N D WIN D N-1 D N-2 =0000 or 1111, the digital code D will be skipped N-Kow1+2 Obtaining the digital code D N-Kow1+1 ，K ow1 For the number of steps of conversion under the limit condition outside the bypass window, K is more than or equal to 5 ow1 N-1 is less than or equal to, according to digital code D N-Kow1+1 Controlling the connection position of the bottom plates of the capacitors in the upper capacitor array (2-1) and the lower capacitor array (2-2), and repeating the operation of the step B5 outside the bypass window until the digital code D is obtained 1 The method comprises the steps of carrying out a first treatment on the surface of the Other non-limiting conditions, digital codes D are obtained N-Kow2+2 ，K ow2 For the number of steps of conversion under non-limiting conditions outside the bypass window, K is more than or equal to 5 ow2 N is less than or equal to D according to digital code N-Kow2+2 Controlling the connection position of the bottom plates of the capacitors in the upper capacitor array (2-1) and the lower capacitor array (2-2), and repeating the operation of the step B5 outside the bypass window until the digital code D is obtained 1 ；
Step C, code spelling stage:
the digital control logic circuit (4) outputs the digital codes of the comparator (3) to the code spelling device (5), and the code spelling device (5) carries out code spelling on each digital code to obtain converted N-bit digital codes.
2. A bypass window switching method for a successive approximation analog to digital converter according to claim 1, wherein the second one of the sub-capacitor arrays (DAC P2a ) And a second sub-capacitor array (DAC) P2b ) Is a split capacitor array of high four-bit capacitors, wherein the second highest bit capacitor (C N,pa ) Has a capacitance value of 2 N-3 C, the second last high-order capacitor (C N-1,pa ) Has a capacitance value of 2 N-4 C, the second last low-order capacitance (C N-2,pa ) Has a capacitance value of 2 N-5 C, the second one of the upper minimum capacitors (C N-3,pa ) Has a capacitance value of 2 N-6 C, wherein N represents the number of bits of the analog-to-digital converter, and C is a unit capacitance value; the first upper sub-capacitor array (DAC P1 ) Is a low-order capacitance, wherein the first upper N-9-order capacitance (C N-9,p ) Is a virtual capacitor, the capacitance value is 1C, the first upper N-4 bit capacitor (C N-4,p ) Has a capacitance value of 2 N-6 C, first upper N-5 bit capacitor (C N-5,p ) Has a capacitance value of 2 N-7 C, first upper N-6 bit capacitor (C N-6,p ) Has a capacitance value of 2 N-8 C, first upper N-7 bit capacitor (C N-7,p ) The capacitance value of (2) N-9 C, first upper N-8 bit capacitor (C N-8,p ) The capacitance value of (2) is 1C.
3. A bypass window switching method for a successive approximation analog-to-digital converter according to claim 1, wherein the digital control logic circuit (4) in step B1 is configured to control the digital control logic circuit according to digital code D N The connection position of the bottom electrode plates of the capacitors in the upper capacitor array (2-1) and the lower capacitor array (2-2) is controlled, and the method specifically comprises the following steps:
case one: if D N =1, the second last low capacitance (C N-2,pb ) The bottom polar plate is formed by reference voltage (V ref ) Is connected to the ground level (gnd), the second lower capacitor (C N-2,na ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref ) Differential voltage reduction 2 on top plate of capacitor array (2) (-3) V ref Forming a 0-2 (-3) V ref Wherein V is ref Is the reference voltage;
and a second case: if D N =0, the second last low capacitance (C N-2,pa ) The bottom plate is connected to the reference by a ground level (gnd) Test voltage (V) ref ) Second its second next lower capacitance (C N-2,nb ) The bottom polar plate is formed by reference voltage (V ref ) Connected to ground (gnd), the differential voltage on the top plate of the capacitor array (2) increases by 2 (-3) V ref Forming a 0 to-2 (-3) V ref Is provided.
4. The method as claimed in claim 1, wherein the step B2 is based on digital code D N And D WIN Judging whether the differential input voltage is within a bypass window or not, so as to control the connection position of the capacitor bottom plates in the upper capacitor array (2-1) and the lower capacitor array (2-2), and specifically comprising the following steps:
case one: if D N D WIN =11, explaining that the differential input voltage is in the bypass window 0-2 (-3) V ref In addition, the second upper most significant capacitor (C N,pb ) The bottom polar plate is formed by reference voltage (V ref ) Is connected to the ground level (gnd), the second lower most significant capacitor (C N,na ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref ) Differential voltage reduction 2 on top plate of capacitor array (2) (-1) V ref ；
And a second case: if D N D WIN =10, explaining that the differential input voltage is within the bypass window 0-2 (-3) V ref Within, skip the digital code D N-1 、D N-2 A second one of the upper minimum capacitors (C N-3,pa ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref ) Second two lower most significant capacitors (C N-3,nb ) The bottom polar plate is formed by reference voltage (V ref ) Connected to ground (gnd), the differential voltage on the top plate of the capacitor array (2) increases by 2 (-4) V ref ；
And a third case: if D N D WIN =01, explaining that the differential input voltage is in the bypass window 0 to-2 (-3) V ref Within, skip the digital code D N-1 、D N-2 A second upper two least significant capacitors (C N-3,pb ) The bottom polar plate is formed by reference voltage (V ref ) Is connected to the ground level (gnd), a second one of the lower most significant capacitors (C N-3,na ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref ) Differential voltage reduction 2 on top plate of capacitor array (2) (-4) V ref ；
Case four: if D N D WIN =00, illustrating that the differential input voltage is at bypass windows 0 to-2 (-3) V ref In addition, the second highest capacitance (C N,pa ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref ) A second two lower most significant capacitors (C N,nb ) The bottom polar plate is formed by reference voltage (V ref ) Connected to ground (gnd), the differential voltage on the top plate of the capacitor array (2) increases by 2 (-1) V ref 。
5. The method as claimed in claim 1, wherein the step B3 is performed according to digital code D within the bypass window N 、D WIN And D N-4 The connection positions of the bottom electrode plates of the capacitors in the upper capacitor array (2-1) and the lower capacitor array (2-2) are controlled, and the connection positions are specifically as follows:
case one: if D N D WIN D N-4 =101, the first N-4 bit capacitor (C N-4,n ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref ) Differential voltage reduction 2 on top plate of capacitor array (2) (-5) V ref ；
And a second case: if D N D WIN D N-4 =100, the first upper N-4 bit capacitor (C N-4,p ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref ) Differential voltage on top plate of capacitor array (2) is increased by 2 (-5) V ref ；
And a third case: if D N D WIN D N-4 011, the first lower N-4 bit capacitor (C N-4,n ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref ) Differential voltage reduction 2 on top plate of capacitor array (2) (-5) V ref ；
Case four: if D N D WIN D N-4 =010, the first upper N-4 bit capacitor (C N-4,p ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref ) Differential voltage on top plate of capacitor array (2) is increased by 2 (-5) V ref ；
Step B3, according to the digital code D outside the bypass window N 、D WIN And D N-1 The connection positions of the bottom electrode plates of the capacitors in the upper capacitor array (2-1) and the lower capacitor array (2-2) are controlled, and the connection positions are specifically as follows:
case five: if D N D WIN D N-1 =111, the second two last higher capacitors (C N-1,pb ) The bottom polar plate is formed by reference voltage (V ref ) Is connected to the ground level (gnd), the second next higher capacitor (C N-1,na ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref ) Differential voltage reduction 2 on top plate of capacitor array (2) (-2) V ref ；
Case six: if D N D WIN D N-1 =110, the second last higher capacitor (C N-1,pa ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref ) A second next higher capacitor (C N-1,nb ) The bottom polar plate is formed by reference voltage (V ref ) Connected to ground (gnd), the differential voltage on the top plate of the capacitor array (2) increases by 2 (-2) V ref ；
Case seven: if D N D WIN D N-1 =001, the second two last higher capacitors (C N-1,pb ) The bottom polar plate is formed by reference voltage (V ref ) Is connected to the ground level (gnd), the second next higher capacitor (C N-1,na ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref ) Differential voltage reduction 2 on top plate of capacitor array (2) (-2) V ref ；
Case eight: if D N D WIN D N-1 =000, the second last higher capacitor (C N-1,pa ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref ) A second next higher capacitor (C N-1,nb ) The bottom polar plate is formed by reference voltage (V ref ) Connected to ground (gnd), capacitanceDifferential voltage increase 2 on top plate of array (2) (-2) V ref 。
6. The method as claimed in claim 1, wherein the step B4 is performed according to digital code D in the bypass window N 、D WIN 、D N-4 And D N-5 The connection position of the bottom electrode plates of the capacitors in the upper capacitor array (2-1) and the lower capacitor array (2-2) is controlled, and the method specifically comprises the following steps:
case one: if D N D WIN D N-4 D N-5 =1011, first lower N-5 bit capacitor (C N-5,n ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref ) Differential voltage reduction 2 on top plate of capacitor array (2) (-6) V ref ；
And a second case: if D N D WIN D N-4 D N-5 =1010, the first upper N-5 bit capacitor (C N-5,p ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref ) Differential voltage on top plate of capacitor array (2) is increased by 2 (-6) V ref ；
And a third case: if D N D WIN D N-4 D N-5 =1001, first N-5 bit capacitor (C N-5,n ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref ) Differential voltage reduction 2 on top plate of capacitor array (2) (-6) V ref ；
Case four: if D N D WIN D N-4 D N-5 =1000, the first upper N-5 bit capacitor (C N-5,p ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref ) Differential voltage on top plate of capacitor array (2) is increased by 2 (-6) V ref ；
Case five: if D N D WIN D N-4 D N-5 =0111, the first lower N-5 bit capacitor (C N-5,n ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref ) Differential voltage reduction 2 on top plate of capacitor array (2) (-6) V ref ；
Case six: if D N D WIN D N-4 D N-5 =0110, the first upper N-5 bit capacitor (C N-5,p ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref ) Differential voltage on top plate of capacitor array (2) is increased by 2 (-6) V ref ；
Case seven: if D N D WIN D N-4 D N-5 =0101, first N-5 bit capacitor (C N-5,n ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref ) Differential voltage reduction 2 on top plate of capacitor array (2) (-6) V ref ；
Case eight: if D N D WIN D N-4 D N-5 =0100, the first upper N-5 bit capacitor (C N-5,p ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref ) Differential voltage on top plate of capacitor array (2) is increased by 2 (-6) V ref ；
Step B4, according to the digital code D outside the bypass window N 、D WIN 、D N-1 And D N-2 The connection position of the bottom electrode plates of the capacitors in the upper capacitor array (2-1) and the lower capacitor array (2-2) is controlled, and the method specifically comprises the following steps:
case nine: if D N D WIN D N-1 D N-2 =1111, skip D N-3 A second upper two least significant capacitors (C N-3,pb ) The bottom polar plate is formed by reference voltage (V ref ) Is connected to the ground level (gnd), a second one of the lower most significant capacitors (C N-3,na ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref ) Differential voltage reduction 2 on top plate of capacitor array (2) (-4) V ref ；
Case ten: if D N D WIN D N-1 D N-2 =1110, the second two last low-order capacitors (C N-2,pb ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref ) A second low-order capacitor (C N-2,na ) The bottom polar plate is formed by reference voltage (V ref ) Connected to ground (gnd), the differential voltage on the top plate of the capacitor array (2) increases by 2 (-3) V ref ；
Case eleven: if D N D WIN D N-1 D N-2 =1101, the second next higher capacitor (C N-1,nb ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref ) Differential voltage reduction 2 on top plate of capacitor array (2) (-3) V ref ；
Twelve cases: if D N D WIN D N-1 D N-2 =1100, the second two last low-order capacitors (C N-2,pb ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref ) A second low-order capacitor (C N-2,na ) The bottom polar plate is formed by reference voltage (V ref ) Connected to ground (gnd), the differential voltage on the top plate of the capacitor array (2) increases by 2 (-3) V ref ；
Thirteen cases: if D N D WIN D N-1 D N-2 =0011, the second last low-order capacitance (C N-2,pa ) The bottom polar plate is formed by reference voltage (V ref ) Connected to ground level (gnd), a second of its next higher capacitors (C N-2,nb ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref ) Differential voltage reduction 2 on top plate of capacitor array (2) (-3) V ref ；
Fourteen cases: if D N D WIN D N-1 D N-2 =0010, the second two last higher capacitors (C N-1,pb ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref ) Differential voltage on top plate of capacitor array (2) is increased by 2 (-3) V ref ；
Fifteen cases: if D N D WIN D N-1 D N-2 =0001, the second last low-order capacitance (C N-2,pa ) The bottom polar plate is formed by reference voltage (V ref ) Connected to ground level (gnd), a second low-order capacitor (C N-2,nb ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref ) Differential voltage reduction 2 on top plate of capacitor array (2) (-3) V ref ；
Sixteen cases: if D N D WIN D N-1 D N-2 =0000, skip D N-3 A second one of the upper minimum capacitors (C N-3,pa ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref ) Second two lower most significant capacitors (C N-3,nb ) The bottom polar plate is formed by reference voltage (V ref ) Connected to ground (gnd), the differential voltage on the top plate of the capacitor array (2) increases by 2 (-4) V ref 。
7. The method as claimed in claim 1, wherein the step B5 is based on digital code D N-Kiw-1 The connection positions of the bottom electrode plates of the capacitors in the upper capacitor array (2-1) and the lower capacitor array (2-2) are controlled, and the connection positions are specifically as follows:
case one: voltage within bypass window, D N-Kiw-1 When=1, the first lower N-K iw -1-bit capacitance (C N-Kiw-1,n ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref )，5≤K iw N-3, the differential voltage on the top polar plate of the capacitor array (2) is reduced by 2 (-Kiw-2) V ref The method comprises the steps of carrying out a first treatment on the surface of the Otherwise, D N-Kiw-1 When=0, the first upper N-K iw -1-bit capacitance (C N-Kiw-1,p ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref ) Differential voltage on top plate of capacitor array (2) is increased by 2 (-Kiw-2) V ref ；
Step B5 is described according to the digital code D N-Kow1+1 The connection positions of the bottom electrode plates of the capacitors in the upper capacitor array (2-1) and the lower capacitor array (2-2) are controlled, and the connection positions are specifically as follows:
and a second case: the voltage outside the bypass window, the limit case including D N D WIN D N-1 D N-2 =0000 or 1111, d N-Kow1+1 When=1, the first lower N-K ow1 +1 bit capacitance (C) N-Kow1+1,n ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref )，5≤K ow1 N-1, the differential voltage on the top polar plate of the capacitor array (2) is reduced by 2 (-Kow1) V ref The method comprises the steps of carrying out a first treatment on the surface of the Otherwise, D N-Kow1+1 When=0, the first upper N-K ow1 +1 bit capacitance (C) N-Kow1+1,p ) The bottom polar plate is electrically connected with the groundFlat (gnd) is connected to a reference voltage (V ref ) Differential voltage on top plate of capacitor array (2) is increased by 2 (-Kow1) V ref ；
Step B5 is described according to the digital code D N-Kow2+2 The connection positions of the bottom electrode plates of the capacitors in the upper capacitor array (2-1) and the lower capacitor array (2-2) are controlled, and the connection positions are specifically as follows:
and a third case: voltage outside the bypass window, not limited, D N-Kow2+2 When=1, K ow2 =5, the second upper two least significant capacitors (C N-3,pb ) The bottom polar plate is formed by reference voltage (V ref ) Is connected to the ground level (gnd), a second one of the lower most significant capacitors (C N-3,na ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref ) Differential voltage reduction 2 on top plate of capacitor array (2) (-Kow2+1) V ref The method comprises the steps of carrying out a first treatment on the surface of the When 6 is less than or equal to K ow2 N is less than or equal to N, the first N-K ow2 +2 bit capacitance (C) N-Kow2+2,n ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref ) Differential voltage reduction 2 on top plate of capacitor array (2) (-Kow2+1) V ref The method comprises the steps of carrying out a first treatment on the surface of the Otherwise, D N-Kow2+2 When=0, K ow2 When=5, the second one of the upper least significant capacitors (C N-3,pa ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref ) Second two lower most significant capacitors (C N-3,nb ) The bottom polar plate is formed by reference voltage (V ref ) Connected to ground (gnd), the differential voltage on the top plate of the capacitor array (2) increases by 2 (-Kow2+1) V ref The method comprises the steps of carrying out a first treatment on the surface of the When 6 is less than or equal to K ow2 N is less than or equal to N, N-K is on the first ow2 +2 bit capacitance (C) N-Kow2+2,p ) The bottom plate is connected to a reference voltage (V) by a ground level (gnd) ref ) Differential voltage on top plate of capacitor array (2) is increased by 2 (-Kow2+1) V ref 。
8. The bypass window switching method applied to the successive approximation analog-to-digital converter according to claim 1, wherein in the step C, the code spelling device (5) spells each digital code to obtain a converted N-bit digital code, specifically:
case one: at-2 (-3) V ref 2～2 (-3) V ref Inside the bypass window, let D N-1 ＝D WIN 、D N-2 ＝D WIN And D N-3 ＝D WIN The code spelling device (5) outputs the converted N-bit digital code;
and a second case: outside the bypass window, if under limit conditions D N D WIN D N-1 D N-2 =1111 or 0000, let D N-3 ＝D WIN The code spelling device (5) outputs the converted N-bit digital code;
and a third case: outside the bypass window, if not limited, D N When=1, the corresponding digital code D N-3 D is added at the position WIN And carry calculation, the spelling device (5) outputs the converted N-bit digital code; d (D) N When=0, the corresponding digital code D N-3 To subtract D WIN And there is borrowing calculation, the spelling device (5) outputs the converted N-bit digital code.
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CN107306135A (en) * 2016-04-22 2017-10-31 瑞昱半导体股份有限公司 The correcting circuit of digital analog converter and bearing calibration
CN108233925A (en) * 2016-12-21 2018-06-29 电子科技大学 It is segmented pre-quantization bypass gradually-appoximant analog-digital converter
CN112583409A (en) * 2020-12-28 2021-03-30 东南大学 Successive approximation type analog-to-digital converter and three-level switching method thereof

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CN102006075A (en) * 2010-12-23 2011-04-06 复旦大学 Successive approximation type analog-to-digital converter of energy-saving capacitor array
CN107306135A (en) * 2016-04-22 2017-10-31 瑞昱半导体股份有限公司 The correcting circuit of digital analog converter and bearing calibration
CN108233925A (en) * 2016-12-21 2018-06-29 电子科技大学 It is segmented pre-quantization bypass gradually-appoximant analog-digital converter
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