CN113676184B - Successive approximation analog-digital converter switching method based on semi-dormant structure - Google Patents

Successive approximation analog-digital converter switching method based on semi-dormant structure Download PDF

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CN113676184B
CN113676184B CN202110979176.6A CN202110979176A CN113676184B CN 113676184 B CN113676184 B CN 113676184B CN 202110979176 A CN202110979176 A CN 202110979176A CN 113676184 B CN113676184 B CN 113676184B
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capacitors
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CN113676184A (en
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吴建辉
黄毅
孙志伟
李红
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Southeast University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0602—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
    • H03M1/0604—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic at one point, i.e. by adjusting a single reference value, e.g. bias or gain error
    • H03M1/0607—Offset or drift compensation

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Abstract

The invention discloses a switching method of a successive approximation analog-to-digital converter based on a semi-dormant structure, which comprises the following steps: for input signals VIP and VIN, N-bit digital output codes are obtained after N times of comparison of an analog-to-digital converter, and the N-bit digital output codes are divided into two stages of sampling and conversion; in the sampling stage, input signals VIP and VIN are connected to top electrode plates of upper and lower capacitor arrays of the two sub analog-to-digital converters through sampling switches, and bottom electrode plates of each capacitor are connected to corresponding voltages; in the conversion stage, the comparator compares MSB bit to LSB bit of the top plate voltage of the upper and lower capacitor arrays to obtain corresponding digital codes to control the state of the bottom plate of each capacitor; obtaining N-bit digital code through N times of comparison. The invention switches to generate +/-V for the first time ref Is measured by the capacitor array reference voltage V ref The method is reduced to half of the common method; the power consumption is further reduced by multiple times of merging operation during switching; only the LSB bits introduce a common mode level offset of 0.5 LSB.

Description

Successive approximation analog-digital converter switching method based on semi-dormant structure
Technical Field
The invention relates to a switching method of a successive approximation analog-to-digital converter based on a semi-dormant structure, and belongs to the field of low-power-consumption charge redistribution type SAR ADCs.
Background
With the development of internet of things (IoT) technology, the service life requirements of sensors on nodes of the internet of things are increasing, and thus more strict requirements are placed on the power consumption of analog-to-digital converters in the sensing devices. The SAR ADC has the advantages of simple structure, high energy efficiency, high digitalization, and wide application in medical monitoring, mobile equipment, wearable equipment and other occasions, and the SAR ADC has medium precision (8-12 bits) and medium sampling rate (1-1000 kS/s).
Currently, the charge redistribution DAC is the mainstream direction of the SAR ADC. The purpose of successive approximation is realized by changing the reference voltage connected with the bottom plate of the capacitor array. Under low voltage, dynamic switching power consumption generated by CDAC capacitance switching accounts for a large part of the whole ADC, so that various research teams at home and abroad make much effort in the direction and provide many energy-efficient switching algorithms. However, they introduce multiple levels, common mode level drift [1], or complex control logic [3], etc., while reducing the power consumption of the CDAC, and even face practical problems, and finally, reduce the power consumption of the CDAC while increasing the power consumption of other modules. Therefore, these switching algorithms are not effective in improving the overall energy efficiency of the SAR ADC. The invention designs a successive approximation analog-digital converter switching method based on a semi-dormant structure based on the structure of [2 ].
[1]Z.Zhu et al.:‘A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18-CMOS for medical implant devices’,IEEE Transactions on Circuits and Systems-I.,2015,62,(9),pp.2167-2176
[2]S.-E.Hsieh and C.-C.Hsieh.:‘A 0.44-fJ/conversion-step 11-bit 600-kS/s SAR ADC with semi-resting DAC’,IEEE Journal of Solid-State Circuits.,2018,53,(9),pp.2595-2603
[3]C.H.Kuo and C.E.Hsieh.:‘Floating capacitor switching SAR ADC’.Electronics Letters,2011,47，(13),742-743
Disclosure of Invention
The invention aims to provide a switching method of a successive approximation analog-to-digital converter based on a semi-dormant structure, so that the power consumption of a CDAC is reduced, and simultaneously, the requirement on other modules of the ADC is not too high.
In order to realize the purpose, the invention adopts the technical scheme that:
a method for switching a successive approximation analog-to-digital converter based on a semi-dormant structure is characterized in that the analog-to-digital converter based on the method comprises two same sub analog-to-digital converters (ADC) 1 And ADC 0 Each sub analog-digital converter comprises a sampling switch, a capacitor array, a comparator and digital control logic, wherein the capacitor array comprises identical upper capacitor array DACs P1 、DAC N1 And lower capacitor array DAC P0 、DAC N0 (ii) a Input signal VIP is connected to DAC through sampling switch P1 And DAC P0 The input signal VIN is connected to the DAC through the sampling switch N1 And DAC N0 The top plate of (1); DAC P1 And DAC P0 The top plate of the DAC is connected with the non-inverting input end of the comparator N1 And DAC N0 The top plate of the comparator is connected with the inverting input end of the comparatorThe differential output end of the voltage divider generates a control signal to control the bottom plate switches of the upper capacitor array and the lower capacitor array through digital control logic, so that the bottom plates of the upper capacitor array and the lower capacitor array are connected to corresponding voltages, combined, split or floated;
each sub-capacitor array is composed of a highest-order capacitor C N-4 And N-6 high-order capacitors and sub-low-order capacitors C 1 Lowest order capacitor C 0 And dummy capacitor C d The capacitor comprises the following capacitors: c i ＝2 i C, wherein i is more than or equal to 0 and less than or equal to N-4 d = C, where N represents the number of bits of the analog-to-digital converter and C is the unit capacitance size;
the method comprises the following steps: for input signals VIP and VIN, N-bit digital output codes are obtained after N times of comparison of an analog-to-digital converter, and the N-bit digital output codes are divided into two stages of sampling and conversion; in the sampling stage, input signals VIP and VIN are connected to top electrode plates of upper and lower capacitor arrays of the two sub analog-to-digital converters through sampling switches, and bottom electrode plates of each capacitor are connected to corresponding voltages; in the conversion stage, the comparator compares the MSB bit to the LSB bit of the voltages of the top electrode plates of the upper and lower capacitor arrays to obtain corresponding digital codes so as to control the states of the bottom electrode plates of the capacitors; obtaining N-bit digital code through N times of comparison.
The sampling phase comprises the following steps:
input signals VIP and VIN are respectively connected to the ADC through sampling switches 1 And ADC 0 Top plate of capacitor array, ADC 1 Sub-capacitor array DAC P1 All capacitor bottom plates of (2) are connected to V ref Reference voltage, and sub-capacitor array DAC N1 All capacitor bottom plates of gnd are connected to gnd; ADC (analog to digital converter) 0 Sub-capacitor array DAC P0 All capacitor bottom plates of (2) are connected to gnd, and the sub-capacitor array DAC N0 All capacitor bottom plates of (2) are connected to V ref A reference voltage.
The transition phase comprises the steps of:
step B1, switching off a sampling switch of the analog-to-digital converter, and then directly comparing input signals VIP and VIN held on top electrode plates of the upper capacitor array and the lower capacitor array by a comparator to obtainGiving the most significant bit D N-1 According to digital code D N-1 Controlling the connection relation of the capacitor bottom plates in the upper capacitor array and the lower capacitor array so as to obtain a new top plate voltage;
step B2, the comparator compares the voltages of the top plates of the upper and lower capacitor arrays obtained in the step B1 to obtain a digital code D N-2 According to digital codes D N-1 And D N-2 Controlling the connection relation of the bottom plates of the capacitors in the upper capacitor array and the lower capacitor array so as to obtain a new top plate voltage;
step B3, the comparator compares the voltages of the top electrode plates of the upper capacitor array and the lower capacitor array obtained from the step B2 to obtain a digital code D K Where K is greater than or equal to 1 and less than or equal to N-3, according to the digital code D N-1 And D N-2 And D K Controlling the connection relation of the bottom plates of the capacitors in the upper and lower capacitor arrays; and repeating the step B4 until a digital code D is obtained 1 ；
Step B4, according to the digital code D N-1 And D 1 Controlling the connection relation of the bottom plates of the capacitors in the upper and lower capacitor arrays, and comparing the voltages of the top plates of the upper and lower capacitor arrays by the comparator to obtain a digital code D 0 。
In the step B1, according to the digital code D N-1 The control of the connection relation of the capacitor bottom plates in the upper and lower capacitor arrays is specifically as follows:
the first condition is as follows: if D is N-1 ＝1，ADC 0 The ADC is switched to a dormant state, and the ADC is not subjected to conversion again 0 Performing other operations, DAC P1 And DAC N1 All capacitor bottom plates are combined, so that the differential voltage of the whole DAC is reduced by V ref ；
Case two: if D is N-1 ＝0，ADC 1 The ADC is switched to a dormant state, and the ADC is not switched again in the conversion process 1 Performing other operations, DAC P0 And DAC N0 All capacitor bottom plates are combined, so that the differential voltage of the whole DAC is increased by V ref 。
In the step B2, according to the digital code D N-1 And D N-2 The method comprises the following steps of controlling the connection relation of bottom plates of capacitors in an upper capacitor array and a lower capacitor array, specifically:
the first condition is as follows: if D is N-1 D N-2 ＝11，DAC P1 All but the most significant bit capacitance are connected to gnd by a combination, while the DAC N1 All capacitances except the highest order capacitance are connected by a combination to V ref Reference voltage, so that the differential voltage of the whole DAC will be reduced by 0.5V ref ；
And a second condition: if D is N-1 D N-2 ＝10，DAC P1 All capacitances except the highest order capacitance are connected by a combination to V ref Reference voltage, and DAC N1 All the capacitors except the most significant capacitor are connected to gnd by combination, so that the differential voltage of the whole DAC will increase by 0.5V ref ；
Case three: if D is N-1 D N-2 ＝01，DAC P0 All but the most significant bit capacitance are connected to gnd by a combination, while the DAC N0 All the capacitors except the highest bit capacitor are connected to V by combination ref Reference voltage, so that the differential voltage of the whole DAC will be reduced by 0.5V ref ；
Case four: if D is N-1 D N-2 ＝00，DAC P0 All the capacitors except the highest bit capacitor are connected to V by combination ref Reference voltage, and DAC N0 All the capacitors except the most significant capacitor are connected to gnd by combination, so that the differential voltage of the whole DAC will be increased by 0.5V ref 。
In the step B3, according to the digital code D N-1 、D N-2 And D K The method comprises the following steps of controlling the connection relation of bottom plates of capacitors in an upper capacitor array and a lower capacitor array, specifically:
the first condition is as follows: if D is N-1 D N-2 D K ＝111，DAC P1 C of (A) K-1 The capacitor is connected to gnd, DAC N1 C of (A) K-1 The capacitor is connected to V ref Reference voltage, DAC P1 C of (A) K-2 Capacitor and DAC N1 C of (A) K-2 The capacitors are combined so that the differential voltage of the whole DAC will be reduced by 2 (K-N+1) V ref ；
Case two: if D is N-1 D N-2 D K ＝110，DAC P1 C of (A) K-2 Capacitor and DAC N1 C of (A) K-2 The capacitors are combined so that the differential voltage of the whole DAC will be increased by 2 (K-N+1) V ref ；
Case three: if D is N-1 D N-2 D K ＝101，DAC P1 C of (A) K-2 Capacitor and DAC N1 C of (A) K-2 The capacitors are combined so that the differential voltage of the whole DAC will be reduced by 2 (K-N+1) V ref ；
Case four: if D is N-1 D N-2 D K ＝100，DAC P1 C of (A) K-1 The capacitor is connected to V ref Reference voltage, DAC N1 C of (A) K-1 The capacitor is connected to gnd, DAC P1 C of (A) K-2 Capacitor and DAC N1 C of (A) K-2 The capacitors are combined so that the differential voltage of the whole DAC will be increased by 2 (K-N+1) V ref ；
Case five: if D is N-1 D N-2 D K ＝011，DAC P0 C of (A) K-1 The capacitor being connected to gnd, DAC N0 C of (A) K-1 The capacitor is connected to V ref Reference voltage, DAC P0 C of (A) K-2 Capacitor and DAC N0 C of (A) K-2 The capacitors are combined so that the differential voltage of the whole DAC will be reduced by 2 (K-N+1) V ref ；
Case six: if D is N-1 D N-2 D K ＝010，DAC P0 C of (A) K-2 Capacitor and DAC N0 C of (A) K-2 The capacitors are combined so that the differential voltage of the whole DAC will be increased by 2 (K-N+1) V ref ；
Case seven: if D is N-1 D N-2 D K ＝001，DAC P0 C of (A) K-2 Capacitor and DAC N0 C of (A) K-2 The capacitors are combined so that the differential voltage of the whole DAC is reduced by 2 (K-N+1) V ref ；
The eighth situation: if D is N-1 D N-2 D K ＝000，DAC P0 C of (A) K-1 The capacitor is connected to V ref Reference voltage, DAC N0 C of (A) K-1 The capacitor is connected to gnd, DAC P0 C of (A) K-2 Capacitor and DAC N0 C of (A) K-2 The capacitors are combined so that the differential voltage of the whole DAC will be increased by 2 (K-N+1) V ref ；
Wherein N is the digit of the analog-to-digital converter, K is the ordinal number of the currently obtained digital code, and K is more than or equal to 1 and less than or equal to N-3, that is, D is obtained from high to low in step B4 N-3 To D 1 And a plurality of digital codes.
In the step B4, according to the digital code D N-1 And D 1 The method comprises the following steps of controlling the connection relation of capacitor bottom plates in an upper capacitor array and a lower capacitor array, specifically:
the first condition is as follows: if D is N-1 D 1 ＝11，DAC P1 Capacitor C of 1 Uncombined and connected to gnd, DAC N1 Capacitor C of 1 From the merged state to the floating state, so that the differential voltage of the whole DAC is reduced by 2 (2-N) V ref ；
Case two: if D is N-1 D 1 ＝10，DAC P1 Capacitor C of 1 From a merged state to a floating state, DAC N1 Capacitor C of 1 Uncombined and connected to gnd so that the differential voltage of the whole DAC will increase by 2 (2-N) V ref ；
And a third situation: if D is N-1 D 1 ＝01，DAC P0 Capacitor C of 1 Uncombined and connected to gnd, DAC N0 Capacitor C of 1 From the merged state to the floating state, so that the differential voltage of the whole DAC is reduced by 2 (2-N) V ref ；
Case four: if D is N-1 D 1 ＝00，DAC P0 Capacitor C of 1 From a merged state to a floating state, DAC N0 Capacitor C of 1 Uncombined and connected to gnd so that the differential voltage of the whole DAC will increase by 2 (2-N) V ref ；
Wherein N is the number of bits of the analog-to-digital converter. Has the advantages that: by adopting the technical scheme, the invention can produce the following technical effects:
the method for switching the successive approximation analog-to-digital converter based on the semi-dormant structure provided by the invention is used for the first timeSwitching to produce + -V at the top plate of the capacitor ref Thus, the reference voltage V of the capacitor array under the same range condition ref The range of the ADC can be expanded to be twice of the normal range under the same reference voltage, and almost every step of switching is combined in the switching process, so that the power consumption of the DAC is further reduced; and a single-end switching algorithm is adopted only in the judgment of the last bit, so that the area of a capacitor is saved, and the common-mode level drift is reduced. Compared with the traditional switching algorithm, the invention reduces the power consumption of the capacitor DAC by 99.22%, saves the capacitor area by 75%, does not improve the requirements on other modules, and improves the integral energy efficiency of the SAR ADC.
Drawings
Fig. 1 is a schematic structural diagram of an SAR ADC used for realizing 10-bit resolution by the method of the present invention.
Fig. 2 is a schematic diagram of the switching of the 5-bit SAR ADC according to the present invention.
Fig. 3 is a diagram of the results of MATLAB simulation of the switching power consumption of a 10-bit SAR ADC as a function of the ADC output code (for comparison, V in the diagram is the CDAC reference voltage of most switching algorithms including the split-monotonic switching algorithm).
Detailed Description
The present invention will be further described with reference to the accompanying drawings.
The structure of a 10-bit successive approximation type analog-to-digital converter based on the method is shown in figure 1, and the method comprises two same sub analog-to-digital converters ADC 1 And ADC 0 Each sub-adc comprises a sampling switch 1, a capacitor array 2, a comparator 3 and digital control logic 4, wherein the capacitor array 2 comprises identical upper capacitor array DACs P1 、DAC N1 And lower capacitor array DAC P0 、DAC N0 (ii) a The input signal VIP is connected to the DAC through the sampling switch 1 P1 And DAC P0 The input signal VIN is connected to the DAC through the sampling switch 1 N1 And DAC N0 The top plate of (1); DAC P1 And DAC P0 The top plate of the DAC is connected with the non-inverting input end of the comparator N1 And DAC N0 The top plate of the comparator 3 is connected with the inverting input end of the comparator 3, and the differential output end of the comparator 3 generates a control signal to control the bottom plate switches of the upper capacitor array and the lower capacitor array through the digital control logic 4, so that the bottom plates of the upper capacitor array and the lower capacitor array are connected to corresponding voltages, combined, split or floated;
each sub-capacitor array is composed of a highest-order capacitor C N-4 And N-6 high-order capacitors and sub-low-order capacitor C 1 Lowest order capacitor C 0 And dummy capacitor C d The capacitor comprises the following capacitors: c i ＝2 i C, wherein i is more than or equal to 0 and less than or equal to N-4 d = C, where N represents the number of bits of the analog-to-digital converter and C is the unit capacitance size;
for input signals VIP and VIN, N-bit digital output codes are obtained after N times of comparison by an analog-to-digital converter, and the N-bit digital output codes are divided into two stages of sampling and conversion, specifically as follows:
step A, sampling stage
Input signals VIP and VIN are respectively connected to the ADC through sampling switches 1 And ADC 0 Top plate of capacitor array, ADC 1 Sub-capacitor array DAC P1 All capacitor bottom plates of (2) are connected to V ref Reference voltage, and sub-capacitor array DAC N1 All capacitor bottom plates of gnd are connected to gnd; ADC (analog to digital converter) 0 Sub-capacitor array DAC P0 All capacitor bottom plates of (2) are connected to gnd, and the sub-capacitor array DAC N0 All capacitor bottom plates of (2) are connected to V ref A reference voltage;
step B, transition phase
Step B1, switching off a sampling switch of the analog-to-digital converter, and then directly comparing input signals VIP and VIN held on top electrode plates of the upper capacitor array and the lower capacitor array by a comparator to obtain a most significant bit D N-1 According to digital code D N-1 Controlling the connection relation of the capacitor bottom plates in the upper capacitor array and the lower capacitor array so as to obtain a new top plate voltage;
the first condition is as follows: if D is N-1 ＝1，ADC 0 The ADC is switched to a dormant state, and the ADC is not switched again in the conversion process 0 Performing other operations, DAC P1 And DAC N1 All capacitor bottom plates are combined, so that the differential voltage of the whole DAC is reduced by V ref ；
Case two: if D is N-1 ＝0，ADC 1 The ADC is switched to a dormant state, and the ADC is not switched again in the conversion process 1 Performing other operations, DAC P0 And DAC N0 All capacitor bottom plates are combined, so that the differential voltage of the whole DAC is increased by V ref 。
Step B2, the comparator 3 compares the voltages of the top plates of the upper and lower capacitor arrays obtained in the step B1 to obtain a digital code D N-2 According to digital code D N-1 D N-2 Controlling the connection relation of the bottom plates of the capacitors in the upper and lower capacitor arrays;
the first condition is as follows: if D is N-1 D N-2 ＝11，DAC P1 All but the most significant bit capacitance are connected to gnd by a combination, while the DAC N1 All capacitances except the highest order capacitance are connected by a combination to V ref Reference voltage, so that the differential voltage of the whole DAC will be reduced by 0.5V ref ；
Case two: if D is N-1 D N-2 ＝10，DAC P1 All capacitances except the highest order capacitance are connected by a combination to V ref Reference voltage, and DAC N1 All the capacitors except the most significant capacitor are connected to gnd by combination, so that the differential voltage of the whole DAC will be increased by 0.5V ref ；
Case three: if D is N-1 D N-2 ＝01，DAC P0 All but the most significant bit capacitance are connected to gnd by a combination, while the DAC N0 All capacitances except the highest order capacitance are connected by a combination to V ref Reference voltage, so that the differential voltage of the whole DAC will be reduced by 0.5V ref ；
Case four: if D is N-1 D N-2 ＝00，DAC P0 All capacitances except the highest order capacitance are connected by a combination to V ref Reference voltage, and DAC N0 All but the highest order capacitance is formed byAre combined and connected to gnd so that the differential voltage of the whole DAC will increase by 0.5V ref 。
Step B3, the comparator compares the voltages of the top electrode plates of the upper capacitor array and the lower capacitor array obtained from the step B2 to obtain a digital code D K Wherein K is more than or equal to 1 and less than or equal to N-3 according to the digital code D N-1 And D N-2 And D K Controlling the connection relation of the bottom plates of the capacitors in the upper and lower capacitor arrays; and repeating the step B4 until a digital code D is obtained 1 ；
The first condition is as follows: if D is N-1 D N-2 D K ＝111，DAC P1 C of (A) K-1 The capacitor being connected to gnd, DAC N1 C of (A) K-1 The capacitor is connected to V ref Reference voltage, DAC P1 C of (A) K-2 Capacitor and DAC N1 C of (A) K-2 The capacitors are combined so that the differential voltage of the whole DAC is reduced by 2 (K-N+1) V ref ；
Case two: if D is N-1 D N-2 D K ＝110，DAC P1 C of (A) K-2 Capacitor and DAC N1 C of (A) K-2 The capacitors are combined so that the differential voltage of the whole DAC will be increased by 2 (K-N+1) V ref ；
And a third situation: if D is N-1 D N-2 D K ＝101，DAC P1 C of (A) K-2 Capacitor and DAC N1 C of (A) K-2 The capacitors are combined so that the differential voltage of the whole DAC will be reduced by 2 (K-N+1) V ref ；
Case four: if D is N-1 D N-2 D K ＝100，DAC P1 C of (A) K-1 The capacitor is connected to V ref Reference voltage, DAC N1 C of (A) K-1 The capacitor being connected to gnd, DAC P1 C of (A) K-2 Capacitor and DAC N1 C of (A) K-2 The capacitors are combined so that the differential voltage of the whole DAC will be increased by 2 (K-N+1) V ref ；
Case five: if D is N-1 D N-2 D K ＝011，DAC P0 C of (A) K-1 The capacitor being connected to gnd, DAC N0 C of (A) K-1 The capacitor is connected to V ref Reference voltage, DAC P0 C of (A) K-2 Capacitor and DAC N0 C of (A) K-2 The capacitors are combined so that the differential voltage of the whole DAC will be reduced by 2 (K-N+1) V ref ；
Case six: if D is N-1 D N-2 D K ＝010，DAC P0 C of (A) K-2 Capacitor and DAC N0 C of (A) K-2 The capacitors are combined so that the differential voltage of the whole DAC will be increased by 2 (K-N+1) V ref ；
Case seven: if D is N-1 D N-2 D K ＝001，DAC P0 C of (A) K-2 Capacitor and DAC N0 C of (A) K-2 The capacitors are combined so that the differential voltage of the whole DAC will be reduced by 2 (K-N+1) V ref ；
Case eight: if D is N-1 D N-2 D K ＝000，DAC P0 C of (A) K-1 The capacitor is connected to V ref Reference voltage, DAC N0 C of (A) K-1 The capacitor is connected to gnd, DAC P0 C of (A) K-2 Capacitor and DAC N0 C of (A) K-2 The capacitors are combined so that the differential voltage of the whole DAC will be increased by 2 (K-N+1) V ref ；
Wherein N is the digit of the analog-to-digital converter, K is the ordinal number of the currently obtained digital code, and K is more than or equal to 1 and less than or equal to N-3, that is, D is obtained in sequence from high to low in step B4 N-3 To D 1 And a plurality of digital codes.
Step B4, according to the digital code D N-1 And D 1 Controlling the connection relation of the bottom plates of the capacitors in the upper and lower capacitor arrays, and comparing the voltages of the top plates of the upper and lower capacitor arrays by the comparator to obtain a digital code D 0 。
The first condition is as follows: if D is N-1 D 1 ＝11，DAC P1 Capacitor C of 1 Uncombined and connected to gnd, DAC N1 Capacitor C of 1 From the merged state to the floating state, so that the differential voltage of the whole DAC is reduced by 2 (2-N) V ref ；
And a second condition: if D is N-1 D 1 ＝10，DAC P1 Capacitor C of 1 From merged state to floatingState, DAC N1 Capacitor C of 1 De-merge and connect to gnd so that the differential voltage of the whole DAC will increase by 2 (2-N) V ref ；
Case three: if D is N-1 D 1 ＝01，DAC P0 Capacitor C of 1 Uncombined and connected to gnd, DAC N0 Capacitor C of 1 From the merged state to the floating state, so that the differential voltage of the whole DAC is reduced by 2 (2-N) V ref ；
Case four: if D is N-1 D 1 ＝00，DAC P0 Capacitor C of 1 From a merged state to a floating state, DAC N0 Capacitor C of 1 Uncombined and connected to gnd so that the differential voltage of the whole DAC will increase by 2 (2-N) V ref ；
Wherein N is the number of bits of the analog-to-digital converter.
The differential output end of the comparator generates a control signal to control the bottom plate switches of the upper and lower capacitor arrays after passing through the digital control logic, so that the bottom plate switches are connected to corresponding reference voltages, combined, split and floated. Through the special construction of the core module capacitor array and the combination of the provided novel switching algorithm, the power consumption of a DAC part in the conversion process can be greatly reduced, the capacitor area is saved, and the common-mode level drift is reduced.
The invention will be described in more detail below with reference to an example, since D N-1 =1 and D N-1 In the case of =0, the process of quantizing the dialing capacitance from MSB to LSB bit is completely symmetrical, and to avoid redundant description, let D N-1 =1, fig. 2 shows a specific conversion process of the 5-bit SAR ADC according to the embodiment of the present invention:
step A, sampling stage
Input signals VIP and VIN are respectively connected to the top plates of ADC1 and ADC0 capacitor arrays through sampling switches, and the sub-capacitor array DAC of ADC1 P1 All capacitor bottom plates of (2) are connected to V ref Reference voltage, and sub-capacitor array DAC N1 All capacitor bottom plates of gnd are connected to gnd; sub-capacitor array DAC of ADC0 P0 All capacitor bottom plates of (2) are connected to gnd, and sub-electrodesCapacitor array DAC N0 All capacitor bottom plates of (2) are connected to V ref A reference voltage;
step B, transition phase
Step B1, switching off a sampling switch of the analog-to-digital converter, and then directly comparing input signals VIP and VIN held on the top plates of the upper and lower capacitor arrays by a comparator to obtain a digital code D 4 According to digital codes D 4 Controlling the connection relation of the bottom plates of the capacitors in the upper and lower capacitor arrays;
due to D 4 ＝1，ADC 0 The ADC is switched to a dormant state, and the ADC is not subjected to conversion again 0 Performing other operations, DAC P1 And DAC N1 All capacitor bottom plates are combined, so that the differential voltage of the whole DAC is reduced by V ref ；
Step B2, the comparator compares the voltages of the top plates of the upper and lower capacitor arrays obtained in the step B1 to obtain a digital code D 4 According to digital code D 4 D 3 Controlling the connection relation of the bottom plates of the capacitors in the upper and lower capacitor arrays;
the first condition is as follows: if D is 4 D 3 ＝11，DAC P1 All but the most significant bit capacitance are connected to gnd by a combination, while the DAC N1 All capacitances except the highest order capacitance are connected by a combination to V ref Reference voltage, so that the differential voltage of the whole DAC will be reduced by 0.5V ref ；
And a second condition: if D is 4 D 3 ＝10，DAC P1 All capacitances except the highest order capacitance are connected by a combination to V ref Reference voltage, and DAC N1 All the capacitors except the most significant capacitor are connected to gnd by combination, so that the differential voltage of the whole DAC will be increased by 0.5V ref ；
Step B3, the comparator compares the voltages of the upper and lower capacitor array top plates obtained in the step B2 to obtain a digital code D K Wherein K is more than or equal to 1 and less than or equal to 2 according to the digital code D 4 D 3 And D K Controlling the connection relation of the bottom plates of the capacitors in the upper and lower capacitor arrays; and repeating the step B4 until a digital code D is obtained 1 ；
The first condition is as follows: if D is 4 D 3 D 2 ＝111，DAC P1 C of (A) 1 The capacitor being connected to gnd, DAC N1 C of (A) 1 The capacitor is connected to V ref Reference voltage, DAC P1 C of (A) 0 Capacitor and DAC N1 C of (A) 0 The capacitors are combined, so that the differential voltage of the whole DAC is reduced by 0.25V ref ；
Case two: if D is 4 D 3 D 2 ＝110，DAC P1 C of (A) 0 Capacitor and DAC N1 C of (A) 0 The capacitors are combined, so that the differential voltage of the whole DAC is increased by 0.25V ref ；
Case three: if D is 4 D 3 D 2 ＝101，DAC P1 C of (A) 0 Capacitor and DAC N1 C of (A) 0 The capacitors are combined, so that the differential voltage of the whole DAC is reduced by 0.25V ref ；
Case four: if D is 4 D 3 D 2 ＝100，DAC P1 C of (A) 1 The capacitor is connected to V ref Reference voltage, DAC N1 C of (A) 1 The capacitor is connected to gnd, DAC P1 C of (A) 0 Capacitor and DAC N1 C of (A) 0 The capacitors are combined, so that the differential voltage of the whole DAC is increased by 0.25V ref ；
Step B4, according to the digital code D 4 And D 1 Controlling the connection relation of the bottom plates of the capacitors in the upper and lower capacitor arrays, and comparing the voltages of the top plates of the upper and lower capacitor arrays by the comparator to obtain a digital code D 0 。
The first condition is as follows: if D is 4 D 1 ＝11，DAC P1 Capacitor C of 1 Uncombined and connected to gnd, DAC N1 Capacitor C of 1 From the merged state to the floating state, so that the differential voltage of the whole DAC is reduced by 2 (-3) V ref ；
Case two: if D is 4 D 1 ＝10，DAC P1 Capacitor C of 1 From a merged state to a floating state, DAC N1 Capacitor C of 1 Uncombined and connected to gnd so that the differential voltage of the whole DAC will increase by 2 (-3) V ref ；
As shown in fig. 3, the MATLAB simulation result graph is applied to the switching and resetting power consumption of the 10-bit SAR ADC, which varies with the ADC output code, and the invention can reduce the power consumption of the capacitor DAC by 99.22%, save the capacitor area by 75%, have no improvement on the requirements of other modules, and improve the overall energy efficiency of the SAR ADC.
In summary, the method of the present invention utilizes the first switching of V ref The voltage change and the multiple combined operation reduce the power consumption of the CDAC switch, and improve the integral energy efficiency of the SAR ADC.
The above description is only of the preferred embodiments of the present invention, and it should be noted that: it will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the principles of the invention and these are intended to be within the scope of the invention.

Claims (7)

1. A switching method of a successive approximation analog-to-digital converter based on a semi-dormant structure is characterized by comprising the following steps: the method is based on an analog-to-digital converter comprising two identical sub-analog-to-digital converters (ADCs) 1 And ADC 0 Each sub analog-digital converter comprises a sampling switch (1), a capacitor array (2), a comparator (3) and digital control logic (4), wherein the capacitor array (2) comprises identical upper capacitor array DACs P1 、DAC N1 And lower capacitor array DAC P0 、DAC N0 (ii) a The input signal VIP is connected to the DAC via a sampling switch (1) P1 And DAC P0 The input signal VIN is connected to the DAC through the sampling switch (1) N1 And DAC N0 The top plate of (1); DAC P1 And DAC P0 The top plate of the DAC is connected with the non-inverting input end of the comparator (3) N1 And DAC N0 The top electrode plate of the capacitor is connected with the inverting input end of a comparator (3), and the differential output end of the comparator (3) generates a control signal through a digital control logic (4) to control the bottom electrode plate switches of the upper capacitor array and the lower capacitor array, so that the bottom electrode plates of the upper capacitor array and the lower capacitor array are connected to corresponding voltages and are combined, split or floated;
each sub-capacitor array consists ofA highest order capacitor C N-4 And N-6 high-order capacitors and sub-low-order capacitor C 1 Lowest order capacitor C 0 And dummy capacitor C d The capacitor comprises the following capacitors: c i ＝2 i C, wherein i is more than or equal to 0 and less than or equal to N-4 d = C, where N represents the number of bits of the analog-to-digital converter and C is the unit capacitance size;
the method comprises the following steps: for input signals VIP and VIN, N-bit digital output codes are obtained after N times of comparison of an analog-to-digital converter, and the N-bit digital output codes are divided into two stages of sampling and conversion; in the sampling stage, input signals VIP and VIN are connected to top electrode plates of upper and lower capacitor arrays of the two sub analog-to-digital converters through sampling switches, and bottom electrode plates of each capacitor are connected to corresponding voltages; in the conversion stage, the comparator compares MSB bit to LSB bit of the top plate voltage of the upper and lower capacitor arrays to obtain corresponding digital codes to control the state of the bottom plate of each capacitor; obtaining N-bit digital code through N times of comparison.
2. The method of claim 1, wherein the successive approximation analog-to-digital converter switching method based on the semi-sleep structure comprises: the sampling phase comprises the following steps:
input signals VIP and VIN are respectively connected to the ADC through a sampling switch (1) 1 And ADC 0 Top plate of capacitor array, ADC 1 Sub-capacitor array DAC P1 All capacitor bottom plates of (2) are connected to V ref Reference voltage, and sub-capacitor array DAC N1 All capacitor bottom plates of gnd are connected to gnd; ADC (analog to digital converter) 0 Sub-capacitor array DAC P0 All capacitor bottom plates of (2) are connected to gnd, and the sub-capacitor array DAC N0 All capacitor bottom plates of (2) are connected to V ref A reference voltage.
3. The method of claim 1, wherein the successive approximation analog-to-digital converter switching method based on the semi-sleep structure comprises: the transition phase comprises the steps of:
step B1, a sampling switch (1) of the analog-to-digital converter is switched off, and then a comparator (3) directly controls top pole plates of an upper capacitor array and a lower capacitor arrayCompares the input signals VIP and VIN to obtain the most significant bit D N-1 According to digital code D N-1 Controlling the connection relation of the capacitor bottom plates in the upper capacitor array and the lower capacitor array so as to obtain a new top plate voltage;
step B2, the comparator (3) compares the voltages of the top plates of the upper and lower capacitor arrays obtained in the step B1 to obtain a digital code D N-2 According to digital code D N-1 And D N-2 Controlling the connection relation of the capacitor bottom plates in the upper capacitor array and the lower capacitor array so as to obtain a new top plate voltage;
step B3, the comparator (3) compares the voltages of the top electrode plates of the upper capacitor array and the lower capacitor array obtained from the step B2 to obtain a digital code D K Where K is greater than or equal to 1 and less than or equal to N-3, according to the digital code D N-1 And D N-2 And D K Controlling the connection relation of the bottom plates of the capacitors in the upper and lower capacitor arrays; and repeating the step B4 until a digital code D is obtained 1 ；
Step B4, according to the digital code D N-1 And D 1 The connection relation of the bottom electrode plates of the capacitors in the upper and lower capacitor arrays is controlled, and the comparator (3) compares the voltages of the top electrode plates of the upper and lower capacitor arrays at the moment to obtain a digital code D 0 。
4. The method of claim 3, wherein the successive approximation analog-to-digital converter switching method based on the semi-sleep structure comprises: in the step B1, according to the digital code D N-1 The control of the connection relation of the capacitor bottom plates in the upper and lower capacitor arrays is specifically as follows:
the first condition is as follows: if D is N-1 ＝1，ADC 0 The ADC is switched to a dormant state, and the ADC is not switched again in the conversion process 0 Performing other operations, DAC P1 And DAC N1 All capacitor bottom plates are combined, so that the differential voltage of the whole DAC is reduced by V ref ；
Case two: if D is N-1 ＝0，ADC 1 The ADC is switched to a dormant state, and the ADC is not subjected to conversion again 1 Performing other operations, DAC P0 And DAC N0 All capacitor bottom plates are combined, so that the differential voltage of the whole DACIncrease of V ref 。
5. The method of claim 3, wherein the successive approximation analog-to-digital converter switching method based on the semi-sleep structure comprises: in the step B2, according to the digital code D N-1 And D N-2 The method comprises the following steps of controlling the connection relation of bottom plates of capacitors in an upper capacitor array and a lower capacitor array, specifically:
the first condition is as follows: if D is N-1 D N-2 ＝11，DAC P1 All capacitances except the most significant bit capacitance are connected to gnd by a combination, and the DAC N1 All capacitances except the highest order capacitance are connected by a combination to V ref Reference voltage, so that the differential voltage of the whole DAC will be reduced by 0.5V ref ；
Case two: if D is N-1 D N-2 ＝10，DAC P1 All capacitances except the highest order capacitance are connected by a combination to V ref Reference voltage, and DAC N1 All the capacitors except the most significant capacitor are connected to gnd by combination, so that the differential voltage of the whole DAC will be increased by 0.5V ref ；
Case three: if D is N-1 D N-2 ＝01，DAC P0 All but the most significant bit capacitance are connected to gnd by a combination, while the DAC N0 All capacitances except the highest order capacitance are connected by a combination to V ref Reference voltage, so that the differential voltage of the whole DAC will be reduced by 0.5V ref ；
Case four: if D is N-1 D N-2 ＝00，DAC P0 All capacitances except the highest order capacitance are connected by a combination to V ref Reference voltage, and DAC N0 All the capacitors except the most significant capacitor are connected to gnd by combination, so that the differential voltage of the whole DAC will be increased by 0.5V ref 。
6. The method of claim 3, wherein the method comprises: in the step B3, according to the digital code D N-1 、D N-2 And D K The method comprises the following steps of controlling the connection relation of capacitor bottom plates in an upper capacitor array and a lower capacitor array, specifically:
the first condition is as follows: if D is N-1 D N-2 D K ＝111，DAC P1 C of (A) K-1 The capacitor being connected to gnd, DAC N1 C of (A) K-1 The capacitor is connected to V ref Reference voltage, DAC P1 C of (A) K-2 Capacitor and DAC N1 C of (A) K-2 The capacitors are combined so that the differential voltage of the whole DAC will be reduced by 2 (K-N+1) V ref ；
Case two: if D is N-1 D N-2 D K ＝110，DAC P1 C of (A) K-2 Capacitor and DAC N1 C of (A) K-2 The capacitors are combined so that the differential voltage of the whole DAC will be increased by 2 (K-N+1) V ref ；
And a third situation: if D is N-1 D N-2 D K ＝101，DAC P1 C of (A) K-2 Capacitor and DAC N1 C of (A) K-2 The capacitors are combined so that the differential voltage of the whole DAC will be reduced by 2 (K-N+1) V ref ；
Case four: if D is N-1 D N-2 D K ＝100，DAC P1 C of (A) K-1 The capacitor is connected to V ref Reference voltage, DAC N1 C of (A) K-1 The capacitor being connected to gnd, DAC P1 C of (A) K-2 Capacitor and DAC N1 C of (A) K-2 The capacitors are combined so that the differential voltage of the whole DAC will be increased by 2 (K-N+1) V ref ；
Case five: if D is N-1 D N-2 D K ＝011，DAC P0 C of (A) K-1 The capacitor being connected to gnd, DAC N0 C of (A) K-1 The capacitor is connected to V ref Reference voltage, DAC P0 C of (A) K-2 Capacitor and DAC N0 C of (A) K-2 The capacitors are combined so that the differential voltage of the whole DAC will be reduced by 2 (K-N+1) V ref ；
Case six: if D is N-1 D N-2 D K ＝010，DAC P0 C of (A) K-2 Capacitor and DAC N0 C of (A) K-2 The capacitors are combined so that the differential voltage of the whole DAC will be increased by 2 (K-N+1) V ref ；
Case seven: if D is N-1 D N-2 D K ＝001，DAC P0 C of (A) K-2 Capacitor and DAC N0 C of (A) K-2 The capacitors are combined so that the differential voltage of the whole DAC will be reduced by 2 (K-N+1) V ref ；
The eighth situation: if D is N-1 D N-2 D K ＝000，DAC P0 C of (A) K-1 The capacitor is connected to V ref Reference voltage, DAC N0 C of (A) K-1 The capacitor being connected to gnd, DAC P0 C of (A) K-2 Capacitor and DAC N0 C of (A) K-2 The capacitors are combined so that the differential voltage of the whole DAC will be increased by 2 (K-N+1) V ref ；
Wherein N is the digit of the analog-to-digital converter, K is the ordinal number of the currently obtained digital code, and K is more than or equal to 1 and less than or equal to N-3, that is, D is obtained in sequence from high to low in step B4 N-3 To D 1 And a plurality of digital codes.
7. The method of claim 3, wherein the successive approximation analog-to-digital converter switching method based on the semi-sleep structure comprises: in the step B4, according to the digital code D N-1 And D 1 The method comprises the following steps of controlling the connection relation of bottom plates of capacitors in an upper capacitor array and a lower capacitor array, specifically:
the first condition is as follows: if D is N-1 D 1 ＝11，DAC P1 Capacitor C of 1 Uncombined and connected to gnd, DAC N1 Capacitor C of 1 From the merged state to the floating state, so that the differential voltage of the whole DAC is reduced by 2 (2-N) V ref ；
Case two: if D is N-1 D 1 ＝10，DAC P1 Capacitor C of 1 From a merged state to a floating state, DAC N1 Capacitor C of 1 Uncombined and connected to gnd so that the differential voltage of the whole DAC will increase by 2 (2-N) V ref ；
And a third situation: if D is N-1 D 1 ＝01，DAC P0 Capacitor C of 1 Uncombined and connected to gnd, DAC N0 Capacitor C of 1 From merged state to floatingState such that the differential voltage of the entire DAC will be reduced by 2 (2-N) V ref ；
Case four: if D is N-1 D 1 ＝00，DAC P0 Capacitor C of 1 From merged to floating state, DAC N0 Capacitor C of 1 Uncombined and connected to gnd so that the differential voltage of the whole DAC will increase by 2 (2-N) V ref ；
Wherein, N is the digit of the analog-digital converter.
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Publication number Priority date Publication date Assignee Title
CN110380730A (en) * 2019-07-04 2019-10-25 东南大学 A kind of capacitor array method of switching applied to low-voltage SAR ADC
CN112332847A (en) * 2020-12-07 2021-02-05 东南大学 Two-level switching method applied to successive approximation type analog-to-digital converter
CN112583409A (en) * 2020-12-28 2021-03-30 东南大学 Successive approximation type analog-to-digital converter and three-level switching method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110380730A (en) * 2019-07-04 2019-10-25 东南大学 A kind of capacitor array method of switching applied to low-voltage SAR ADC
CN112332847A (en) * 2020-12-07 2021-02-05 东南大学 Two-level switching method applied to successive approximation type analog-to-digital converter
CN112583409A (en) * 2020-12-28 2021-03-30 东南大学 Successive approximation type analog-to-digital converter and three-level switching method thereof

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