CN113810053A

CN113810053A - Bypass window switching method applied to successive approximation type analog-to-digital converter

Info

Publication number: CN113810053A
Application number: CN202111072372.1A
Authority: CN
Inventors: 吴建辉; 周畅; 黄琳琳; 黄毅; 罗斯婕; 李红
Original assignee: Southeast University
Current assignee: Southeast University
Priority date: 2021-09-14
Filing date: 2021-09-14
Publication date: 2021-12-17
Anticipated expiration: 2041-09-14
Also published as: CN113810053B

Abstract

The invention discloses a bypass window switching method applied to a successive approximation type analog-to-digital converter. The method comprises three stages of sampling, converting and splicing, wherein differential input voltages VIP and VIN are connected to a top plate of a capacitor array through a sampling switch, a comparator compares the voltage of the top plate of the capacitor array to obtain a corresponding digital code, and the connection of a bottom plate of the capacitor array is controlled according to the digital code; the invention switches to generate a bypass window on the top plate of the capacitor for the first time, and obtains N-digit digital codes after splicing the codes only by N-2 times of comparison in the window, and obtains the N-digit digital codes after splicing the codes by N +1 times of comparison outside the window. Compared with the traditional switching algorithm, the invention reduces the CDAC power consumption, reduces the DAC power consumption of the input voltage in the window, saves half of the capacitor area, and realizes the compromise of energy efficiency and area.

Description

Bypass window switching method applied to successive approximation type analog-to-digital converter

Technical Field

The invention relates to a bypass window switching method applied to a successive approximation type analog-to-digital converter, and belongs to the technical field of capacitance type digital-to-analog converters of successive approximation type analog-to-digital converters.

Background

Sensors that can work for a long time are needed in the fields of internet of things, wearable devices and the like, and the use of Analog-to-digital converters (ADCs) by sensor interfaces is extremely frequent. Due to the lifetime requirements, ADCs need to be low power consuming. Successive approximation register analog-to-digital converter (sar adc) is widely used at low voltage due to high digitization and energy efficiency. The commonly used SAR adc structure includes a sampling switch, a capacitive digital to analog converter (CDAC), a comparator, SAR logic and an output circuit, and at low speed, the switching power consumption consumed by the CDAC accounts for a large proportion of the overall power consumption.

In prior studies, various switching algorithms have been proposed to reduce the switching power consumption of CDACs. However, the method introduces an additional interstage error [1] and a plurality of comparators [2] while reducing the switching power consumption, and finally, the reduction of the power consumption of a Digital to analog converter (DAC) is not ideal or higher requirements are put on design indexes of other modules such as the comparators.

[1]H.-Y.Tai,Y.-S.Hu,H.-W.Chen,and H.-S.Chen,“A 0.85fJ/conversion step 10b 200kS/s subranging SAR ADC in 40nmCMOS,”in IEEE ISSCC Dig.Tech.Papers,Feb.2014,pp.196–197.

[2]G.-Y.Huang,S.-J.Chang,C.-C.Liu,and Y.-Z.Lin,“A1-μW 10-bit 200-kS/s SAR ADC with a bypass window for biomedical applications,”in IEEE J.Solid-State Circuits,vol.47,no.11,pp.2783–2795,Nov.2012.

Disclosure of Invention

The purpose of the invention is as follows: in order to solve the problem of low power consumption and additional error introduction in the design of SAR ADC compromise, the invention provides a bypass window applied to a successive approximation type analog-to-digital converterThe first switching can be performed by using the capacitance switching to generate +/-2 on the top plate of the capacitor^-3The voltage change of the Vref judges whether the input voltage is in the window, and if the input voltage is in the window, the previous two times of high-order capacitance switching are skipped, so that the conversion period of the SAR ADC is reduced, and the power consumption is reduced; if the capacitor is outside the window, the capacitors are continuously compared and switched according to the digital codes, and continuous capacitors are prevented from being switched back through code splicing, so that the power consumption is reduced.

The technical scheme is as follows: in order to achieve the above object, the present invention provides a bypass window switching method applied to a successive approximation type analog-to-digital converter, wherein the analog-to-digital converter includes a sampling switch, a capacitor array, a comparator, a digital control logic circuit and a code spelling device, wherein the capacitor array includes an upper capacitor array and a lower capacitor array having the same structure; differential input voltages, namely positive end input voltage and negative end input voltage, are respectively connected to the top pole plates of the upper capacitor array and the lower capacitor array through the sampling switches; the top plate of the upper capacitor array is connected with the non-inverting input end of the comparator, and the top plate of the lower capacitor array is connected with the inverting input end of the comparator; the differential output end of the comparator is connected to the digital control logic circuit, the digital control logic circuit generates a control signal to control the bottom electrode plates of the upper capacitor array and the lower capacitor array to be connected to corresponding levels, and the code spelling device spells each digital code output by the digital control logic circuit to generate a converted digital code;

the upper capacitor array comprises a first upper sub capacitor array, a second first upper sub capacitor array and a second upper sub capacitor array; the lower capacitor array comprises a first lower sub capacitor array, a second lower sub capacitor array and a second lower sub capacitor array;

the bypass window switching method applied to the successive approximation type analog-to-digital converter comprises the following steps:

step A, a sampling stage:

all capacitor bottom plates of the first upper sub capacitor array and the second one upper sub capacitor array of the upper capacitor array are connected to the ground level, and all capacitor bottom plates of the second one upper sub capacitor array are connected to the reference voltage; all the capacitor bottom plates of the first lower sub capacitor array and the second lower sub capacitor array of the lower capacitor array are connected to the ground level, and all the capacitor bottom plates of the second lower sub capacitor array are connected to the reference voltage;

step B, a conversion stage:

step B1, the sampling switch is switched off, then the comparator directly compares the input voltage of the positive end and the input voltage of the negative end of the top polar plate of the upper capacitor array and the lower capacitor array to obtain the digital code D_NWhere N represents the number of bits of the analog-to-digital converter and the digital control logic circuit is based on the digital code D_NControlling the connection position of the bottom plate of the capacitor in the upper capacitor array and the lower capacitor array;

step B2, the comparator compares the voltage of the top electrode plate of the upper capacitor array and the voltage of the bottom electrode plate of the lower capacitor array obtained from the step B1 to obtain a digital code D_WINAccording to digital code D_NAnd D_WINJudging whether the differential input voltage is in a bypass window or not so as to control the connection position of the bottom plates of the capacitors in the upper capacitor array and the lower capacitor array;

step B3, the comparator compares the top plate voltages of the upper capacitor array and the lower capacitor array obtained from step B2 to obtain a digital code D within the bypass window_N-4Within the bypass window according to the digital code D_N、D_WINAnd D_N-4Controlling the connection position of the bottom plate of the capacitor in the upper capacitor array and the lower capacitor array; obtaining digital codes D outside of bypass windows_N-1Outside the bypass window according to the digital code D_N、D_WINAnd D_N-1Controlling the connection position of the bottom plate of the capacitor in the upper capacitor array and the lower capacitor array;

step B4, the comparator compares the top plate voltages of the upper capacitor array and the lower capacitor array obtained from step B3 to obtain a digital code D within the bypass window_N-5In the bypass window according to the digital code D_N、D_WIN、D_N-4And D_N-5Controlling the connection position of the bottom plate of the capacitor in the upper capacitor array and the lower capacitor array; deriving digital codes D outside the bypass window_N-2Outside the bypass window according to the digital code D_N、D_WIN、D_N-1And D_N-2Controlling the connection position of the bottom plate of the capacitor in the upper capacitor array and the lower capacitor array;

step B5, the comparator compares the voltage of the top plate of the upper capacitor array and the voltage of the bottom plate of the lower capacitor array obtained from step B4 to obtain a digital code D in the bypass window_N-Kiw-1In which K is_iwFor the number of switching steps in the window, K is not less than 5_iwLess than or equal to N-3 according to the digital code D_N-Kiw-1Controlling the connection position of the bottom plate of the capacitor in the upper capacitor array and the lower capacitor array; and repeating the operation in the bypass window in the step B5 until the digital code D is obtained₁(ii) a Outside the bypass window, two extreme cases are D_ND_WIND_N-1D_N-20000 or 1111, the digital code D is skipped_N-Kow1+2To obtain a digital code D_N-Kow1+1，K_ow1For the number of steps of switching in the extreme case outside the bypass window, K is not less than 5_ow1Less than or equal to N-1 according to the digital code D_N-Kow1+1Controlling the connection position of the bottom plate of the capacitor in the upper capacitor array and the lower capacitor array, and repeating the operation outside the bypass window in the step B5 until the digital code D is obtained₁(ii) a Other non-limiting cases, to obtain digital code D_N-Kow2+2，K_ow2For the number of steps of switching in the non-limiting case outside the bypass window, K is not less than 5_ow2Less than or equal to N according to the digital code D_N-Kow2+2Controlling the connection position of the bottom plate of the capacitor in the upper capacitor array and the lower capacitor array, and repeating the operation outside the bypass window in the step B5 until the digital code D is obtained₁；

Step C, code spelling:

the digital control logic circuit outputs the digital codes of the comparator to the code spelling device, and the code spelling device spells the codes of the digital codes to obtain the converted N-bit digital codes.

Wherein the content of the first and second substances,

the first upper sub capacitor array and the second upper sub capacitor array are split capacitor arrays of high four-bit capacitors, wherein the capacitance value of the highest bit capacitor on the first upper sub capacitor array is 2^N-3C, the capacitance value of the first last-time high-order capacitor of the second capacitor is 2^N- ⁴C, the capacitance value of the first last-time low-order capacitor of the second capacitor is 2^N-5C, the capacitance value of the lowest bit capacitor on the second one is 2^N-6C, wherein N represents the digit of the analog-to-digital converter, and C is a unit capacitance value; the first upper sub capacitor array is a low-order capacitor, wherein the first upper N-9-order capacitor is a virtual capacitor, the capacitance value is 1C, and the capacitance value of the first upper N-4-order capacitor is 2^N-6C, the capacitance value of the first upper N-5 bit capacitor is 2^N-7C, the capacitance value of the first upper N-6 bit capacitor is 2^N-8C, the capacitance value of the first upper N-7 bit capacitor is 2^N-9And C, the capacitance value of the first upper N-8 bit capacitor is 1C.

The digital control logic circuit in step B1 is based on the digital code D_NControlling the connection position of the bottom plate of the capacitor in the upper capacitor array and the lower capacitor array specifically comprises:

the first condition is as follows: if D is_N1, the second last lower capacitor bottom plate is connected to the ground level by the reference voltage, the second next lower capacitor bottom plate is connected to the reference voltage by the ground level, and the differential voltage on the top plate of the capacitor array is reduced by 2^(-3)V_refForm a 0 to 2^(-3)V_refBy-pass window of (2), wherein V_refIs a reference voltage;

case two: if D is_N0, the bottom plate of the first last low-order capacitor is connected to the reference voltage by the ground level, the bottom plate of the second next low-order capacitor is connected to the ground level by the reference voltage, and the differential voltage on the top plate of the capacitor array is increased by 2^(-3)V_refForm a value of 0 to-2^(-3)V_refThe bypass window of (1).

According to the digital code D in the step B2_NAnd D_WINJudging whether the differential input voltage is in a bypass window or not so as to control the connection position of the bottom plates of the capacitors in the upper capacitor array and the lower capacitor array, wherein the method specifically comprises the following steps:

the first condition is as follows: if D is_ND_WINThe difference input voltage is explained in the bypass window 0-2 ═ 11^(-3)V_refBesides, the bottom plate of the second upper highest-order capacitor is connected to the ground level by the reference voltage, the bottom plate of the second lower highest-order capacitor is connected to the reference voltage by the ground level,differential voltage reduction on top plate of capacitor array 2^(-1)V_ref；

Case two: if D is_ND_WIN10, the differential input voltage is explained in the bypass window 0-2^(-3)V_refWithin, skip digital code D_N-1、D_N-2The bottom plate of the capacitor at the lowest position on the second capacitor is connected to a reference voltage by a ground level, the bottom plate of the capacitor at the lowest position on the second capacitor is connected to the ground level by the reference voltage, and the differential voltage on the top plate of the capacitor array is increased by 2^(-4)V_ref；

Case three: if D is_ND_WIN01, the differential input voltage is explained in the bypass windows 0 to-2^(-3)V_refWithin, skip digital code D_N-1、D_N-2The bottom plate of the second capacitor with the lowest position on the two upper sides is connected to the ground level by the reference voltage, the bottom plate of the second capacitor with the lowest position on the two lower sides is connected to the reference voltage by the ground level, and the differential voltage on the top plate of the capacitor array is reduced by 2^(-4)V_ref；

Case four: if D is_ND_WIN00, the differential input voltage is illustrated in the bypass windows 0 to-2^(-3)V_refBesides, the bottom plate of the capacitor at the highest position on the first capacitor is connected to the reference voltage by the ground level, the bottom plate of the capacitor at the highest position on the second capacitor is connected to the ground level by the reference voltage, and the differential voltage on the top plate of the capacitor array is increased by 2^(-1)V_ref。

Step B3, according to digital code D, within the bypass window_N、D_WINAnd D_N-4Controlling the connection position of the bottom plate of the capacitor in the upper capacitor array and the lower capacitor array, specifically:

the first condition is as follows: if D is_ND_WIND_N-4101, the first lower N-4 bit capacitor bottom plate is connected to the reference voltage by ground level, and the differential voltage on the capacitor array top plate is reduced by 2^(-5)V_ref；

Case two: if D is_ND_WIND_N-4100, the first upper N-4 bit capacitor bottom plate is connected to the reference voltage by ground level, the difference on the capacitor array top platePartial voltage increase 2^(-5)V_ref；

Case three: if D is_ND_WIND_N-4011, the first lower N-4 bit capacitor bottom plate is connected to the reference voltage from ground level, the differential voltage on the capacitor array top plate is reduced by 2^(-5)V_ref；

Case four: if D is_ND_WIND_N-4010, the first upper N-4 bit capacitor bottom plate is connected from ground to a reference voltage, and the differential voltage on the capacitor array top plate is increased by 2^(-5)V_ref；

Step B3, according to the digital code D, outside the bypass window_N、D_WINAnd D_N-1Controlling the connection position of the bottom plate of the capacitor in the upper capacitor array and the lower capacitor array, specifically:

case five: if D is_ND_WIND_N-1111, the second last higher capacitor bottom plate is connected to ground by the reference voltage, the second next higher capacitor bottom plate is connected to the reference voltage by the ground, the differential voltage on the top plate of the capacitor array is decreased by 2^(-2)V_ref；

Case six: if D is_ND_WIND_N-1110, the second one of the last higher capacitor bottom plates is connected to the reference voltage by the ground level, the second two of the next higher capacitor bottom plates is connected to the ground level by the reference voltage, and the differential voltage on the top plate of the capacitor array is increased by 2^(-2)V_ref；

Case seven: if D is_ND_WIND_N-1001, the second last high-order capacitor bottom plate is connected to ground by a reference voltage, the second next high-order capacitor bottom plate is connected to the reference voltage by the ground, the differential voltage on the capacitor array top plate is reduced by 2^(-2)V_ref；

Case eight: if D is_ND_WIND_N-1000, the second one of the last higher capacitor bottom plates is connected to a reference voltage by a ground level, the second two of the next higher capacitor bottom plates is connected to a ground level by a reference voltage, and the difference on the top plate of the capacitor arrayIncrease in voltage 2^(-2)V_ref。

Step B4 according to the digital code D in the bypass window_N、D_WIN、D_N-4And D_N-5Controlling the connection position of the bottom plate of the capacitor in the upper capacitor array and the lower capacitor array specifically comprises:

the first condition is as follows: if D is_ND_WIND_N-4D_N-51011, the first bottom N-5 bit capacitor bottom plate is connected to the reference voltage from ground level, and the differential voltage on the capacitor array top plate is reduced by 2^(-6)V_ref；

Case two: if D is_ND_WIND_N-4D_N-51010, the first upper N-5 bit capacitor bottom plate is connected from ground to a reference voltage, and the differential voltage on the capacitor array top plate is increased by 2^(-6)V_ref；

Case three: if D is_ND_WIND_N-4D_N-51001, the first lower N-5 bit capacitor bottom plate is connected from ground to a reference voltage, and the differential voltage on the capacitor array top plate is reduced by 2^(-6)V_ref；

Case four: if D is_ND_WIND_N-4D_N-51000, the first upper N-5 bit capacitor bottom plate is connected from ground to a reference voltage, and the differential voltage on the capacitor array top plate is increased by 2^(-6)V_ref；

Case five: if D is_ND_WIND_N-4D_N-50111, the first bottom N-5 bit capacitor bottom plate is connected to a reference voltage from ground, the differential voltage on the capacitor array top plate is reduced by 2^(-6)V_ref；

Case six: if D is_ND_WIND_N-4D_N-50110, the first upper N-5 bit capacitor bottom plate is connected from ground to a reference voltage, and the differential voltage on the capacitor array top plate is increased by 2^(-6)V_ref；

Case seven: if D is_ND_WIND_N-4D_N-50101, the first lower N-5 bit capacitor bottom plate is connected to the reference electrode via ground levelDifferential voltage reduction on the top plate of the capacitor array 2^(-6)V_ref；

Case eight: if D is_ND_WIND_N-4D_N-50100, the first upper N-5 bit capacitor bottom plate is connected from ground to a reference voltage, and the differential voltage on the capacitor array top plate is increased by 2^(-6)V_ref；

Step B4 said outside the bypass window according to the digital code D_N、D_WIN、D_N-1And D_N-2Controlling the connection position of the bottom plate of the capacitor in the upper capacitor array and the lower capacitor array specifically comprises:

case nine: if D is_ND_WIND_N-1D_N-21111, skip D_N-3The bottom plate of the second capacitor with the lowest position on the two upper sides is connected to the ground level by the reference voltage, the bottom plate of the second capacitor with the lowest position on the two lower sides is connected to the reference voltage by the ground level, and the differential voltage on the top plate of the capacitor array is reduced by 2^(-4)V_ref；

Case ten: if D is_ND_WIND_N-1D_N-21110, the second last lower capacitor bottom plate is connected to the reference voltage by the ground level, the second next lower capacitor bottom plate is connected to the ground level by the reference voltage, and the differential voltage on the top plate of the capacitor array is increased by 2^(-3)V_ref；

Case eleven: if D is_ND_WIND_N-1D_N-21101, the second next higher capacitor bottom plate is connected to the reference voltage from ground, and the differential voltage on the top plate of the capacitor array is reduced by 2^(-3)V_ref；

Case twelve: if D is_ND_WIND_N-1D_N-21100, the second last lower capacitor bottom plate is connected to the reference voltage by the ground level, the second next lower capacitor bottom plate is connected to the ground level by the reference voltage, and the differential voltage on the top plate of the capacitor array is increased by 2^(-3)V_ref；

Case thirteen: if D is_ND_WIND_N-1D_N-20011, the second one of the last lower capacitor bottom plates is connected to ground by a reference voltage, the second two of the next higher capacitor bottom plates is connected to the reference voltage by ground, and the differential voltage on the top plate of the capacitor array is reduced by 2^(-3)V_ref；

A fourteenth situation: if D is_ND_WIND_N-1D_N-20010, the second and last higher capacitor bottom plate is connected from ground to a reference voltage, and the differential voltage on the top plate of the capacitor array is increased by 2^(-3)V_ref；

Case fifteen: if D is_ND_WIND_N-1D_N-20001, connecting the bottom plate of the first last lower capacitor to ground level by reference voltage, connecting the bottom plate of the second next lower capacitor to ground level by reference voltage, and reducing the differential voltage on the top plate of the capacitor array by 2^(-3)V_ref；

Case sixteen: if D is_ND_WIND_N-1D_N-20000, skip D_N-3The bottom plate of the capacitor at the lowest position on the second capacitor is connected to a reference voltage by a ground level, the bottom plate of the capacitor at the lowest position on the second capacitor is connected to the ground level by the reference voltage, and the differential voltage on the top plate of the capacitor array is increased by 2^(-4)V_ref。

According to the digital code D in the step B5_N-Kiw-1Controlling the connection position of the bottom plate of the capacitor in the upper capacitor array and the lower capacitor array, specifically:

the first condition is as follows: voltage within the bypass window, D_N-Kiw-1When 1, the first is N-K_iwThe bottom plate of the-1-bit capacitor is connected to a reference voltage by a ground level, and K is more than or equal to 5 ≦ K_iwLess than or equal to N-3, and the differential voltage on the top plate of the capacitor array is reduced by 2^(-Kiw-2)V_ref(ii) a Otherwise, D_N-Kiw-1When equal to 0, first go up N-K_iw1 bit capacitor bottom plate connected from ground level to reference voltage, differential voltage increase on capacitor array top plate 2^(-Kiw-2)V_ref；

According to the digital code D in the step B5_N-Kow1+1Controlling capacitors in upper and lower capacitor arraysThe connection position of the bottom polar plate specifically is as follows:

case two: voltages outside the bypass window, the limiting case including D_ND_WIND_N-1D_N-20000 or 1111, D_N-Kow1+1When 1, the first is N-K_ow1The +1 bit capacitor bottom plate is connected to a reference voltage by a ground level, and K is more than or equal to 5_ow1Less than or equal to N-1, and the differential voltage on the top plate of the capacitor array is reduced by 2^(-Kow1)V_ref(ii) a Otherwise, D_N-Kow1+1When equal to 0, first go up N-K_ow1The +1 bit capacitor bottom plate is connected to the reference voltage by the ground level, the differential voltage on the capacitor array top plate is increased by 2^(-Kow1)V_ref；

According to the digital code D in the step B5_N-Kow2+2Controlling the connection position of the bottom plate of the capacitor in the upper capacitor array and the lower capacitor array, specifically:

case three: voltages outside the bypass window, not limiting, D_N-Kow2+2When 1, K_ow25, the bottom plate of the second capacitor with the lowest position on the second upper electrode is connected to the ground level by the reference voltage, the bottom plate of the second capacitor with the lowest position on the second lower electrode is connected to the reference voltage by the ground level, and the differential voltage on the top plate of the capacitor array is reduced by 2^(-Kow2+1)V_ref(ii) a When K is more than or equal to 6_ow2Less than or equal to N, the first N-K_ow2The bottom plate of the + 2-bit capacitor is connected to a reference voltage by a ground level, and the differential voltage on the top plate of the capacitor array is reduced by 2^(-Kow2+1)V_ref(ii) a Otherwise, D_N-Kow2+2When equal to 0, K_ow2When the voltage is 5, the bottom plate of the second capacitor with the lowest position on the second capacitor is connected to the reference voltage by the ground level, the bottom plate of the second capacitor with the lowest position on the second capacitor is connected to the ground level by the reference voltage, and the differential voltage on the top plate of the capacitor array is increased by 2^(-Kow2+1)V_ref(ii) a When K is more than or equal to 6_ow2Less than or equal to N, first N-K_ow2The +2 bit capacitor bottom plate is connected to the reference voltage by the ground level, the differential voltage on the capacitor array top plate is increased by 2^(-Kow2+1)V_ref。

And C, the code spelling device is used for spelling the digital codes to obtain the converted N-bit digital codes, and the method specifically comprises the following steps:

the first condition is as follows: in-2^(-3)V_ref2～2^(-3)V_refBypassing the window, instruction D_N-1＝D_WIN、D_N-2＝D_WINAnd D_N-3＝D_WINThe code spelling device outputs the converted N-bit digital code;

case two: outside the bypass window, in the limiting case D_ND_WIND_N-1D_N-21111 or 0000, order D_N-3＝D_WINThe code spelling device outputs the converted N-bit digital code;

case three: outside the bypass window, if not at all, D_NWhen 1, corresponding digital code D_N-3Where is required to add D_WINThe value of (1) and carry calculation, the code spelling device outputs the converted N-bit digital code; d_NWhen equal to 0, corresponding digital code D_N-3To subtract D_WINAnd with borrow calculation, the splicer outputs the converted N-digit digital code.

Has the advantages that: by adopting the technical scheme, the invention can produce the following beneficial effects:

the invention switches for the first time to generate +/-2 on the top plate of the capacitor^-3Voltage variation of Vref, resulting in a value of + -2^-3A Vref window is set, so that whether the differential input voltage is in the window or not is judged, the conversion steps of Most Significant Bit (MSB) and MSB-1 can be skipped in the window, and a large amount of power consumption is saved; compared with the traditional switching algorithm, the invention averagely reduces 87.29% of DAC power consumption, reduces 95.56% of DAC power consumption of input voltage in a window, saves 50% of capacitor area, and realizes compromise of energy efficiency and area.

Drawings

FIG. 1 is a schematic structural diagram of a SARADC employed for achieving 10-bit resolution by the method of the present invention;

FIG. 2 is a schematic diagram of the switching of the 6-bit SARADC according to the present invention, and FIG. 2(a) is a schematic diagram of the switching from step B1 to step B3 and D₆D_WIND₅The switching from B4 to step B5 in 111 cases is shown as D in fig. 2(B)₆D_WIND₅＝110、D₆D_WIND₂＝101、D₆D_WIND₂Switching signals from B4 to step B5 for 100 cases;

FIG. 3 is a diagram of MATLAB simulation results of the switching energy consumption of a 10-bit SARADC according to the present invention.

The figure shows that: the circuit comprises a sampling switch 1, a capacitor array 2, a comparator 3, a digital control logic circuit 4, a code spelling device 5, an upper capacitor array 2-1, a lower capacitor array 2-2 and a first upper sub capacitor array DAC_P1The second capacitor array DAC on one of the capacitors_P2aA second two upper sub-capacitor array DAC_P2b(ii) a First lower sub capacitor array DAC_N1A second lower sub-capacitor array DAC_N2aSecond two lower sub-capacitor array DAC_N2b；

The highest capacitor C on the second one_N,paSecond one of the last high-order capacitors C_N-1,paSecond one of the last low-order capacitors C_N-2,paThe lowest bit capacitor C on the second one_N-3,pa(ii) a Second highest capacitor C_N,pbSecond, third, fourth, and fourth capacitors_N-1,pbSecond, last, lower capacitor C_N-2,pbSecond lowest two-level capacitor C_N-3,pb；

Second one of the lower highest bit capacitor C_N,naSecond one next higher capacitor C_N-1,naSecond, its next lower capacitor C_N-2,naSecond one lower lowest bit capacitor C_N-3,na(ii) a Second highest capacitor C_N,nbSecond, second next higher capacitor C_N-1,nbSecond, next lower capacitor C_N-2,nbSecond lowest two-level capacitor C_N-3,nb；

First upper N-4 bit capacitor C_N-4,pFirst upper N-5 bit capacitor C_N-5,pFirst upper N-6 bit capacitor C_N-6,pFirst upper N-7 bit capacitor C_N-7,pFirst upper N-8 bit capacitor C_N-8,pFirst upper N-9 th bit capacitor C_N-9,p；

First lower N-4 bit capacitor C_N-4,nFirst lower N-5 bit capacitor C_N-5,nFirst lower N-6 bit capacitor C_N-6,nFirst lower N-7 bit capacitor C_N-7,nFirst lower N-8 bit capacitor C_N-8,nFirst lower N-9 bit capacitor C_N-9,n。

Detailed Description

The following describes embodiments of the present invention with reference to the drawings.

The invention relates to a bypass window switching method applied to a successive approximation type analog-to-digital converter, which comprises a sampling switch 1, a capacitor array 2, a comparator 3, a digital control logic circuit 4 and a code spelling device 5, wherein the capacitor array 2 comprises an upper capacitor array 2-1 and a lower capacitor array 2-2 which have the same structure; differential input voltage, namely positive end input voltage VIP and negative end input voltage VIN, is respectively connected to the top plates of the upper capacitor array 2-1 and the lower capacitor array 2-2 through a sampling switch 1; the top plate of the upper capacitor array 2-1 is connected with the non-inverting input end of the comparator 3, and the top plate of the lower capacitor array 2-2 is connected with the inverting input end of the comparator 3; the differential output end of the comparator 3 is connected to the digital control logic circuit 4, the digital control logic circuit 4 generates control signals to control the bottom electrode plates of the upper capacitor array 2-1 and the lower capacitor array 2-2 to be connected to corresponding electrical levels, and the code spelling device 5 spells each digital code output by the digital control logic circuit 4 to generate converted digital codes.

The upper capacitor array 2-1 comprises a first upper sub capacitor array DAC_P1The second capacitor array DAC on one of the capacitors_P2aAnd a second upper sub-capacitor array DAC_P2b(ii) a The lower capacitor array 2-2 comprises a first lower sub capacitor array DAC_N1A second lower sub-capacitor array DAC_N2aAnd a second lower sub-capacitor array DAC_N2b。

Second one of which has sub-capacitor array DAC_P2aAnd a second upper sub-capacitor array DAC_P2bSplit capacitor array of high four-bit capacitors, the second one of which has the highest bit capacitor C_N,paHas a capacitance value of 2^N-3C, the second one of the last high-order capacitors C_N-1,paHas a capacitance value of 2^N-4C, the second one of which is the last low-order capacitor C_N-2,paHas a capacitance value of 2^N-5C, the lowest bit capacitor C on the second one_N-3,paHas a capacitance value of2^N-6C, wherein N represents the digit of the analog-to-digital converter, and C is a unit capacitance value; first upper sub capacitor array DAC_P1Is a low-order capacitor, wherein the first upper N-9-order capacitor C_N-9,pIs a dummy capacitor with a capacitance of 1C and a first upper N-4 bit capacitor C_N-4,pHas a capacitance value of 2^N-6C, a first upper N-5 bit capacitor C_N-5,pHas a capacitance value of 2^N-7C, the first upper N-6 bit capacitor C_N-6,pA capacitance value of 2^N-8C, the first upper N-7 bit capacitor C_N-7,pHas a capacitance value of 2^N-9C, a first upper N-8 bit capacitor C_N-8,pThe capacitance value of (1C). The number N of the analog-to-digital converter bits is 10.

The bypass window switching method applied to the successive approximation type analog-to-digital converter comprises the following steps of:

step A, a sampling stage:

first upper sub capacitor array DAC of upper capacitor array 2-1_P1And a second one of which has a sub-capacitor array DAC_P2aIs connected to ground level gnd, and a second one of its two upper sub-capacitor array DACs_P2bAll capacitor bottom plates of (2) are connected to a reference voltage V_ref(ii) a First lower sub-capacitor array DAC of lower capacitor array 2-2_N1And a second lower sub-capacitor array DAC_N2aAll capacitor bottom plates of (1) are connected to ground level gnd, the second two lower sub-capacitor array DAC_N2bAll capacitor bottom plates of (2) are connected to a reference voltage V_ref；

Step B, a conversion stage:

step B1, the sampling switch 1 is switched off, then the comparator 3 directly carries out the most significant bit comparison of the positive terminal input voltage VIP and the negative terminal input voltage VIN of the top plates of the upper capacitor array 2-1 and the lower capacitor array 2-2 to obtain the digital code D_NWhere N denotes the number of bits of the analog-to-digital converter, the digital control logic 4 being based on the digital code D_NControlling the connection position of the bottom plate of the capacitor in the upper capacitor array 2-1 and the lower capacitor array 2-2; the method specifically comprises the following steps:

the first condition is as follows: if D is_NSecond, last lower capacitor C ═ 1_N-2,pbBottom plate is driven by reference voltage V_refIs connected to earth groundPlanar, second, its next lower capacitor C_N-2,naThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage reduction 2 on the top plate of capacitor array 2^(-3)V_refForm a 0 to 2^(-3)V_refBy-pass window of (2), wherein V_refIs a reference voltage;

case two: if D is_N0, the second one of which has the last lower capacitance C_N-2,paThe bottom plate being connected from ground level gnd to a reference voltage V_refSecond, next lower capacitor C_N-2,nbBottom plate is driven by reference voltage V_refConnected to ground level gnd, the differential voltage on the top plate of the capacitor array 2 is increased by 2^(-3)V_refForm a value of 0 to-2^(-3)V_refThe bypass window of (1).

In step B2, the comparator 3 compares the voltages of the top electrode plates of the upper capacitor array 2-1 and the lower capacitor array 2-2 obtained in step B1 to obtain a digital code D_WINAccording to digital code D_NAnd D_WINJudging whether the differential input voltage is in a bypass window or not so as to control the connection position of the bottom electrode plates of the capacitors in the upper capacitor array 2-1 and the lower capacitor array 2-2; the method specifically comprises the following steps:

the first condition is as follows: if D is_ND_WINThe difference input voltage is explained in the bypass window 0-2 ═ 11^(-3)V_refIn addition, the second highest-order capacitor C_N,pbBottom plate is driven by reference voltage V_refConnected to ground gnd, the second one of its next highest-order capacitors C_N,naThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage reduction 2 on the top plate of capacitor array 2^(-1)V_ref；

Case two: if D is_ND_WIN10, the differential input voltage is explained in the bypass window 0-2^(-3)V_refWithin, skip digital code D_N-1、D_N-2The lowest bit capacitor C on the second one_N-3,paThe bottom plate being connected from ground level gnd to a reference voltage V_refSecond lowest two-level capacitor C_N-3,nbBottom plate is driven by reference voltage V_refConnected to ground level gnd, capacitor array 2 topDifferential voltage increase on the plates 2^(-4)V_ref；

Case three: if D is_ND_WIN01, the differential input voltage is explained in the bypass windows 0 to-2^(-3)V_refWithin, skip digital code D_N-1、D_N-2Second lowest two-level capacitor C_N-3,pbBottom plate is driven by reference voltage V_refConnected to ground gnd, the second one of its lower lowest bit capacitance C_N-3,naThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage reduction 2 on the top plate of capacitor array 2^(-4)V_ref；

Case four: if D is_ND_WIN00, the differential input voltage is illustrated in the bypass windows 0 to-2^(-3)V_refBesides, the highest bit capacitance C on the second one_N,paThe bottom plate being connected from ground level gnd to a reference voltage V_refSecond highest capacitor C_N,nbBottom plate is driven by reference voltage V_refConnected to ground level gnd, the differential voltage on the top plate of the capacitor array 2 is increased by 2^(-1)V_ref。

In step B3, the comparator 3 compares the voltages of the top electrode plates of the upper capacitor array 2-1 and the lower capacitor array 2-2 obtained in step B2 to obtain a digital code D within the bypass window_N-4Within the bypass window according to the digital code D_N、D_WINAnd D_N-4Controlling the connection position of the bottom plate of the capacitor in the upper capacitor array 2-1 and the lower capacitor array 2-2; the method specifically comprises the following steps:

the first condition is as follows: if D is_ND_WIND_N-4101, first N-4 bit capacitance C_N-4,nThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage reduction 2 on the top plate of capacitor array 2^(-5)V_ref；

Case two: if D is_ND_WIND_N-4First upper N-4 bit capacitance C as 100_N-4,pThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage on the top plate of capacitor array 2 is increased by 2^(-5)V_ref；

Situation three: if D is_ND_WIND_N-4011, first N-4 bit capacitance C_N-4,nThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage reduction 2 on the top plate of capacitor array 2^(-5)V_ref；

Case four: if D is_ND_WIND_N-4010, first upper N-4 bit capacitance C_N-4,pThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage on the top plate of capacitor array 2 is increased by 2^(-5)V_ref；

Obtaining digital codes D outside of bypass windows_N-1Outside the bypass window according to the digital code D_N、D_WINAnd D_N-1Controlling the connection position of the bottom plate of the capacitor in the upper capacitor array 2-1 and the lower capacitor array 2-2; the method specifically comprises the following steps:

case five: if D is_ND_WIND_N-1111, the second and last high-order capacitor C_N-1,pbBottom plate is driven by reference voltage V_refConnected to ground gnd, second of which is a next higher capacitance C_N-1,naThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage reduction 2 on the top plate of capacitor array 2^(-2)V_ref；

Case six: if D is_ND_WIND_N-1110, the second one of which has the last higher capacitance C_N-1,paThe bottom plate being connected from ground level gnd to a reference voltage V_refSecond, second next higher capacitor C_N-1,nbBottom plate is driven by reference voltage V_refConnected to ground level gnd, the differential voltage on the top plate of the capacitor array 2 is increased by 2^(-2)V_ref；

Case seven: if D is_ND_WIND_N-1001, the second and last high-order capacitor C_N-1,pbBottom plate is driven by reference voltage V_refConnected to ground gnd, second of which is a next higher capacitance C_N-1,naThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage reduction 2 on the top plate of capacitor array 2^(-2)V_ref；

Situation(s)Eighthly: if D is_ND_WIND_N-1000, the second one of which has the last higher capacitance C_N-1,paThe bottom plate being connected from ground level gnd to a reference voltage V_refSecond, second next higher capacitor C_N-1,nbBottom plate is driven by reference voltage V_refConnected to ground level gnd, the differential voltage on the top plate of the capacitor array 2 is increased by 2^(-2)V_ref。

In step B4, the comparator 3 compares the voltages of the top plates of the upper capacitor array 2-1 and the lower capacitor array 2-2 obtained in step B3 to obtain a digital code D within the bypass window_N-5In the bypass window according to the digital code D_N、D_WIN、D_N-4And D_N-5Controlling the connection position of the bottom plate of the capacitor in the upper capacitor array 2-1 and the lower capacitor array 2-2; the method specifically comprises the following steps:

the first condition is as follows: if D is_ND_WIND_N-4D_N-51011, the first N-5 bit capacitance C_N-5,nThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage reduction 2 on the top plate of capacitor array 2^(-6)V_ref；

Case two: if D is_ND_WIND_N-4D_N-51010, first upper N-5 bit capacitor C_N-5,pThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage on the top plate of capacitor array 2 is increased by 2^(-6)V_ref；

Case three: if D is_ND_WIND_N-4D_N-51001, first N-5 bit capacitance C_N-5,nThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage reduction 2 on the top plate of capacitor array 2^(-6)V_ref；

Case four: if D is_ND_WIND_N-4D_N-51000, first upper N-5 bit capacitor C_N-5,pThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage on the top plate of capacitor array 2 is increased by 2^(-6)V_ref；

Case five: if D is_ND_WIND_N-4D_N-50111, first N-5 bit capacitance C_N-5,nThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage reduction 2 on the top plate of capacitor array 2^(-6)V_ref；

Case six: if D is_ND_WIND_N-4D_N-50110, first N-5 bits of capacitance C_N-5,pThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage on the top plate of capacitor array 2 is increased by 2^(-6)V_ref；

Case seven: if D is_ND_WIND_N-4D_N-50101, first N-5 bit capacitance C_N-5,nThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage reduction 2 on the top plate of capacitor array 2^(-6)V_ref；

Case eight: if D is_ND_WIND_N-4D_N-50100, first upper N-5 bit capacitance C_N-5,pThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage on the top plate of capacitor array 2 is increased by 2^(-6)V_ref；

Deriving digital codes D outside the bypass window_N-2Outside the bypass window according to the digital code D_N、D_WIN、D_N-1And D_N-2Controlling the connection position of the bottom plate of the capacitor in the upper capacitor array 2-1 and the lower capacitor array 2-2; the method specifically comprises the following steps:

case nine: if D is_ND_WIND_N-1D_N-21111, skip D_N-3Second lowest two-level capacitor C_N-3,pbBottom plate is driven by reference voltage V_refConnected to ground gnd, the second one of its lower lowest bit capacitance C_N-3,naThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage reduction 2 on the top plate of capacitor array 2^(-4)V_ref；

Case ten: if D is_ND_WIND_N-1D_N-21110, the second last lower capacitor C_N-2,pbThe bottom plate being connected to a reference electrode by ground level gndPressure V_refSecond, its next lower capacitor C_N-2,naBottom plate is driven by reference voltage V_refConnected to ground level gnd, the differential voltage on the top plate of the capacitor array 2 is increased by 2^(-3)V_ref；

Case eleven: if D is_ND_WIND_N-1D_N-21101, the second next highest capacitor C_N-1,nbThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage reduction 2 on the top plate of capacitor array 2^(-3)V_ref；

Case twelve: if D is_ND_WIND_N-1D_N-21100, the second last lower capacitor C_N-2,pbThe bottom plate being connected from ground level gnd to a reference voltage V_refSecond, its next lower capacitor C_N-2,naBottom plate is driven by reference voltage V_refConnected to ground level gnd, the differential voltage on the top plate of the capacitor array 2 is increased by 2^(-3)V_ref；

Case thirteen: if D is_ND_WIND_N-1D_N-20011, the second one of which has the last lower capacitance C_N-2,paBottom plate is driven by reference voltage V_refConnected to ground gnd, second its second next higher capacitance C_N-2,nbThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage reduction 2 on the top plate of capacitor array 2^(-3)V_ref；

A fourteenth situation: if D is_ND_WIND_N-1D_N-20010, second and last high-order capacitor C_N-1,pbThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage on the top plate of capacitor array 2 is increased by 2^(-3)V_ref；

Case fifteen: if D is_ND_WIND_N-1D_N-20001, the second one of which has the last lower capacitance C_N-2,paBottom plate is driven by reference voltage V_refConnected to ground gnd, second its second next lower capacitor C_N-2,nbThe bottom plate being connected from ground level gnd to a reference voltage V_ref2 top pole of capacitor arrayDifferential voltage reduction on board 2^(-3)V_ref；

Case sixteen: if D is_ND_WIND_N-1D_N-20000, skip D_N-3The lowest bit capacitor C on the second one_N-3,paThe bottom plate being connected from ground level gnd to a reference voltage V_refSecond lowest two-level capacitor C_N-3,nbBottom plate is driven by reference voltage V_refConnected to ground level gnd, the differential voltage on the top plate of the capacitor array 2 is increased by 2^(-4)V_ref。

In step B5, the comparator 3 compares the voltages of the top plates of the upper capacitor array 2-1 and the lower capacitor array 2-2 obtained in step B4 to obtain a digital code D in the bypass window_N-Kiw-1In which K is_iwFor the number of switching steps in the window, K is not less than 5_iwLess than or equal to N-3 according to the digital code D_N-Kiw-1Controlling the connection position of the bottom plate of the capacitor in the upper capacitor array 2-1 and the lower capacitor array 2-2;

D_N-Kiw-1when 1, the first is N-K_iw-1 bit capacitance C_N-Kiw-1,nThe bottom plate being connected from ground level gnd to a reference voltage V_ref，5≤K_iwLess than or equal to N-3, and the differential voltage on the top plate of the capacitor array 2 is reduced by 2^(-Kiw-2)V_ref(ii) a Otherwise, D_N-Kiw-1When equal to 0, first go up N-K_iw-1 bit capacitance C_N-Kiw-1,pThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage on the top plate of capacitor array 2 is increased by 2^(-Kiw-2)V_ref；

And repeating the operation in the bypass window in the step B5 until the digital code D is obtained₁；

Outside the bypass window, two extreme cases are D_ND_WIND_N-1D_N-20000 or 1111, the digital code D is skipped_N-Kow1+2To obtain a digital code D_N-Kow1+1，K_ow1For the number of steps of switching in the extreme case outside the bypass window, K is not less than 5_ow1Less than or equal to N-1 according to the digital code D_N-Kow1+1Controlling the connection position of the bottom plate of the capacitor in the upper capacitor array 2-1 and the lower capacitor array 2-2, which comprises the following steps:

D_N-Kow1+1when 1, the first is N-K_ow1+1 bit capacitor C_N-Kow1+1,nThe bottom plate being connected from ground level gnd to a reference voltage V_ref，5≤K_ow1Less than or equal to N-1, and the differential voltage on the top plate of the capacitor array 2 is reduced by 2^(-Kow1)V_ref(ii) a Otherwise, D_N-Kow1+1When equal to 0, first go up N-K_ow1+1 bit capacitor C_N-Kow1+1,pThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage on the top plate of capacitor array 2 is increased by 2^(-Kow1)V_ref；

And repeating the operation outside the bypass window in the step B5 until the digital code D is obtained₁；

Other non-limiting cases, to obtain digital code D_N-Kow2+2，K_ow2For the number of steps of switching in the non-limiting case outside the bypass window, K is not less than 5_ow2Less than or equal to N according to the digital code D_N-Kow2+2Controlling the connection position of the bottom plate of the capacitor in the upper capacitor array 2-1 and the lower capacitor array 2-2, which comprises the following steps:

voltages outside the bypass window, not limiting, D_N-Kow2+2When 1, K_ow2Second lowest order capacitor C of 5_N-3,pbBottom plate is driven by reference voltage V_refConnected to ground gnd, the second one of its lower lowest bit capacitance C_N-3,naThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage reduction 2 on the top plate of capacitor array 2^(-Kow2+1)V_ref(ii) a When K is more than or equal to 6_ow2Less than or equal to N, the first N-K_ow2+2 bit capacitance C_N-Kow2+2,nThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage reduction 2 on the top plate of capacitor array 2^(-Kow2+1)V_ref(ii) a Otherwise, D_N-Kow2+2When equal to 0, K_ow2When it is 5, the lowest capacitor C is on the second one_N-3,paThe bottom plate being connected from ground level gnd to a reference voltage V_refSecond lowest two-level capacitor C_N-3,nbBottom plate is driven by reference voltage V_refConnected to ground level gnd, the differential voltage on the top plate of the capacitor array 2 is increased by 2^(-Kow2+1)V_ref(ii) a When K is more than or equal to 6_ow2Less than or equal to N, first N-K_ow2+2 bit capacitance C_N-Kow2+2,pThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage on the top plate of capacitor array 2 is increased by 2^(-Kow2+1)V_ref。

Step C, code spelling:

the digital control logic circuit 4 outputs the digital codes of the comparator 3 to the code spelling device 5, and the code spelling device 5 spells the digital codes to obtain the converted N-bit digital codes. The method specifically comprises the following steps:

the first condition is as follows: in-2^(-3)V_ref2～2^(-3)V_refBypassing the window, instruction D_N-1＝D_WIN、D_N-2＝D_WINAnd D_N-3＝D_WINThe code spelling device 5 outputs the converted N-digit digital code;

case two: outside the bypass window, in the limiting case D_ND_WIND_N-1D_N-21111 or 0000, order D_N-3＝D_WINThe code spelling device 5 outputs the converted N-digit digital code;

case three: outside the bypass window, if not at all, D_NWhen 1, corresponding digital code D_N-3Where is required to add D_WINAnd carry calculation, the code spelling device 5 outputs the converted N-bit digital code; d_NWhen equal to 0, corresponding digital code D_N-3To subtract D_WINAnd with a borrow calculation, the transcoder 5 outputs the converted N-bit digital code.

Therefore, the differential output end of the comparator 3 of the method of the invention generates a control signal to control the bottom plate switches of the upper capacitor array 2-1 and the lower capacitor array 2-2 through the digital control logic 4, the capacitors are switched for the first time to generate a bypass window, whether the differential input voltage is in the window is judged, if the differential input voltage falls in the window, the previous two high-order conversion cycles are skipped, the conversion times can be reduced, and the power consumption of the CDAC, the comparator and the control logic is reduced; if the current is outside the window, the capacitor generating the bypass window is not switched back to continue normal conversion, correct digital codes are output through code splicing, and power consumption of part of DAC switching is reduced.

The invention will now be described in more detail with reference to an example, since D_N1 and D_NIn both cases of 0, the process of quantizing the capacitance from the Most Significant Bit (MSB) to the Least Significant Bit (LSB) is completely symmetrical, and the sar adc conversion process after 6 bits is the same, and the embodiment herein describes a topology where N is 6, assuming that D is equal to 6_NFig. 2 shows a schematic diagram of switching applied to a 6-bit SAR ADC according to the present invention.

Step A, sampling stage

The positive end input voltage VIP and the negative end input voltage VIN are respectively connected to the top plates of the upper capacitor array 2-1 and the lower capacitor array 2-2 through the sampling switch 1, and the first upper sub capacitor array DAC of the upper capacitor array 2-1_P1And a second one of which has a sub-capacitor array DAC_P2aIs connected to ground level gnd, and a second one of its two upper sub-capacitor array DACs_P2bAll capacitor bottom plates of (2) are connected to a reference voltage V_ref(ii) a First lower sub-capacitor array DAC of lower capacitor array 2-2_N1And a second lower sub-capacitor array DAC_N2aAll capacitor bottom plates of (1) are connected to ground level gnd, the second two lower sub-capacitor array DAC_N2bAll capacitor bottom plates of (2) are connected to a reference voltage V_ref。

Step B, transition phase

Step B1, the sampling switch 1 of the analog-to-digital converter is turned off, then the comparator 3 directly compares the MSB bit of the positive terminal input voltage VIP and the negative terminal input voltage VIN of the top plates of the upper capacitor array 2-1 and the lower capacitor array 2-2 to obtain the digital code D₆According to digital code D₆Controlling the connection position of the bottom plate of the capacitor in the upper capacitor array 2-1 and the lower capacitor array 2-2;

due to D₆Second, last lower capacitor C ═ 1_4,pbBottom plate is driven by reference voltage V_refConnected to ground gnd, second of which is a next lower capacitor C_4,naThe bottom plate being connected from ground level gnd to a reference voltage V_refCapacitor array 2 top plateDifferential voltage reduction of 2^(-3)V_refForm a 0 to 2^(-3)V_refThe bypass window of (1);

step B2, according to the digital code D₆And D_WINControlling the connection position of the bottom plate of the capacitor in the upper capacitor array 2-1 and the lower capacitor array 2-2;

the first condition is as follows: if D is₆D_WINWhen the difference input voltage is equal to 11, the difference input voltage is explained in a window 0-2^(-3)V_refIn addition, the second highest-order capacitor C_6,pbBottom plate is driven by reference voltage V_refConnected to ground gnd, the second one of its next highest-order capacitors C_6,naThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage reduction 2 on the top plate of capacitor array 2^(-1)V_ref；

Case two: if D is₆D_WINWhen the difference input voltage is 10, the difference input voltage is explained in a window 0-2^(-3)V_refWithin, skip digital code D₅、D₄At this time, D_WINIs D₃The lowest bit capacitor C on the second one_3,paThe bottom plate being connected from ground level gnd to a reference voltage V_refSecond lowest two-level capacitor C_3,nbBottom plate is driven by reference voltage V_refConnected to ground level gnd, the differential voltage on the top plate of the capacitor array 2 is increased by 2^(-4)V_ref；

Step B3, outside the window, according to the digital code D₆、D_WINAnd D₅Controlling the connection position of the bottom plates of the capacitors in the upper capacitor array 2-1 and the lower capacitor array 2-2 according to the digital code D in the window₆、D_WINAnd D₂Controlling the connection position of the bottom plate of the capacitor in the upper capacitor array 2-1 and the lower capacitor array 2-2;

the first condition is as follows: if D is₆D_WIND₅111, the second and last high-order capacitor C_5,pbBottom plate is driven by reference voltage V_refConnected to ground gnd, second of which is a next higher capacitance C_5,naThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage reduction 2 on the top plate of capacitor array 2^(-2)V_ref；

Case two: if D is₆D_WIND₅110, the second one of which has the last higher capacitance C_5,paBottom plate connected to V by gnd_refSecond, second next higher capacitor C_5,nbBottom plate is driven by reference voltage V_refConnected to ground level gnd, the differential voltage on the top plate of the capacitor array 2 is increased by 2^(-2)V_ref；

Case three: if D is₆D_WIND₂101, first lower 2-bit capacitance C_2,nThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage reduction 2 on the top plate of capacitor array 2^(-5)V_refThe comparator compares the voltages of the top electrode plates of the upper capacitor array 2-1 and the lower capacitor array 2-2 at the moment to obtain a digital code D₁And the conversion is finished;

case four: if D is₆D_WIND₂First upper 2-bit capacitance C as 100_2,pThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage on the top plate of capacitor array 2 is increased by 2^(-5)V_ref；

Said step B4, outside the window, is based on the digital code D₆、D_WIN、D₅And D₄Controlling the connection position of the bottom plates of the capacitors in the upper capacitor array 2-1 and the lower capacitor array 2-2 according to the digital code D in the window₂Controlling the connection position of the bottom plate of the capacitor, and comparing the voltages of the top plates in the upper capacitor array 2-1 and the lower capacitor array 2-2 by the comparator 3 to obtain a digital code D1;

the first condition is as follows: if D is₆D_WIND₅D₄1111, skip D₃Second lowest two-level capacitor C_3,pbBottom plate is driven by reference voltage V_refConnected to ground gnd, the second one of its lower lowest bit capacitance C_3,naThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage reduction 2 on the top plate of capacitor array 2^(-4)V_ref；

Case two: if D is₆D_WIND₅D₄1110, the second last lower capacitor C_4,pbThe bottom plate being connected from ground level gnd to a reference voltage V_refSecond, its next lower capacitor C_4,naBottom plate is driven by reference voltage V_refConnected to ground level gnd, the differential voltage on the top plate of the capacitor array 2 is increased by 2^(-3)V_ref；

Case three: if D is₆D_WIND₅D₄1101, the second next highest capacitor C_5,naThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage reduction 2 on the top plate of capacitor array 2^(-3)V_ref；

Case four: if D is₆D_WIND₅D₄1100, the second last lower capacitor C_4,pbThe bottom plate being connected from ground level gnd to a reference voltage V_refSecond, its next lower capacitor C_4,naBottom plate is driven by reference voltage V_refConnected to ground level gnd, the differential voltage on the top plate of the capacitor array 2 is increased by 2^(-3)V_ref；

Step B5, outside the window, according to the digital code D₃Controlling the connection positions of the bottom plates of the capacitors in the upper capacitor array 2-1 and the lower capacitor array 2-2, and repeating the step B5 until a digital code D is obtained₁(ii) a The method comprises the following conditions:

the first condition is as follows: at voltages outside the window, the limit case being D₆D_WIND₅D₄＝1111，D₂When 1, the first 2 lower capacitors C_2,nThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage reduction 2 on the top plate of capacitor array 2^(-5)V_ref(ii) a Otherwise, D₂When equal to 0, the first upper 2-bit capacitance C_2,pThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage on the top plate of capacitor array 2 is increased by 2^(-5)V_ref；

Case two: at voltages outside the window, not extreme, D_N-Kow2+2When 1, K_ow2Second lowest order capacitor C of 5_3,pbBottom polar plateFrom a reference voltage V_refConnected to ground gnd, the second one of its lower lowest bit capacitance C_3,naThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage reduction 2 on the top plate of capacitor array 2^(-K+1)V_ref；6≤K_ow2N +1 or less, first N-K_ow2+2 bit capacitance C_N-Kow2+2,nThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage reduction 2 on the top plate of capacitor array 2^(-K+1)V_ref. Otherwise, D_N-Kow2+2When equal to 0, K_ow2When it is 5, the lowest capacitor C is on the second one_3,paThe bottom plate being connected from ground level gnd to a reference voltage V_refSecond lowest two-level capacitor C_3,nbBottom plate is driven by reference voltage V_refConnected to ground level gnd, the differential voltage on the top plate of the capacitor array 2 is increased by 2^(-Kow2+1)V_ref；6≤K_ow2Not more than N +1, the first N-K_ow2+2 bit C_N-Kow2+2,pThe bottom plate being connected from ground level gnd to a reference voltage V_refDifferential voltage on the top plate of capacitor array 2 is increased by 2^(-Kow2+1)V_ref；

Step C, the code spelling device 5 spells the codes of different digital codes, which specifically comprises:

the first condition is as follows: in the range of 0 to 2^(-3)V_refWithin the window, order D₅＝D_WIN、D₄＝D_WIN、D₃＝D_WINThe correct output code is output by the splicer 5.

Case two: outside the window, in the limiting case D₆D_WIND₅D₄1111, let D₃＝D_WINThe code spelling device 5 outputs the correct output code.

Case three: outside the window, if not in the limit, the digital code D₃To add D_WINAnd with a carry calculation, the splicer 5 outputs the correct digital code.

As shown in fig. 3, which is a diagram of MATLAB simulation results of the power consumption of switching and resetting applied to 10-bit sar ADC varying with ADC input signals, for comparison, V in the diagram is the CDAC reference voltage of most switching algorithms including Vcm-based switching algorithm; according to the invention, the DAC power consumption is averagely reduced by 87.29%, the DAC power consumption of 95.56% of the input voltage in a window can be reduced, the capacitance area is saved by 50%, and the compromise of energy efficiency and area is realized.

In summary, the method of the present invention utilizes + -2 of the first handover^-3The voltage change of Vref utilizes DAC electric capacity to produce the bypass window, avoids introducing extra error, and the voltage in the window can skip the electric capacity switching of high two, reduces the conversion cycle, and the voltage outside the window can improve partial nonlinearity, adopts the top plate sampling to save half electric capacity area, has realized the good compromise of energy efficiency and area saving.

The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.

Claims

1. A bypass window switching method applied to a successive approximation type analog-to-digital converter is characterized in that the analog-to-digital converter comprises a sampling switch (1), a capacitor array (2), a comparator (3), a digital control logic circuit (4) and a code splicing device (5), wherein the capacitor array (2) comprises an upper capacitor array (2-1) and a lower capacitor array (2-2) which have the same structure; the differential input voltage, namely a positive end input Voltage (VIP) and a negative end input Voltage (VIN), is respectively connected to the top plates of the upper capacitor array (2-1) and the lower capacitor array (2-2) through the sampling switch (1); the top polar plate of the upper capacitor array (2-1) is connected with the non-inverting input end of the comparator (3), and the top polar plate of the lower capacitor array (2-2) is connected with the inverting input end of the comparator (3); the differential output end of the comparator (3) is connected to the digital control logic circuit (4), the digital control logic circuit (4) generates a control signal to control the bottom pole plates of the upper capacitor array (2-1) and the lower capacitor array (2-2) to be connected to corresponding levels, and the code spelling device (5) spells each digital code output by the digital control logic circuit (4) to generate a converted digital code;

the upper capacitor array (2-1) comprises a first upper sub capacitor array(DAC_P1) A second one of which has a sub-capacitor array (DAC)_P2a) And a second upper sub-capacitor array (DAC)_P2b) (ii) a The lower capacitor array (2-2) comprises a first lower sub-capacitor array (DAC)_N1) A second lower sub-capacitor array (DAC)_N2a) And a second lower sub-capacitor array (DAC)_N2b)；

step A, a sampling stage:

first upper sub-capacitor array (DAC) of upper capacitor array (2-1)_P1) And a second sub-capacitor array (DAC) thereon_P2a) Is connected to ground (gnd), and a second, upper, sub-capacitor array (DAC)_P2b) Is connected to a reference voltage (V)_ref) (ii) a A first lower sub-capacitor array (DAC) of the lower capacitor array (2-2)_N1) And a second lower sub-capacitor array (DAC)_N2a) Is connected to ground level (gnd), and a second, lower sub-capacitor array (DAC)_N2b) Is connected to a reference voltage (V)_ref)；

Step B, a conversion stage:

step B1, the sampling switch (1) is switched off, then the comparator (3) directly carries out the most significant bit comparison on the positive terminal input Voltage (VIP) and the negative terminal input Voltage (VIN) of the top polar plates of the upper capacitor array (2-1) and the lower capacitor array (2-2) to obtain the digital code D_NWhere N represents the number of bits of the analog-to-digital converter, the digital control logic (4) being based on the digital code D_NControlling the connection position of the capacitor bottom plates in the upper capacitor array (2-1) and the lower capacitor array (2-2);

step B2, the comparator (3) compares the voltage of the top electrode plate of the upper capacitor array (2-1) and the lower capacitor array (2-2) obtained from the step B1 to obtain a digital code D_WINAccording to digital code D_NAnd D_WINJudging whether the differential input voltage is in a bypass window or not, and controlling the connection position of the bottom plates of the capacitors in the upper capacitor array (2-1) and the lower capacitor array (2-2);

step B3, the comparator (3) compares the slave stepThe voltage of the top electrode plate of the upper capacitor array (2-1) and the lower capacitor array (2-2) obtained in the step B2 obtains a digital code D in a bypass window_N-4Within the bypass window according to the digital code D_N、D_WINAnd D_N-4Controlling the connection position of the capacitor bottom plates in the upper capacitor array (2-1) and the lower capacitor array (2-2); obtaining digital codes D outside of bypass windows_N-1Outside the bypass window according to the digital code D_N、D_WINAnd D_N-1Controlling the connection position of the capacitor bottom plates in the upper capacitor array (2-1) and the lower capacitor array (2-2);

step B4, the comparator (3) compares the voltage of the top plate of the upper capacitor array (2-1) and the lower capacitor array (2-2) obtained from step B3 to obtain a digital code D within the bypass window_N-5In the bypass window according to the digital code D_N、D_WIN、D_N-4And D_N-5Controlling the connection position of the capacitor bottom plates in the upper capacitor array (2-1) and the lower capacitor array (2-2); deriving digital codes D outside the bypass window_N-2Outside the bypass window according to the digital code D_N、D_WIN、D_N-1And D_N-2Controlling the connection position of the capacitor bottom plates in the upper capacitor array (2-1) and the lower capacitor array (2-2);

step B5, the comparator (3) compares the voltage of the top electrode plate of the upper capacitor array (2-1) and the lower capacitor array (2-2) obtained from the step B4 to obtain a digital code D in the bypass window_N-Kiw-1In which K is_iwFor the number of switching steps in the window, K is not less than 5_iwLess than or equal to N-3 according to the digital code D_N-Kiw-1Controlling the connection position of the capacitor bottom plates in the upper capacitor array (2-1) and the lower capacitor array (2-2); and repeating the operation in the bypass window in the step B5 until the digital code D is obtained₁(ii) a Outside the bypass window, two extreme cases are D_ND_WIND_N-1D_N-20000 or 1111, the digital code D is skipped_N-Kow1+2To obtain a digital code D_N-Kow1+1，K_ow1For the number of steps of switching in the extreme case outside the bypass window, K is not less than 5_ow1Less than or equal to N-1 according to the digital code D_N-Kow1+1Controlling the bottom plates of the capacitors in the upper capacitor array (2-1) and the lower capacitor array (2-2)Connecting the position, and repeating the operation outside the bypass window in the step B5 until the digital code D is obtained₁(ii) a Other non-limiting cases, to obtain digital code D_N-Kow2+2，K_ow2For the number of steps of switching in the non-limiting case outside the bypass window, K is not less than 5_ow2Less than or equal to N according to the digital code D_N-Kow2+2Controlling the connection position of the bottom plates of the capacitors in the upper capacitor array (2-1) and the lower capacitor array (2-2), and repeating the operation outside the bypass window in the step B5 until a digital code D is obtained₁；

Step C, code spelling:

the digital control logic circuit (4) outputs the digital codes of the comparator (3) to the code spelling device (5), and the code spelling device (5) spells the digital codes to obtain the converted N-bit digital codes.

2. The method of claim 1, wherein the second sub-capacitor array on the first capacitor (DAC) is a digital-to-analog converter (ADC)_P2a) And a second upper sub-capacitor array (DAC)_P2b) Split capacitor array being a high four-bit capacitor, the second of which has the highest bit capacitance (C)_N,pa) Has a capacitance value of 2^N-3C, second one of the last high order capacitor (C)_N-1,pa) Has a capacitance value of 2^N-4C, second one of last low order capacitance (C)_N-2,pa) Has a capacitance value of 2^N-5C, the lowest bit capacitance on the second one (C)_N-3,pa) Has a capacitance value of 2^N-6C, wherein N represents the digit of the analog-to-digital converter, and C is a unit capacitance value; the first upper sub-capacitor array (DAC)_P1) Is a low-order capacitor, wherein the first upper N-9-order capacitor (C)_N-9,p) Is a dummy capacitor with a capacitance of 1C, a first upper N-4 bit capacitor (C)_N-4,p) Has a capacitance value of 2^N-6C, first upper N-5 bit capacitance (C)_N-5,p) Has a capacitance value of 2^N-7C, first upper N-6 bit capacitance (C)_N-6,p) Has a capacitance value of 2^N-8C, first upper N-7 bit capacitance (C)_N-7,p) Has a capacitance value of 2^N-9C, first upper N-8 bit capacitance (C)_N-8,p) The capacitance value of (1C).

3. The method of claim 1, wherein the digital control logic circuit (4) in step B1 is based on a digital code D_NThe method for controlling the connection position of the bottom plates of the capacitors in the upper capacitor array (2-1) and the lower capacitor array (2-2) specifically comprises the following steps:

the first condition is as follows: if D is_NSecond two last lower capacitors (C) of 1_N-2,pb) The bottom plate is driven by a reference voltage (V)_ref) Connected to ground (gnd), second of which is the next lower capacitance (C)_N-2,na) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Differential voltage reduction 2 on the top plate of the capacitor array 2^(-3)V_refForm a 0 to 2^(-3)V_refBy-pass window of (2), wherein V_refIs a reference voltage;

case two: if D is_N0, the second one of which has the last lower capacitance (C)_N-2,pa) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Second two next lower capacitors (C)_N-2,nb) The bottom plate is driven by a reference voltage (V)_ref) Connected to ground level (gnd), the differential voltage on the top plate of the capacitor array (2) is increased by 2^(-3)V_refForm a value of 0 to-2^(-3)V_refThe bypass window of (1).

4. The method of claim 1, wherein the step B2 is performed according to a digital code D_NAnd D_WINJudging whether the differential input voltage is in a bypass window or not so as to control the connection position of a bottom plate of a capacitor in the upper capacitor array (2-1) and the lower capacitor array (2-2), and the method specifically comprises the following steps:

the first condition is as follows: if D is_ND_WINThe difference input voltage is explained in the bypass window 0-2 ═ 11^(-3)V_refExcept that the second highest capacitance (C)_N,pb) The bottom plate is driven by a reference voltage (V)_ref) Connected to ground (gnd), the second one of its next highest bit capacitance (C)_N,na) The bottom polar plate is grounded (gnd)Is connected to a reference voltage (V)_ref) Differential voltage reduction 2 on the top plate of the capacitor array 2^(-1)V_ref；

Case two: if D is_ND_WIN10, the differential input voltage is explained in the bypass window 0-2^(-3)V_refWithin, skip digital code D_N-1、D_N-2The lowest bit capacitance (C) of the second one_N-3,pa) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Second lowest two bit capacitance (C)_N-3,nb) The bottom plate is driven by a reference voltage (V)_ref) Connected to ground level (gnd), the differential voltage on the top plate of the capacitor array (2) is increased by 2^(-4)V_ref；

Case three: if D is_ND_WIN01, the differential input voltage is explained in the bypass windows 0 to-2^(-3)V_refWithin, skip digital code D_N-1、D_N-2Second lowest two-level capacitor (C)_N-3,pb) The bottom plate is driven by a reference voltage (V)_ref) Connected to ground (gnd), the second one of its lowest bit capacitance (C)_N-3,na) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Differential voltage reduction 2 on the top plate of the capacitor array 2^(-4)V_ref；

Case four: if D is_ND_WIN00, the differential input voltage is illustrated in the bypass windows 0 to-2^(-3)V_refBesides, the second one has the highest bit capacitance (C)_N,pa) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Second highest capacitance (C) of two lower most significant bits_N,nb) The bottom plate is driven by a reference voltage (V)_ref) Connected to ground level (gnd), the differential voltage on the top plate of the capacitor array (2) is increased by 2^(-1)V_ref。

5. The method of claim 1, wherein the step B3 is performed within the bypass window according to a digital code D_N、D_WINAnd D_N-4Controlling the capacitor bottom plates in the upper capacitor array (2-1) and the lower capacitor array (2-2)The connecting position of (a) is specifically:

the first condition is as follows: if D is_ND_WIND_N-4First N-4 bit capacitance (C) of 101_N-4,n) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Differential voltage reduction 2 on the top plate of the capacitor array 2^(-5)V_ref；

Case two: if D is_ND_WIND_N-4First N-4 bit capacitance (C) of 100_N-4,p) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Differential voltage on the top plate of the capacitor array (2) is increased by 2^(-5)V_ref；

Case three: if D is_ND_WIND_N-4011, first N-4 bit capacitance (C)_N-4,n) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Differential voltage reduction 2 on the top plate of the capacitor array 2^(-5)V_ref；

Case four: if D is_ND_WIND_N-4010, first upper N-4 bit capacitance (C)_N-4,p) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Differential voltage on the top plate of the capacitor array (2) is increased by 2^(-5)V_ref；

Step B3, according to the digital code D, outside the bypass window_N、D_WINAnd D_N-1Controlling the connection position of the capacitor bottom plates in the upper capacitor array (2-1) and the lower capacitor array (2-2) specifically as follows:

case five: if D is_ND_WIND_N-1111, the second two last higher order capacitors (C)_N-1,pb) The bottom plate is driven by a reference voltage (V)_ref) Connected to ground (gnd), second its next higher capacitance (C)_N-1,na) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Differential voltage reduction 2 on the top plate of the capacitor array 2^(-2)V_ref；

Case six: if D is_ND_WIND_N-1110, the second one of which has the last higher capacitance (C)_N-1,pa) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Second two next higher capacitors (C)_N-1,nb) The bottom plate is driven by a reference voltage (V)_ref) Connected to ground level (gnd), the differential voltage on the top plate of the capacitor array (2) is increased by 2^(-2)V_ref；

Case seven: if D is_ND_WIND_N-1Second two last high order capacitors (C) 001_N-1,pb) The bottom plate is driven by a reference voltage (V)_ref) Connected to ground (gnd), second its next higher capacitance (C)_N-1,na) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Differential voltage reduction 2 on the top plate of the capacitor array 2^(-2)V_ref；

Case eight: if D is_ND_WIND_N-1000, the second one of which has the last higher capacitance (C)_N-1,pa) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Second two next higher capacitors (C)_N-1,nb) The bottom plate is driven by a reference voltage (V)_ref) Connected to ground level (gnd), the differential voltage on the top plate of the capacitor array (2) is increased by 2^(-2)V_ref。

6. The method of claim 1, wherein the step B4 is based on digital code D in the bypass window_N、D_WIN、D_N-4And D_N-5The method for controlling the connection position of the bottom plates of the capacitors in the upper capacitor array (2-1) and the lower capacitor array (2-2) specifically comprises the following steps:

the first condition is as follows: if D is_ND_WIND_N-4D_N-51011, the first N-5 bit capacitance (C)_N-5,n) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Differential voltage reduction 2 on the top plate of the capacitor array 2^(-6)V_ref；

Case two: if D is_ND_WIND_N-4D_N-51010, first upper N-5 bit capacitance (C)_N-5,p) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Differential voltage on the top plate of the capacitor array (2) is increased by 2^(-6)V_ref；

Case three: if D is_ND_WIND_N-4D_N-51001, first N-5 bit capacitance (C)_N-5,n) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Differential voltage reduction 2 on the top plate of the capacitor array 2^(-6)V_ref；

Case four: if D is_ND_WIND_N-4D_N-51000, first N-5 bit capacitance (C)_N-5,p) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Differential voltage on the top plate of the capacitor array (2) is increased by 2^(-6)V_ref；

Case five: if D is_ND_WIND_N-4D_N-50111, first N-5 bit capacitance (C)_N-5,n) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Differential voltage reduction 2 on the top plate of the capacitor array 2^(-6)V_ref；

Case six: if D is_ND_WIND_N-4D_N-50110, first N-5 bit capacitance (C)_N-5,p) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Differential voltage on the top plate of the capacitor array (2) is increased by 2^(-6)V_ref；

Case seven: if D is_ND_WIND_N-4D_N-50101, first N-5 bit capacitance (C)_N-5,n) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Differential voltage reduction 2 on the top plate of the capacitor array 2^(-6)V_ref；

Case eight: if D is_ND_WIND_N-4D_N-50100, first upper N-5 bit capacitance (C)_N-5,p) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Differential voltage on the top plate of the capacitor array (2) is increased by 2^(-6)V_ref；

Step B4 said outside the bypass window according to the digital code D_N、D_WIN、D_N-1And D_N-2Controlling the upper capacitor array (2-1) and the lower capacitorThe connecting position of the capacitor bottom plate in the array (2-2) specifically comprises the following steps:

case nine: if D is_ND_WIND_N-1D_N-21111, skip D_N-3Second lowest two-level capacitor (C)_N-3,pb) The bottom plate is driven by a reference voltage (V)_ref) Connected to ground (gnd), the second one of its lowest bit capacitance (C)_N-3,na) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Differential voltage reduction 2 on the top plate of the capacitor array 2^(-4)V_ref；

Case ten: if D is_ND_WIND_N-1D_N-21110, the second two last lower capacitors (C)_N-2,pb) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Second one of its next lower capacitance (C)_N-2,na) The bottom plate is driven by a reference voltage (V)_ref) Connected to ground level (gnd), the differential voltage on the top plate of the capacitor array (2) is increased by 2^(-3)V_ref；

Case eleven: if D is_ND_WIND_N-1D_N-21101, the second next highest capacitance (C)_N-1,nb) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Differential voltage reduction 2 on the top plate of the capacitor array 2^(-3)V_ref；

Case twelve: if D is_ND_WIND_N-1D_N-21100, the second two last lower capacitors (C)_N-2,pb) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Second one of its next lower capacitance (C)_N-2,na) The bottom plate is driven by a reference voltage (V)_ref) Connected to ground level (gnd), the differential voltage on the top plate of the capacitor array (2) is increased by 2^(-3)V_ref；

Case thirteen: if D is_ND_WIND_N-1D_N-20011, the second one of which has the last lower capacitance (C)_N-2,pa) The bottom plate is driven by a reference voltage (V)_ref) Connected to ground (gnd), second its two next higher capacitors (C)_N-2,nb) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Differential voltage reduction 2 on the top plate of the capacitor array 2^(-3)V_ref；

A fourteenth situation: if D is_ND_WIND_N-1D_N-20010, the second two last higher order capacitor (C)_N-1,pb) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Differential voltage on the top plate of the capacitor array (2) is increased by 2^(-3)V_ref；

Case fifteen: if D is_ND_WIND_N-1D_N-20001, the second one of which has the last lower capacitance (C)_N-2,pa) The bottom plate is driven by a reference voltage (V)_ref) Connected to ground (gnd), second its two next lower capacitors (C)_N-2,nb) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Differential voltage reduction 2 on the top plate of the capacitor array 2^(-3)V_ref；

Case sixteen: if D is_ND_WIND_N-1D_N-20000, skip D_N-3The lowest bit capacitance (C) of the second one_N-3,pa) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Second lowest two bit capacitance (C)_N-3,nb) The bottom plate is driven by a reference voltage (V)_ref) Connected to ground level (gnd), the differential voltage on the top plate of the capacitor array (2) is increased by 2^(-4)V_ref。

7. The method of claim 1, wherein the step B5 is performed according to a digital code D_N-Kiw-1Controlling the connection position of the capacitor bottom plates in the upper capacitor array (2-1) and the lower capacitor array (2-2) specifically as follows:

the first condition is as follows: voltage within the bypass window, D_N-Kiw-1When 1, the first is N-K_iw-1 bit capacitance (C)_N-Kiw-1,n) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref)，5≤K_iwLess than or equal to N-3, the differential voltage on the top plate of the capacitor array (2) is reduced by 2^(-Kiw-2)V_ref(ii) a Otherwise, D_N-Kiw-1When the content is equal to 0, the content,first upper N-K_iw-1 bit capacitance (C)_N-Kiw-1,p) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Differential voltage on the top plate of the capacitor array (2) is increased by 2^(-Kiw-2)V_ref；

According to the digital code D in the step B5_N-Kow1+1Controlling the connection position of the capacitor bottom plates in the upper capacitor array (2-1) and the lower capacitor array (2-2) specifically as follows:

case two: voltages outside the bypass window, the limiting case including D_ND_WIND_N-1D_N-20000 or 1111, D_N-Kow1+1When 1, the first is N-K_ow1+1 bit capacitance (C)_N-Kow1+1,n) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref)，5≤K_ow1Less than or equal to N-1, the differential voltage on the top plate of the capacitor array (2) is reduced by 2^(-Kow1)V_ref(ii) a Otherwise, D_N-Kow1+1When equal to 0, first go up N-K_ow1+1 bit capacitance (C)_N-Kow1+1,p) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Differential voltage on the top plate of the capacitor array (2) is increased by 2^(-Kow1)V_ref；

According to the digital code D in the step B5_N-Kow2+2Controlling the connection position of the capacitor bottom plates in the upper capacitor array (2-1) and the lower capacitor array (2-2) specifically as follows:

case three: voltages outside the bypass window, not limiting, D_N-Kow2+2When 1, K_ow2Second, lowest order capacitor (C) of 5_N-3,pb) The bottom plate is driven by a reference voltage (V)_ref) Connected to ground (gnd), the second one of its lowest bit capacitance (C)_N-3,na) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Differential voltage reduction 2 on the top plate of the capacitor array 2^(-Kow2+1)V_ref(ii) a When K is more than or equal to 6_ow2Less than or equal to N, the first N-K_ow2+2 bit capacitance (C)_N-Kow2+2,n) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Differential voltage reduction 2 on the top plate of the capacitor array 2^(-Kow2+1)V_ref(ii) a Otherwise, D_N-Kow2+2When equal to 0, K_ow2When equal to 5, the firstTwo of them has lowest bit capacitance (C)_N-3,pa) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Second lowest two bit capacitance (C)_N-3,nb) The bottom plate is driven by a reference voltage (V)_ref) Connected to ground level (gnd), the differential voltage on the top plate of the capacitor array (2) is increased by 2^(-Kow2+1)V_ref(ii) a When K is more than or equal to 6_ow2Less than or equal to N, first N-K_ow2+2 bit capacitance (C)_N-Kow2+2,p) The bottom plate is connected to a reference voltage (V) by a ground level (gnd)_ref) Differential voltage on the top plate of the capacitor array (2) is increased by 2^(-Kow2+1)V_ref。

8. The method of claim 1, wherein the code spelling device (5) performs code spelling on each digital code in step C to obtain a converted N-bit digital code, and specifically comprises:

the first condition is as follows: in-2^(-3)V_ref2～2^(-3)V_refBypassing the window, instruction D_N-1＝D_WIN、D_N-2＝D_WINAnd D_N-3＝D_WINThe code spelling device (5) outputs the converted N-bit digital code;

case two: outside the bypass window, in the limiting case D_ND_WIND_N-1D_N-21111 or 0000, order D_N-3＝D_WINThe code spelling device (5) outputs the converted N-bit digital code;

case three: outside the bypass window, if not at all, D_NWhen 1, corresponding digital code D_N-3Where is required to add D_WINAnd carry calculation, the code spelling device (5) outputs the converted N-bit digital code; d_NWhen equal to 0, corresponding digital code D_N-3To subtract D_WINAnd with a borrow calculation, the transcoder (5) outputs the converted N-bit digital code.