CN113794450B - Broadband high-linearity low-noise amplifier adopting linearity optimization technology - Google Patents
Broadband high-linearity low-noise amplifier adopting linearity optimization technology Download PDFInfo
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- CN113794450B CN113794450B CN202110914173.4A CN202110914173A CN113794450B CN 113794450 B CN113794450 B CN 113794450B CN 202110914173 A CN202110914173 A CN 202110914173A CN 113794450 B CN113794450 B CN 113794450B
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The invention belongs to the technical field of radio frequency microwave integrated circuits, and particularly relates to a broadband high-linearity low-noise amplifier adopting a linearity optimization technology. The low noise amplifier mainly includes: an input matching stage consisting of an amplifier and a feedback resistor, an intermediate amplification stage, a noise cancellation stage and a linearity optimization stage consisting of a self-loading structure. The noise cancellation stage amplifies the cross-coupled input signal such that the input useful signal is superimposed at the output and the noise signal is cancelled at the output, reducing the overall noise figure. The self-loading technology is adopted as a linear optimization stage structure, so that the influence on the gain, input matching, noise coefficient and the like of the low-noise amplifier is small, and the linearity is improved; in the working frequency range of 0.3-4GHz, the linearity optimization effect of more than 10dB can be achieved.
Description
Technical Field
The invention belongs to the technical field of radio frequency microwave integrated circuits, and particularly relates to a broadband high-linearity low-noise amplifier applied to a radio frequency front end.
Background
The low noise amplifier acts as the first stage active amplifier of the signal receiver and is critical to the overall performance of the communication system. As a research focus in the current academia and industry, a low noise amplifier having both a low noise figure and a high linearity plays an important role in reducing interference of adjacent channels and generation of intermodulation components in a frequency spectrum. Due to the development of wireless communication technology, frequency spectrum resources are increasingly scarce, and when a receiver front-end receives in-band signals, the receiver front-end often receives out-of-band or in-band strong interference signals, which requires that a low-noise amplifier of the receiver front-end can provide higher linearity in addition to a certain gain and lower noise figure.
The deterioration of linearity of the active circuit generally comes from nonlinear components of transistors, and in order to improve the linearity of the low noise amplifier, domestic and foreign research institutions propose modes such as source degeneration resistance, multi-gate transconductance cancellation, bypass floating power supply and the like. However, these structures suffer from disadvantages such as affecting the main path signal, having too little linearization range, and having too high power consumption in the auxiliary path. On the other hand, the linearity improvement of a low noise amplifier often has an effect on its gain and noise figure. Therefore, how to ensure a lower noise coefficient and improve linearity performance in the design of a broadband high-linearity low-noise amplifier is a main problem in current research.
Disclosure of Invention
The invention aims to provide a low noise amplifier with a wider frequency range, higher linearity and lower noise figure.
The broadband high-linearity low-noise amplifier provided by the invention is realized in a differential structure, and the structure is shown in the attached figure 1. The method specifically comprises an input matching stage, an intermediate amplifying stage, a noise eliminating stage and a linearity optimizing stage consisting of a self-loading structure, wherein:
the input matching stage consists of an amplifier with an inverter structure and a feedback resistor, and is used for receiving signals, so that good matching between a signal source and input impedance is realized in a required frequency band range, and the return loss of the input signals is reduced;
LC network matching is generally not considered in order to implement a broadband low noise amplifier. Meanwhile, as the power consumption of the common-gate matching structure is overlarge, a feedback resistor matching mode can be selected to save the area and the power consumption of a circuit;
the intermediate amplifying stage is connected between the input matching stage and the output end and is used for amplifying the received signal;
the noise elimination stage is connected between the input end RFIN and the output end RFOUT, and amplifies the cross-coupled input signals to strengthen the received signals, counteract the noise of the low-noise amplifier, reduce the overall noise coefficient and improve the output signal-to-noise ratio of the low-noise amplifier; as shown in fig. 2, the useful signal received by the output terminal is overlapped with the inverted signal amplified by the noise cancellation stage in the same phase to form an output signal; meanwhile, noise signals at the input end are amplified in phase at the output end and amplified in opposite phase at the noise elimination path, and the noise signals and the useful signals are mutually offset at the output end, so that useful signals at the output end are enhanced, noise signals are weakened, and the output signal to noise ratio of the low-noise amplifier is greatly improved;
the linearity optimization stage consists of a self-loading structure and is used for counteracting nonlinear components of the amplifier, and the linearity of the amplifier can be improved on the premise of not greatly influencing the performance of the low-noise amplifier. By adopting the linearity optimization technology of the self-loading structure, the distortion component generated by the low-noise amplifier is partially eliminated by adjusting the value of the feedback resistor in the self-loading structure, so that the linearity of the low-noise amplifier is improved. Although the linear optimization stage may cause a certain loss to the gain of the low noise amplifier, since the linearization path is only connected between the two differential output terminals rfout+ and RFOUT-, the linear optimization stage has very little influence on the overall noise figure.
The invention adopts the linearity optimization stage of the self-loading structure, can greatly improve the linearity of the low-noise amplifier, and can achieve the linearity optimization effect of more than 10dB in the working frequency range of 0.3-4 GHz. And only brings less than 1.5dB loss to the gain of the low noise amplifier, and the linearization path is only connected to the output end, so that the influence on the overall noise coefficient is very small.
Drawings
Fig. 1 is a block diagram of a low noise amplifier according to the present invention.
Fig. 2 is a specific construction diagram of a low noise amplifier according to the present invention.
FIG. 3 is a graph showing the effect of the adjustable resistance of the self-loading structure on the overall linearity in an embodiment of the present invention.
Fig. 4 shows the comparison of S parameter changes before and after the addition of the linearity optimization stage in the embodiment of the present invention.
FIG. 5 is a comparison of noise figure changes before and after the addition of the linearity optimization stage in an embodiment of the present invention.
FIG. 6 shows the comparison of linearity changes before and after the addition of the linearity optimization stage in an embodiment of the present invention.
Detailed Description
The invention is further described below with reference to the drawings and detailed description.
As shown in fig. 2, a specific structure of a wideband high linearity low noise amplifier adopting a linearity optimization technology provided by the invention comprises: an input matching stage, an intermediate amplification stage, a noise cancellation stage and a linearity optimization stage.
The input matching stage consists of an MOS tube M 1 ~M 4 Resistor R FM1 、R FM2 Composition is prepared. Wherein MOS tube M 1 ~M 4 Amplifier with complementary CMOS structure and resistor R FM1 、R FM2 As a feedback resistor of the amplifier, the input impedance of the input matching stage is controlled. The input signal is input to the input matching stage of the low noise amplifier in differential form, and the impedance R of the input signal source is selected in design to match the input S =R FM /(1+A V ) Wherein A is V Is M 1 ~M 4 Gain, R of constituent amplifier S Is the impedance of the input signal source. When the input meets the matching requirement, S can be met in the required frequency band 11 <10dB, the degree of input matching may be limited due to parasitic capacitance effects at high frequencies.
Further, the signal passing through the input matching stage circuit is amplified by a second stage amplifying circuit, i.e., an intermediate amplifier. The intermediate amplifying circuit comprises an MOS tube M 5 ~M 8 The grid drain electrode of the NMOS tube is connected with the grid drain electrode of the PMOS tube, and the source electrode is respectively connected with GND and V DD An amplifier constituting an inverter structure. Compared with other structures, the amplifier with the inverter structure has the characteristics of simple structure, large transconductance current ratio, relatively small power consumption and noise and the like. In addition, the parasitic capacitance of the output node is smaller, and the working frequency band of the low-noise amplifier can be widened.
The noise elimination stage consists of a MOS tube M 9 ~M 16 Composition is prepared. As shown in FIG. 2, wherein M 9 、M 12 、M 13 、M 16 As a control tube for the noise cancellation stage, it is possible to control M 9 、M 12 、M 13 、M 16 Gate electricity of (2)The voltage controls the switching and depth of noise cancellation. When the received signal and noise are simultaneously input into the differential input port of the low noise amplifier, the useful received signal passes through the MOS tube M 1 ~M 4 Resistor R FM1 、R FM2 The input matching stage is amplified in opposite phase and then passes through MOS tube M 5 ~M 8 The composed intermediate amplification stage is again amplified in antiphase; the other way of the liquid crystal is reversed to enter the MOS tube M 9 ~M 16 The noise eliminating stage is inversely amplified, and the useful signals of the two paths are inversely amplified twice and superposed at the output end to form the output signal. Because the in-phase noise generated by the input matching stage at the two input ends is mutually opposite-phase signals at the output ends when passing through the two paths, the signals can be mutually offset, and the overall signal-to-noise ratio of the low-noise amplifier is improved.
The linearity optimization stage consists of a MOS tube M 17 ~M 20 And resistance R LE1 、R LE2 Composition, wherein MOS tube M 17 ~M 20 Amplifier, resistor R forming inverter structure LE1 、R LE2 Is a variable resistor. The linearity optimization scheme can be defined as a self-loading structure, wherein the input end of the self-loading structure is connected with the output end of the low-noise amplifier, and the output end of the self-loading structure floats. As shown in fig. 1, according to kirchhoff's current law, at the output end of the low noise amplifier, nonlinear components in the output current of the amplifier are offset by nonlinear components in the output current of the self-load structure, so as to achieve the linearization effect. Since the self-loading structure does not need a large gain, M 17 ~M 20 The size is smaller, and the variable resistance R can be adjusted LE1 、R LE2 So that the linearity of the low noise amplifier is optimized as shown in fig. 3.
The S-parameter curve and the noise coefficient curve of the low-noise amplifier with broadband low power consumption and high linearity in the specific examples are shown in fig. 4 and fig. 5 respectively. From the results of fig. 4 and 5, the linear optimization technique proposed by the present invention ensures that the low noise amplifier input matching and noise figure conditions are both less affected on the gain. Finally, under the condition of double-tone signals at intervals of 1MHz, the linearity performance of the low-noise amplifier in the frequency band of 0.3-4GHz is tested, and the result is shown in figure 5. As shown in figure 5, the self-load linear optimization technology provided by the invention can realize linear optimization of more than 10dB in a frequency band of 0.3-4GHz, so that the advancement and uniqueness of the self-load linear optimization technology are shown.
Claims (4)
1. The broadband high-linearity low-noise amplifier adopting the linearity optimization technology is realized in a differential structure, and is characterized by comprising an input matching stage, an intermediate amplifying stage, a noise elimination stage and a linearity optimization stage formed by a self-loading structure, wherein:
the input matching stage consists of an amplifier with an inverter structure and a feedback resistor, and is used for receiving signals, so that good matching between a signal source and input impedance is realized in a required frequency band range, and the return loss of the input signals is reduced;
the intermediate amplifying stage is connected between the input matching stage and the output end and is used for amplifying the received signal;
the noise elimination stage is connected between the input end RFIN and the output end RFOUT, and amplifies the cross-coupled input signals to strengthen the received signals, counteract the noise of the low-noise amplifier, reduce the overall noise coefficient and improve the output signal-to-noise ratio of the low-noise amplifier;
the linearity optimization stage is connected between the two differential output ends RFOUT+ and RFOUT-and is used for counteracting nonlinear components of the amplifier and improving the linearity of the low-noise amplifier on the premise of not greatly influencing the performance of the low-noise amplifier; the linearity optimization technology of the self-loading structure is adopted, and the distortion component generated by the low-noise amplifier is partially eliminated by adjusting the value of the feedback resistor in the self-loading structure, so that the linearity of the low-noise amplifier is improved;
the linearity optimization stage consists of a MOS tube M 17 ~M 20 And resistance R LE1 、R LE2 Composition; wherein, MOS tube M 17 ~M 20 Amplifier, resistor R forming inverter structure LE1 、R LE2 Is a variable resistor; wherein, NMOS tube M 17 And PMOS tube M 18 Gate interconnect and drain interconnect, NMOS transistor M 17 Is connected with GND, PMOS tube M 18 Source connection V of (2) DD ，R LE1 Is connected with NMOS tube M 17 And PMOS tube M 18 Between the gate and the drain; NMOS tube M 19 And PMOS tube M 20 Gate interconnect and drain interconnect, NMOS transistor M 19 Is connected with GND, PMOS tube M 20 Source connection V of (2) DD ，R LE2 Is connected with NMOS tube M 19 And PMOS tube M 20 Between the gate and the drain; the linearity optimization is defined as a self-loading structure, the input end of the self-loading structure is connected with the output end of the low-noise amplifier, and the output end of the self-loading structure floats; by adjusting the variable resistance R LE1 、R LE2 So that the linearity of the low noise amplifier is optimized.
2. The wideband high linearity low noise amplifier of claim 1 wherein said input matching stage is comprised of a MOS transistor M 1 ~M 4 Resistor R FM1 、R FM2 Composition; NMOS tube M 1 And PMOS tube M 2 Gate interconnect and drain interconnect, NMOS transistor M 1 Is connected with GND, PMOS tube M 2 Source connection V of (2) DD ，R FM1 Is connected with NMOS tube M 1 And PMOS tube M 2 Between the gate and the drain; NMOS tube M 3 And PMOS tube M 4 Gate interconnect and drain interconnect, NMOS transistor M 3 Is connected with GND, PMOS tube M 4 Source connection V of (2) DD ，R FM2 Is connected with NMOS tube M 3 And PMOS tube M 4 Between the gate and the drain; wherein, MOS tube M 1 ~M 4 Amplifier with complementary CMOS structure and resistor R FM1 、R FM2 As a feedback resistor of the amplifier, controlling the input impedance of the input matching stage; the input signal is input in differential form to the input matching stage of the low noise amplifier.
3. The wideband high linearity low noise amplifier of claim 1 wherein saidThe intermediate amplifying stage comprises a MOS tube M 5 ~M 8 Wherein, NMOS tube M 5 And PMOS tube M 6 Gate interconnect and drain interconnect, NMOS transistor M 5 Is connected with GND, PMOS tube M 6 Source connection V of (2) DD The method comprises the steps of carrying out a first treatment on the surface of the NMOS tube M 7 And PMOS tube M 8 Gate interconnect and drain interconnect, NMOS transistor M 7 Is connected with GND, PMOS tube M 8 Source connection V of (2) DD The method comprises the steps of carrying out a first treatment on the surface of the The grid drain electrode of the NMOS tube is connected with the grid drain electrode of the PMOS tube, and the source electrode is respectively connected with GND and V DD An amplifier constituting an inverter structure.
4. The wideband high linearity low noise amplifier of claim 1 wherein said noise cancellation stage is formed by a MOS transistor M 9 ~M 16 Composition; NMOS tube M 15 And PMOS tube M 14 Gate interconnect and drain interconnect, NMOS transistor M 15 Source electrode of (d) and NMOS tube M 16 Is connected with the drain electrode of the PMOS tube M 14 Source electrode of (C) and PMOS tube M 13 Drain electrode connection of NMOS tube M 16 Bias BIASN2 with source electrode connected with GND and gate electrode connected with NMOS, PMOS tube M 13 Source connection V of (2) DD And the grid is connected with bias BIASP2 of the PMOS; NMOS tube M 11 And PMOS tube M 10 Gate interconnect and drain interconnect, NMOS transistor M 11 Source electrode of (d) and NMOS tube M 12 Is connected with the drain electrode of the PMOS tube M 10 Source electrode of (C) and PMOS tube M 9 Drain electrode connection of NMOS tube M 12 Bias BIASN1 with source electrode connected with GND and gate electrode connected with NMOS, PMOS tube M 9 Source connection V of (2) DD And the grid is connected with bias BIASP1 of the PMOS; wherein M is 9 、M 12 、M 13 、M 16 As a control tube for noise cancellation stage, by controlling M 9 、M 12 、M 13 、M 16 To control the switching and depth of noise cancellation; when the received signal and noise are simultaneously input into the differential input port of the low noise amplifier, the useful received signal passes through the MOS tube M 1 ~M 4 Resistor R FM1 、R FM2 The input matching stage is amplified in opposite phase and then passes through MOS tube M 5 ~M 8 The composed intermediate amplification stage is again amplified in antiphase; the other way of the liquid crystal is reversed to enter the MOS tube M 9 ~M 16 The noise elimination stage is amplified in opposite phase, and the useful signals of the two paths amplified in opposite phase are overlapped at the output end to form an output signal; because the in-phase noise generated by the input matching stage at the two input ends is mutually opposite-phase signals at the output ends when passing through the two paths, the signals can be mutually offset, and the overall signal-to-noise ratio of the low-noise amplifier is improved.
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