CN212210952U - Variable gain low noise amplifier with broadband flat gain - Google Patents
Variable gain low noise amplifier with broadband flat gain Download PDFInfo
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- CN212210952U CN212210952U CN202020719651.7U CN202020719651U CN212210952U CN 212210952 U CN212210952 U CN 212210952U CN 202020719651 U CN202020719651 U CN 202020719651U CN 212210952 U CN212210952 U CN 212210952U
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Abstract
The utility model discloses a variable gain low noise amplifier of flat gain of broadband. The amplifier comprises a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a first inductor, a second inductor, a third inductor, a fourth inductor, a fifth inductor, a first bias resistor, a second bias resistor, a first NMOS transistor, a second NMOS transistor, a first group of switching transistors, a second group of switching transistors, n resistors, n control voltages, direct current bias and a power supply; the first group of switch transistors and the second group of switch transistors respectively comprise n switch transistors. The utility model realizes the compromise between better noise matching and broadband input matching by adopting the transformer to input the grid drain of the transistor, and realizes the flat gain response of the broadband by the double-grid inductive peaking technology; the digital switch pair realizes the control of the voltage flat gain.
Description
Technical Field
The utility model relates to an electronic communication technology's millimeter wave front end circuit field, concretely relates to flat gain's of broadband low noise amplifier.
Background
In recent years, many research institutes in the industry and academia have turned the research focus to the fifth generation (5G) communication, and the millimeter wave front end circuit is an important ring in the 5G communication system, wherein one key is the low noise amplifier located at the first stage of the receiver front end circuit. In a 5G phased array receiver, a variable gain low noise amplifier would be a more attractive option, and when a weak RF signal enters the receiver, the low noise amplifier needs to have the highest gain and the lowest noise figure; on the other hand, if the input RF signal is strong, the low noise amplifier provides medium gain and high linearity to prevent the receiver from saturating.
In the prior implemented variable gain low noise amplifier scheme, (Kim S, Kim H C, Kim D H, et al 58-72GHz CMOS wireless variable gain low-noise amplifier [ J ]. Electronics Letters, 2011, 47(16): 904.) a simulated current-steering variable gain amplifier is disclosed, with a 3dB gain bandwidth of 58.5-73 GHz, a relative bandwidth of 11%, a 1dB flat gain bandwidth of 10 GHz, and a noise figure of 4.2 dB; (Hsieh, Y.K., Kuo, J.L., Wang, H., and Lu, L.H. A60 GHz broadband low-noise amplifier with variable-gain control in 65 nm CMOS, IEEE micro. wire. Comp. Lett., 2011, 21, (11), pp. 610-; (Chang, Yu-Teng & Lu, Hsin-Chia. A V-Band Low-Power Digital Variable-Gain Low-Noise Amplifier Using Current-Reused Technique With Stable Matching and Maintained OP1dB. IEEE Transactions on Microwave Theory and techniques. PP. 1-14.10.1109/TMTT.2019.2938752.) A Digital Current-steering Variable-Gain Low Noise Amplifier is disclosed, the center frequency is 60GHz, the 3dB Gain bandwidth is 10 GHz, the relative bandwidth is 16.7%, the 1dB flat Gain bandwidth is 4 GHz, and the Noise figure is 6 dB.
The variable gain low noise amplifier in the above-mentioned scheme of the variable gain low noise amplifier that has been realized has a narrow bandwidth and a low 1dB gain flatness, and the gain bandwidth and 1dB flatness of the broadband cannot be maintained in different gain modes.
SUMMERY OF THE UTILITY MODEL
The utility model provides a flat gain's of broadband variable gain low noise amplifier, aim at realize the flat gain of variable broadband.
The purpose of the utility model is realized through one of following technical scheme.
A variable gain low noise amplifier with broadband flat gain comprises a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a first inductor, a second inductor, a third inductor, a fourth inductor, a fifth inductor, a first bias resistor, a second bias resistor, a first NMOS transistor, a second NMOS transistor, a first group of switch transistors, a second group of switch transistors, n resistors, n control voltages, a direct current bias and a power supply; the first group of switch transistors and the second group of switch transistors respectively comprise n switch transistors;
the input end is connected to the negative end of the first inductor through the first capacitor, and the direct current bias is connected to the negative end of the first inductor through the first bias resistor for biasing; the positive end of the first inductor is connected to the grid electrode of the first NMOS transistor, the source electrode of the first NMOS transistor is grounded, and the drain electrode of the first NMOS transistor is connected to the positive end of the second inductor; the positive end of the first inductor is coupled with the positive end of the second inductor, the coupling coefficient is k, and the first inductor and the second inductor form a transformer;
the negative end of the second inductor is connected with the negative end of the third inductor, and the negative end of the second inductor and the negative end of the third inductor are both connected with the second capacitor; the other end of the second capacitor is connected with the negative end of the fourth inductor and is connected to one end of a second bias resistor, and the other end of the second bias resistor is connected with the negative end of the fifth inductor and is connected to a power supply; the positive end of the fourth inductor is connected with the grid electrode of the second NMOS transistor, and the drain electrode of the second NMOS transistor is connected with the positive end of the fifth inductor; the source of the second NMOS transistor is connected with the positive end of the third inductor, the source of the second NMOS transistor and the positive end of the third inductor are both connected with the third capacitor, and the other end of the third capacitor is grounded; the positive end of the fifth inductor is connected with the output end;
the negative end of the second inductor and the negative end of the third inductor are both connected with one end of a fourth capacitor, and the other end of the fourth capacitor is connected with the drain electrode of the first group of switching transistors; the output end OUT is connected with one end of a fifth capacitor, and the other end of the fifth capacitor is connected with the drain electrode of the second group of switching transistors; the source electrodes of the first group of switching transistors and the second group of switching transistors are grounded; the first group of switch transistors and the second group of switch transistors form n pairs of digital switch pairs, the grids of the corresponding transistors are respectively connected with n control voltages through n resistors, and the other ends of the n control voltages are grounded.
Furthermore, the first capacitor, the fourth capacitor and the fifth capacitor are all blocking capacitors, the second capacitor is an alternating current coupling capacitor, and the third capacitor is a bypass capacitor; the first inductor and the second inductor form a source-drain transformer, and the third inductor is an isolated inductor.
Furthermore, the values of the first capacitor, the second capacitor, the third capacitor, the fourth capacitor and the fifth capacitor are all 1 pF; the value range of the first inductor is 200-300 pH, the value range of the second inductor is 50-130 pH, the value range of the third inductor is larger than 600pH, the value range of the fourth inductor is 150-220 pH, the value range of the fifth inductor is 130-180 pH, and the values of the first bias resistor, the second bias resistor and the n resistors are all larger than 5k omega; the values of the n control voltages are 0V or 1V; the value of the power supply is 1V.
Further, a gate-drain transformer is used at the input transistor, i.e. the first NMOS transistor, to achieve broadband input matching, to enhance the trade-off between noise matching and broadband input matching, to achieve broadband flat gain response using a dual-gate inductive peaking technique, and to achieve voltage flat gain control through n pairs of digital switch pairs.
Furthermore, the gain of the flat broadband is mainly realized through a first inductor and a fourth inductor, and two main poles are generated by a dual-gate inductance peaking technology through adding inductors to the gates of two common-source tubes of a current multiplexing common-source-common-source cascade; the first inductor and the first NMOS transistor realize generation of a first conjugate pole, namely a low-frequency pole, and the fourth inductor and the second NMOS transistor generate a second conjugate pole, namely a high-frequency pole; the dominant poles of the two different frequencies control the width and flatness of the gain of the overall circuit.
Furthermore, the realization of the flat-broadband variable gain is that digital switch control is simultaneously used for the output of each stage of common-source amplifier, a pair of digital switches is formed to control and attenuate the gain bandwidth, mainly the control and attenuation of the gain are carried out on the signals at the two generated dominant pole frequencies, and finally the flat gain control in the bandwidth is realized on the basis of the flat-broadband gain bandwidth; the gain control or gain stepping control of multiple modes is realized by adding corresponding digital switches in parallel:
when the n control voltages are all 0V, the highest gain can be realized;
when the n control voltages are all 1V, the lowest gain can be realized;
multimode gain control can be achieved by different (0V, 1V) combinations of the n control voltages.
Compared with the prior art, the utility model has the advantages of:
the utility model realizes the compromise between better noise matching and broadband input matching by adopting the transformer to input the grid drain of the transistor, and realizes the flat gain response of the broadband by the double-grid inductive peaking technology; the digital switch pair realizes the control of the voltage flat gain.
Drawings
Fig. 1 is a schematic diagram of a broadband flat gain variable gain low noise amplifier according to the present invention;
fig. 2 is a schematic diagram of the S parameter in the high gain mode according to an embodiment of the present invention;
FIG. 3 is a gain comparison diagram of the high and low gain modes according to an embodiment of the present invention;
fig. 4 is a comparison graph of noise coefficients of high and low gain modes according to an embodiment of the present invention.
Detailed Description
For a better understanding of the objects, technical solutions and advantages of the present invention, the following detailed description of the present invention is provided in conjunction with the accompanying drawings.
Example (b):
a variable gain low noise amplifier with broadband flat gain is disclosed, as shown in FIG. 1, comprising a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a first inductor L1, a second inductor L2, a third inductor L3, a fourth inductor L4, a fifth inductor L5, a first bias resistor RB1, a second bias resistor RB2, a first NMOS transistor M1, a second NMOS transistor M2, a first group of switch transistors, a second group of switch transistors, n resistors, n control voltages, a DC bias VB1 and a power supply VDD; the first group of switch transistors and the second group of switch transistors respectively comprise n switch transistors;
the input end IN is connected to the negative end of the first inductor L1 through a first capacitor C1, and the direct current bias VB1 is connected to the negative end of the first inductor L1 through a first bias resistor RB1 for biasing; the positive terminal of the first inductor L1 is connected to the gate of the first NMOS transistor M1, the source of the first NMOS transistor M1 is grounded, and the drain of the first NMOS transistor M1 is connected to the positive terminal of the second inductor L2; the positive terminal of the first inductor L1 and the positive terminal of the second inductor L2 are coupled, the coupling coefficient is k, and the first inductor L1 and the second inductor L2 form a transformer;
the negative end of the second inductor L2 is connected with the negative end of the third inductor L3, and the negative end of the second inductor L2 and the negative end of the third inductor L3 are both connected with the second capacitor C2; the other end of the second capacitor C2 is connected to the negative terminal of the fourth inductor L4 and to one end of a second bias resistor RB2, and the other end of the second bias resistor RB2 is connected to the negative terminal of the fifth inductor L5 and to the power supply VDD; the positive terminal of the fourth inductor L4 is connected to the gate of the second NMOS transistor M2, and the drain of the second NMOS transistor M2 is connected to the positive terminal of the fifth inductor L5; the source of the second NMOS transistor M2 is connected to the positive terminal of the third inductor L3, the source of the second NMOS transistor M2 and the positive terminal of the third inductor L3 are both connected to the third capacitor C3, and the other terminal of the third capacitor C3 is grounded; the positive end of the fifth inductor L5 is connected with the output end OUT;
the negative end of the second inductor L2 and the negative end of the third inductor L3 are both connected with one end of a fourth capacitor C4, and the other end of the fourth capacitor C4 is connected with the drains of the first group of switching transistors Ma 1-Man; the output end OUT is connected with one end of a fifth capacitor C5, and the other end of the fifth capacitor C5 is connected with the drains of the second group of switching transistors Mb 1-Mbn; the source electrodes of the first group of switching transistors Ma 1-Man and the second group of switching transistors Mb 1-Mbn are grounded; the first group of switching transistors Ma 1-Man and the second group of switching transistors Mb 1-Mbn form n pairs of digital switch pairs (Ma 1, Mb 1) - (Man, Mbn), the grids of the corresponding transistors are respectively connected with n control voltages VCTRL 1-VCTRLn through n resistors R1-Rn, and the other ends of the n control voltages VCTRL 1-VCTRLn are grounded.
The first capacitor C1, the fourth capacitor C4 and the fifth capacitor C5 are all blocking capacitors, the second capacitor C2 is an alternating current coupling capacitor, and the third capacitor C3 is a bypass capacitor; the first inductor L1 and the second inductor L2 form a source-drain transformer, and the third inductor L3 is a crossover inductor.
In this embodiment, the values of the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4 and the fifth capacitor C5 are all 1 pF; the value of the first inductor L1 is 280pH, the value of the second inductor L2 is 70pH, the value of the third inductor L3 is 850pH, the value of the fourth inductor L4 is 160pH, the value of the fifth inductor L5 is 140pH, and the values of the first bias resistor RB1, the second bias resistor RB2 and the n resistors are all 10k omega; according to different gain modes, the n control voltages can be 0V (high gain) or 1V (low gain); the value of the power supply VDD is 1V.
The utility model discloses use the grid leakage transformer to realize the broadband input matching in input transistor first NMOS transistor M1 department promptly, the reinforcing is to carrying out the compromise between the input matching of noise matching and broadband, uses the flat gain response of dual gate inductance peaking technique realization broadband to and realize the control of voltage flat gain to digital switch pair (Ma 1, Mb 1) ~ (Man, Mbn) through n.
The gain of the flat broadband is mainly realized through a first inductor L1 and a fourth inductor L4, and two main poles are generated by a dual-gate inductance peaking technology through adding inductors to the gates of two common source tubes of a current multiplexing common source-common source cascade; the first inductor L1 and the first NMOS transistor M1 may implement generation of a first conjugate pole, i.e., a low frequency pole, and the fourth inductor L4 and the second NMOS transistor M2 may generate a second conjugate pole, i.e., a high frequency pole; the dominant poles of the two different frequencies control the width and flatness of the gain of the overall circuit.
The realization of the flat variable gain of the broadband is that the output of each stage of common source amplifier is simultaneously controlled by using a digital switch to form a pair of digital switches to control and attenuate the gain bandwidth, mainly to control and attenuate the gain of the signals at the frequency of two dominant poles, and finally to realize the flat gain control in the bandwidth on the basis of the flat gain bandwidth of the broadband; multimode gain control or gain stepping control can be realized by adding corresponding digital switch pairs (Ma 1, Mb 1) - (Man, Mbn) in parallel:
when the n control voltages VCTRL 1-VCTRLn are all 0V, the highest gain Av can be realizedmax；
When the n control voltages VCTRL 1-VCTRLn are all 1V, the lowest gain Av can be realizedmin；
The gain control of multiple modes can be realized by carrying out different (0V, 1V) combinations on the n control voltages VCTRL 1-VCTRLn.
As shown in FIG. 2, the S parameters in the high gain mode are S11 and S21 respectively, and it can be seen that the 3dB gain bandwidth is 18-62GHz, the relative bandwidth is 110%, the frequency range of the 1dB gain bandwidth is 22-57GHz, the low noise amplifier of the prior art shows excellent relative bandwidth and 1dB flat gain bandwidth, and the frequency range of S11< -10dB is 22-60 GHz; FIG. 3 is a comparison of the noise figure in the high and low gain modes, showing that the noise figure in the high gain mode is less than 4dB in the frequency range of 20-60 GHz. In both the high gain and low gain modes, the condition of broadband flat gain can be realized, and low noise in the whole frequency band can still be realized; FIG. 4 is a gain contrast graph for high and low gain modes, showing a high and low voltage gain control map for a digital switch pair, where the gain in the low gain mode still maintains a broadband flat gain mode in the high gain mode, and the pair of switches can be adjusted to approximately 5dB and maintain a stable gain curve. Fig. 2 and 3 illustrate the trade-off between better noise matching and broadband input matching achieved with a transformer through the gate-drain of the input transistor, and the dual-gate inductive peaking technique achieves a flat gain response in the broadband. Fig. 3 and 4 illustrate that a digital switch pair can achieve control of the voltage flat gain with good noise.
Claims (5)
1. The variable gain low noise amplifier with the broadband flat gain is characterized by comprising a first capacitor (C1), a second capacitor (C2), a third capacitor (C3), a fourth capacitor (C4), a fifth capacitor (C5), a first inductor (L1), a second inductor (L2), a third inductor (L3), a fourth inductor (L4), a fifth inductor (L5), a first bias resistor (RB 1), a second bias resistor (RB 2), a first NMOS transistor (M1), a second NMOS transistor (M2), a first group of switch transistors, a second group of switch transistors, n resistors, n control voltages, a direct current bias (VB 1) and a power supply (VDD); the first group of switch transistors and the second group of switch transistors respectively comprise n switch transistors;
the input end (IN) is connected to the negative end of the first inductor (L1) through a first capacitor (C1), and the direct current bias (VB 1) is connected to the negative end of the first inductor (L1) through a first bias resistor (RB 1) for biasing; the positive terminal of the first inductor (L1) is connected to the gate of the first NMOS transistor (M1), the source of the first NMOS transistor (M1) is grounded, and the drain of the first NMOS transistor (M1) is connected to the positive terminal of the second inductor (L2); the positive terminal of the first inductor (L1) and the positive terminal of the second inductor (L2) are coupled, the coupling coefficient is k, and the first inductor (L1) and the second inductor (L2) form a transformer;
the negative end of the second inductor (L2) is connected with the negative end of the third inductor (L3), and the negative end of the second inductor (L2) and the negative end of the third inductor (L3) are both connected with the second capacitor (C2); the other end of the second capacitor (C2) is connected with the negative end of the fourth inductor (L4) and is connected to one end of a second bias resistor (RB 2), and the other end of the second bias resistor (RB 2) is connected with the negative end of the fifth inductor (L5) and is connected to the power supply (VDD); the positive terminal of the fourth inductor (L4) is connected with the gate of the second NMOS transistor (M2), and the drain of the second NMOS transistor (M2) is connected with the positive terminal of the fifth inductor (L5); the source of the second NMOS transistor (M2) is connected with the positive end of the third inductor (L3), the source of the second NMOS transistor (M2) and the positive end of the third inductor (L3) are both connected with the third capacitor (C3), and the other end of the third capacitor (C3) is grounded; the positive end of the fifth inductor (L5) is connected with the output end (OUT);
the negative end of the second inductor (L2) and the negative end of the third inductor (L3) are both connected with one end of a fourth capacitor (C4), and the other end of the fourth capacitor (C4) is connected with the drains of the first group of switching transistors (Ma 1-Man); the output end (OUT) is connected with one end of a fifth capacitor (C5), and the other end of the fifth capacitor (C5) is connected with the drains of a second group of switching transistors (Mb 1-Mbn); the source of the first set of switching transistors (Ma 1 to Man) and the second set of switching transistors (Mb 1 to Mbn) is grounded; the first group of switching transistors (Ma 1-Man) and the second group of switching transistors (Mb 1-Mbn) form n pairs of digital switch pairs ((Ma 1, Mb 1) - (Man, Mbn)), the grid electrodes of the corresponding transistors are respectively connected with n control voltages (VCTRL 1-VCTRLn) through n resistors (R1-Rn), and the other ends of the n control voltages (VCTRL 1-VCTRLn) are grounded.
2. The broadband flat-gain variable-gain low-noise amplifier according to claim 1, wherein the first capacitor (C1), the fourth capacitor (C4) and the fifth capacitor (C5) are all dc blocking capacitors, the second capacitor (C2) is an ac coupling capacitor, and the third capacitor (C3) is a bypass capacitor; the first inductor (L1) and the second inductor (L2) form a source-drain transformer, and the third inductor (L3) is an isolated inductor.
3. The broadband flat-gain variable-gain low-noise amplifier according to claim 1, wherein the first capacitor (C1), the second capacitor (C2), the third capacitor (C3), the fourth capacitor (C4) and the fifth capacitor (C5) all have a value of 1 pF; the value range of the first inductor (L1) is 200-300 pH, the value range of the second inductor (L2) is 50-130 pH, the value range of the third inductor (L3) is larger than 600pH, the value range of the fourth inductor (L4) is 150-220 pH, the value range of the fifth inductor (L5) is 130-180 pH, and the values of the first bias resistor (RB 1), the second bias resistor (RB 2) and the n resistors are all larger than 5k omega; the values of the n control voltages are 0V or 1V; the value of the power supply (VDD) is 1V.
4. A broadband flat-gain variable-gain low-noise amplifier according to claim 1, characterized in that at the input transistor, the first NMOS transistor (M1), a gate-drain transformer is used to achieve broadband input matching, the trade-off between noise matching and broadband input matching is enhanced, a dual-gate inductive peaking technique is used to achieve broadband flat-gain response, and control of voltage flat-gain is achieved by n pairs of digital switch pairs (Ma 1, Mb 1) — (Man, Mbn).
5. The broadband flat-gain variable-gain low-noise amplifier as claimed in claim 4, wherein the flat broadband gain is mainly realized by a first inductor (L1) and a fourth inductor (L4), and the dual-gate inductive peaking technique is realized by adding inductors to the gates of two common-source tubes of the current-multiplexed common-source-common-source cascade to generate two main poles; the first inductor (L1) and the first NMOS transistor (M1) realize the generation of a first conjugate pole, namely a low-frequency pole, and the fourth inductor (L4) and the second NMOS transistor (M2) generate a second conjugate pole, namely a high-frequency pole; the dominant poles of the two different frequencies control the width and flatness of the gain of the overall circuit.
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| CN111404492A (en) * | 2020-04-30 | 2020-07-10 | 华南理工大学 | Variable gain low noise amplifier with broadband flat gain |
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