CN113782489A - Through silicon via and forming method thereof - Google Patents
Through silicon via and forming method thereof Download PDFInfo
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- CN113782489A CN113782489A CN202110994115.7A CN202110994115A CN113782489A CN 113782489 A CN113782489 A CN 113782489A CN 202110994115 A CN202110994115 A CN 202110994115A CN 113782489 A CN113782489 A CN 113782489A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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Abstract
The application discloses a through silicon via and a forming method thereof, wherein the method comprises the following steps: providing a substrate, wherein a semiconductor device is formed on the front surface of the substrate, and a first interlayer dielectric layer covers the substrate and the semiconductor device; etching the front surface, and removing the first interlayer dielectric layer of the first target area to form a first groove; etching the front surface, and forming a first through hole in the substrate at the bottom of the first groove; filling metal in the first through hole to form the upper part of the silicon through hole; etching the back surface of the substrate to form a second through hole, wherein the second through hole is positioned below the first through hole, and the upper part of the silicon through hole at the bottom of the second through hole is exposed; and filling metal in the second through hole to form a lower part of the through silicon via, wherein the upper part of the through silicon via and the lower part of the through silicon via form the through silicon via. This application is through the trompil separately on the two sides of substrate, and the filler metal forms the through-silicon via who runs through the substrate, has solved the through-silicon via who provides among the correlation technique and has formed the problem of outstanding defect at the back easily, has improved the yield of product.
Description
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a through silicon via and a forming method thereof.
Background
A Through Silicon Via (TSV) is a structure formed by forming a through hole through a wafer and filling the through hole with metal, and is used to connect devices on the front and back of the wafer.
Referring to fig. 1, a schematic cross-sectional view of a through-silicon via formed by a method for forming a through-silicon via provided in the related art is shown. As shown in fig. 1, a through hole is etched in the substrate 110, and the through hole is filled with a metal to form a through silicon via 111, where the through silicon via 111 is used to connect a semiconductor device (not shown in fig. 1) formed on the front surface of the substrate 110 and a metal layer (not shown in fig. 1) formed on the back surface of the substrate 110 in a subsequent process.
However, through the through-silicon via formed by the related art, after subsequent back etching, a protruding defect of the through-silicon via (as shown by a dotted line in fig. 1) may occur, thereby affecting the morphology of a chip product and reducing the reliability of a device.
Disclosure of Invention
The application provides a through silicon via and a forming method thereof, which can solve the problem that the forming method of the through silicon via provided by the related technology is formed by etching through hole filling metal from one side, so that the protruding defect is caused.
In one aspect, an embodiment of the present application provides a method for forming a through silicon via, including:
providing a substrate, wherein a semiconductor device is formed on the front surface of the substrate, and a first interlayer dielectric (ILD) layer covers the substrate and the semiconductor device;
etching from the front side, and removing the first interlayer dielectric layer of the first target area to form a first groove;
etching from the front surface, and forming a first through hole in the substrate at the bottom of the first groove;
filling metal in the first through hole to form the upper part of the silicon through hole;
thinning the substrate from the back side of the substrate;
etching from the back of the substrate to form a second through hole, wherein the second through hole is positioned below the first through hole, and the upper part of the through silicon hole at the bottom of the second through hole is exposed;
and filling metal in the second through hole to form the lower part of the through silicon via, wherein the upper part of the through silicon via and the lower part of the through silicon via form the through silicon via.
Optionally, the filling of metal in the first via hole includes:
forming a first barrier layer (barrier layer) on the front surface, the first barrier layer covering surfaces of the first interlayer dielectric layer, the first trench, and the first via;
forming a first metal layer on the surface of the first barrier layer;
etching is carried out from the front surface, and the first metal layer except the first through hole is removed;
forming a second metal layer covering the first barrier layer and the first metal layer;
and carrying out planarization to remove the second metal layer except the first through hole.
Optionally, the filling metal in the second through hole includes:
forming a second barrier layer on the back surface, wherein the second barrier layer covers the back surface of the substrate and the surface of the second through hole;
forming a third metal layer on the surface of the second barrier layer;
and flattening, and removing the third metal layer except the second through hole.
Optionally, the first barrier layer and the second barrier layer comprise titanium nitride (TiN).
Optionally, the first metal layer, the second metal layer, and the third metal layer include tungsten (W).
Optionally, the semiconductor device includes a gate oxide formed on the front surface, and a gate formed on the gate oxide, and a first heavily doped region and a second heavily doped region are formed in the substrate on both sides of the gate.
Optionally, after forming the upper portion of the through silicon via and before forming the lower portion of the through silicon via, the method further includes:
and forming a metal interconnection structure above the front surface, wherein the metal interconnection structure is used for leading out the first heavily doped region, the second heavily doped region, the grid and the through silicon via.
In another aspect, an embodiment of the present application provides a device including a through silicon via, including:
the semiconductor device comprises a substrate, wherein a semiconductor device and a through silicon via are formed on the front surface of the substrate;
the through silicon via comprises an upper part and a lower part, the width of the top end of the upper part is larger than that of the bottom end of the upper part, the width of the top end of the lower part is larger than that of the bottom end of the lower part, the top end of the upper part is positioned on the front surface of the substrate, the top end of the lower part is positioned on the back surface of the substrate, and the bottom end of the upper part is connected with the bottom end of the lower part.
Optionally, the upper portion includes a barrier layer and a metal layer in sequence from outside to inside, and the lower portion includes a barrier layer and a metal layer in sequence from outside to inside.
Optionally, the barrier layer includes titanium nitride, and the metal layer includes tungsten.
The technical scheme at least comprises the following advantages:
the first through hole is formed on the front surface of the substrate, the upper part of the silicon through hole is formed after metal is filled, the second through hole is formed on the back surface of the substrate, the lower part of the silicon through hole is formed after metal is filled, and the silicon through hole penetrating through the substrate is formed by the upper part and the lower part, so that the problem that the protruding defect is formed on the back surface due to the fact that the through hole penetrating through the front surface of the substrate is formed by filling metal to form the silicon through hole is solved, and the yield of products is improved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic cross-sectional view of a through-silicon-via formed by a method for forming a through-silicon-via provided in the related art;
fig. 2 is a flow chart of a method for forming a through silicon via provided by an exemplary embodiment of the present application;
fig. 3-19 are schematic diagrams illustrating formation of a device including a through silicon via provided by an exemplary embodiment of the present application;
fig. 20 is a flow chart of a method of forming a metal interconnect structure provided in an exemplary embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 2, a flow chart of a method for forming a through silicon via according to an exemplary embodiment of the present application is shown, the method including:
Referring to fig. 3, a schematic cross-sectional view is shown before etching to form the first trench. As shown in fig. 3, a semiconductor device is formed on the front surface of a substrate 310, the semiconductor device includes a gate oxide 320 formed on the front surface of the substrate 310 and a gate electrode 330 formed on the gate oxide 320, a heavily doped region (not shown in fig. 3) is formed in the substrate 310 on both sides of the gate electrode 330, the substrate 310 and the semiconductor device are covered with a first interlayer dielectric layer 340, and the first interlayer dielectric layer 340 includes a low dielectric constant material (a material having a dielectric constant k less than 4, such as silicon oxide).
Optionally, a surrounding Shallow Trench Isolation (STI) structure 321 is formed in the substrate 310 on the peripheral side of the Active Area (AA) of the semiconductor device, and sidewalls 322 are formed on two sides of the gate 330.
Referring to fig. 4, a cross-sectional view of forming a first trench is shown. Illustratively, as shown in FIG. 4, step 202 includes, but is not limited to: covering a photoresist on the front surface by adopting a photoetching process, exposing the first target area, etching, removing the first interlayer dielectric layer 340 of the first target area, exposing the substrate 310 of the first target area, forming a first groove 401, and removing the photoresist.
Referring to fig. 5, a schematic cross-sectional view of forming a first via is shown. Illustratively, as shown in FIG. 5, step 203 includes, but is not limited to: and covering a photoresist on the front surface by adopting a photoetching process, exposing the second target area, etching to a preset depth in the substrate 310 of the second target area to form a first through hole 501, and removing the photoresist.
And step 204, filling metal in the first through hole to form the upper part of the silicon through hole.
Optionally, step 204 includes, but is not limited to: forming a first barrier layer on the front surface of the substrate, wherein the first barrier layer covers the surfaces of the first interlayer dielectric layer and the first through hole; forming a first metal layer on the surface of the first barrier layer; etching the front surface, and removing the first metal layer except the first through hole; forming a second metal layer, wherein the second metal layer covers the first barrier layer and the first metal layer; and carrying out planarization to remove the second metal layer except the first through hole.
Referring to fig. 6, a cross-sectional view of a first barrier layer formed on the front surface of the substrate and a first metal layer formed on the surface of the first barrier layer is shown. Illustratively, as shown in fig. 6, the first barrier layer 511 comprises titanium nitride, the first metal layer 512 comprises tungsten, the first barrier layer 511 is formed by depositing titanium nitride on the front surface of the substrate 310 by using a Chemical Vapor Deposition (CVD) process, the first barrier layer 511 covers the first interlayer dielectric layer 340, the first trench 401 and the surface of the first via 501, and the first metal layer 512 is formed by depositing tungsten on the surface of the first barrier layer 511 by using a CVD process. If the first metal layer 512 includes copper (Cu), an electroplating process may be used to plate copper on the first barrier layer 511 to form the first metal layer 512; if the first metal layer 512 includes aluminum (Al), the first metal layer 512 may be formed by depositing aluminum on the first barrier layer 511 using a Physical Vapor Deposition (PVD) process.
Referring to fig. 7, a schematic diagram of a cross-section of etching a first metal layer is shown. Illustratively, as shown in fig. 7, the first metal layer 512 in the other regions except for the first via hole may be removed by a general dry etching.
Referring to fig. 8, a cross-sectional view of forming the second metal layer is shown. Illustratively, as shown in fig. 8, a CVD process may be used to deposit tungsten to form the second metal layer 513. If the second metal layer 513 includes copper, an electroplating process may be used to plate copper to form the second metal layer 513; if the second metal layer 513 comprises aluminum, the second metal layer 513 may be formed by depositing aluminum using a PVD process.
Referring to fig. 9, a cross-sectional view of planarizing the second metal layer is shown. For example, as shown in fig. 9, the second metal layer 513 may be planarized by a Chemical Mechanical Planarization (CMP) process to remove the second metal layer 513 except for the first via 501.
Referring to fig. 15, a schematic cross-sectional view of the substrate before thinning is shown; referring to fig. 16, a schematic cross-sectional view of a substrate after thinning is shown. Illustratively, as shown in fig. 5, the substrate 310 has a thickness h1 before the substrate 310 is thinned, and a grinding process may be used to thin the substrate 310 from the back side thereof, as shown in fig. 6, and the substrate 310 has a thickness h2 after the substrate 310 is thinned.
And 206, etching from the back of the substrate to form a second through hole, wherein the second through hole is positioned below the first through hole, and the upper part of the through silicon via at the bottom of the second through hole is exposed.
Referring to fig. 17, a cross-sectional view of the etching to form the second via is shown. Illustratively, as shown in FIG. 17, step 206 includes, but is not limited to: and covering a photoresist on the back by adopting a photoetching process, exposing the third target area, etching until the upper part of the through silicon via in the third target area is exposed to form a second through hole 502, and removing the photoresist.
And step 207, filling metal in the second through hole to form the lower part of the through silicon via, wherein the upper part of the through silicon via and the lower part of the through silicon via form the through silicon via.
Optionally, step 207 includes, but is not limited to: forming a second barrier layer on the back surface of the substrate, wherein the second barrier layer covers the back surface of the substrate and the surface of the second through hole; forming a third metal layer on the surface of the second barrier layer; and flattening is carried out, and the third metal layer except the second through hole is removed.
Referring to fig. 18, a cross-sectional schematic view of forming the second barrier layer is shown. Illustratively, as shown in fig. 18, the second barrier layer 514 comprises titanium nitride, and a CVD process may be used to deposit titanium nitride on the backside of the substrate 310 to form the second barrier layer 514, wherein the second barrier layer 514 covers the backside of the substrate 310 and the surface of the second via 502.
Referring to fig. 19, a schematic cross-sectional view of a lower portion of a formed through-silicon-via is shown. Illustratively, as shown in fig. 19, the third metal layer 515 comprises tungsten, and the CVD process may be used to deposit tungsten on the surface of the second barrier layer 514 to form the third metal layer 515 (if the third metal layer 515 comprises copper, an electroplating process may be used to plate copper on the surface of the second barrier layer 514 to form the third metal layer 515; if the third metal layer 515 comprises aluminum, a PVD process may be used to deposit aluminum on the surface of the second barrier layer 514 to form the third metal layer 515); a CMP process may be used to remove the second barrier layer 514 and the third metal layer 515 in areas other than the second via.
In summary, in the embodiment of the present application, the first through hole is formed on the front surface of the substrate, the upper portion of the through silicon via is formed after the metal is filled, the second through hole is formed on the back surface of the substrate, the lower portion of the through silicon via is formed after the metal is filled, and the through silicon via penetrating through the substrate is formed by the upper portion and the lower portion, so that the problem of formation of the protruding defect on the back surface caused by forming the through hole penetrating through the front surface of the substrate by filling the metal to form the through silicon via is solved, and the yield of the product is improved.
After forming the upper portion of the through-silicon via, a metal interconnection structure for extracting the first heavily doped region, the second heavily doped region, the gate electrode, and the through-silicon via may be formed over the front surface of the substrate 310. An alternative method of forming a metal interconnect structure is provided below as an example.
Referring to fig. 20, a flowchart of a method for forming a metal interconnect structure according to an exemplary embodiment of the present application is shown, where the method may be performed after step 204 and before step 205 in the embodiment of fig. 2, and the method includes:
in step 2001, a first contact hole (CT) is formed in the first interlayer dielectric layer on the first heavily doped region, the gate electrode, and the second heavily doped region.
Referring to fig. 10, a schematic cross-sectional view of forming a first contact hole is shown. Illustratively, as shown in fig. 10, step 2001 includes, but is not limited to: and covering a photoresist on the front surface by adopting a photolithography process, exposing a fourth target region (a region corresponding to the first contact holes 341, 342, 343), etching to form a third through hole (a through hole corresponding to the first contact holes 341, 342, 343), removing the photoresist to form a fourth metal layer, removing the fourth metal layer in the other region except the fourth target region, and forming the first contact holes 341, 342, 343 by using the remaining fourth metal layer. The bottom end of the first contact hole 341 is connected to the first heavily doped region, the bottom end of the first contact hole 343 is connected to the gate 330, and the bottom end of the first contact hole 343 is connected to the second heavily doped region.
If the fourth metal layer comprises tungsten, depositing tungsten on the surface of the first interlayer dielectric layer 340 and the upper portion of the through-silicon via by using a CVD process to form the fourth metal layer; if the fourth metal layer comprises copper, a plating process may be used to plate copper on the surfaces of the first interlayer dielectric layer 340 and the upper portion of the through-silicon via to form the fourth metal layer; if the fourth metal layer comprises aluminum, a PVD process may be used to deposit aluminum on the surface of the first interlayer dielectric layer 340 and the upper portion of the through-silicon via to form the fourth metal layer.
In step 2002, a first metal line is formed over the top of the through-silicon-via and the first contact hole.
Referring to fig. 11, a cross-sectional schematic of the formation of the fifth metal layer is shown. For example, as shown in fig. 11, if the fifth metal layer 351 includes tungsten, the fifth metal layer 351 may be formed by depositing tungsten on the surfaces of the first interlayer dielectric layer 340, the first contact holes 341, 342, 343, and the upper portions of the through silicon vias using a CVD process; if the fifth metal layer 351 comprises copper, an electroplating process may be used to plate copper on the surfaces of the first interlayer dielectric layer 340, the first contact holes 341, 342, 343, and the upper portions of the through-silicon vias to form the fifth metal layer 351; if the fifth metal layer 351 includes aluminum, the fifth metal layer 351 may be formed by depositing aluminum on the surfaces of the first interlayer dielectric layer 340, the first contact holes 341, 342, 343, and the upper portion of the through-silicon via using a PVD process.
Referring to fig. 12, a cross-sectional view of forming a first metal line is shown. For example, as shown in fig. 12, a photoresist may be coated on the fifth metal layer 351 by a photolithography process to expose the regions except for the fifth target region, and etching is performed to remove the fifth metal layer 351 in the regions except for the fifth target region, and the remaining fifth metal layer forms the first metal connecting lines 3511 and 3512. The bottom end of the first metal wire 3511 is connected to the top end of the first contact hole, and the first metal wire 3512 is formed in the first trench and the bottom end thereof is connected to the upper portion of the through-silicon via.
Optionally, step 2003 includes, but is not limited to: forming a second interlayer dielectric layer on the first interlayer dielectric layer, wherein the second interlayer dielectric layer covers the first metal connecting line; and planarizing the second interlayer dielectric layer.
Referring to fig. 13, a schematic cross-sectional view of forming a second interlayer dielectric layer is shown; referring to fig. 14, a schematic cross-sectional view illustrating planarization of the second interlayer dielectric layer is shown. Illustratively, as shown in fig. 13, a second interlayer dielectric layer 350 may be formed by depositing a low dielectric constant material (e.g., silicon oxide) through a CVD process, and the deposited second interlayer dielectric layer 350 forms a recess 302 above the first trench 401 due to unevenness of the upper surface of the substrate 310; illustratively, as shown in fig. 14, the second interlayer dielectric layer 350 may be planarized by a CMP process.
In step 2004, a second contact hole is formed in the second interlayer dielectric layer over the first metal line.
Optionally, step 2004 includes, but is not limited to: and covering a photoresist on the second interlayer dielectric layer by adopting a photoetching process, exposing a sixth target area (an area corresponding to the second contact hole), etching, forming a fourth through hole (a through hole corresponding to the second contact hole), removing the photoresist, forming a sixth metal layer, flattening (for example, the CMP process can be adopted for flattening), removing the sixth metal layer in other areas except the seventh target area, and forming the second contact hole by using the remaining sixth metal layer.
In step 2005, a second metal line is formed over the second contact hole.
Optionally, step 2005 includes, but is not limited to: forming a seventh metal layer on the second interlayer dielectric layer; and removing the seventh metal layer in the other area except the seventh target area (the area corresponding to the second metal connecting line), wherein the rest of the seventh metal layer forms the second metal connecting line. The method for forming the second metal line can refer to the method for forming the first metal line in step 2002, which is not described herein again.
Optionally, step 2006 includes, but is not limited to: forming a third interlayer dielectric layer on the second interlayer dielectric layer, wherein the third interlayer dielectric layer covers the second metal connecting line; and planarizing the third interlayer dielectric layer. The method for forming the third interlayer dielectric layer can refer to the method for forming the first metal line in step 2003, which is not described herein.
In step 2007, a third contact hole is formed in the third interlayer dielectric layer and above the second metal line.
Optionally, step 2007 includes, but is not limited to: and covering a photoresist on the third interlayer dielectric layer by adopting a photoetching process, exposing an eighth target area (an area corresponding to the third contact hole), etching, forming a fifth through hole (a through hole corresponding to the third contact hole), removing the photoresist, forming a seventh metal layer, flattening (for example, the seventh metal layer can be flattened by adopting a CMP process), removing the seventh metal layer in the other areas except the eighth target area, and forming the third contact hole by using the residual seventh metal layer.
In step 2008, a third metal connection line is formed on the third contact hole.
Optionally, step 2008 includes, but is not limited to: forming an eighth metal layer on the third interlayer dielectric layer; and removing the eighth metal layer in the other area except the ninth target area (the area corresponding to the third metal connecting line), wherein the rest eighth metal layer forms the third metal connecting line. The method for forming the third metal line can refer to the method for forming the first metal line in step 2002, which is not described herein again.
It should be noted that, in the methods for forming the sixth metal layer, the seventh metal layer and the eighth metal layer in steps 2004 to 2008, reference may be made to the above methods for forming the first metal layer to the fifth metal layer, which are not described herein again.
In step 2009, a dielectric layer is formed on the third interlayer dielectric layer and around the third metal line.
Optionally, step 2009 includes, but is not limited to: and forming a dielectric layer on the third interlayer dielectric layer and the third metal connecting line, and opening a preset area at the top end of the third metal connecting line.
Referring to fig. 15, a cross-sectional view of a metal interconnect structure formed on the front side of a substrate is shown. Illustratively, as shown in fig. 15, second contact holes 3521 and 3522 are formed in the second interlayer dielectric 350, a bottom end of the second contact hole 3521 is connected to a top end of the first metal wire 3511, and a bottom end of the second contact hole 3522 is connected to a top end of the first metal wire 3512; a third interlayer dielectric layer 360 is formed on the second interlayer dielectric layer 350, second metal connecting lines 3611 and 3612 and third contact holes 3621 and 3622 are formed in the third interlayer dielectric layer 360, the bottom end of the third contact hole 3621 is connected with the top end of the second metal connecting line 3611, and the bottom end of the third contact hole 3622 is connected with the top end of the second metal connecting line 3612; a third metal wire 3711 is formed in the third contact hole 3621, a third metal wire 3712 is formed in the third contact hole 3622, a dielectric layer 372 is formed around the third interlayer dielectric layer 360 and the third metal wires 3711 and 3712, and the dielectric layer 372 forms a cylindrical structure around the third metal wires 3711 and 3712.
Illustratively, as shown in fig. 15, step 2009 includes, but is not limited to: depositing a dielectric layer on the third interlayer dielectric layer 360 and the third metal lines 3711 and 3712, covering a photoresist on the dielectric layer by a photolithography process to expose the dielectric layer in a predetermined region above the third metal lines 3711 and 3712, and etching to expose a predetermined region at the top ends of the third metal lines 3711 and 3712.
Referring to fig. 19, there is shown a schematic cross-sectional view of a device including a through-silicon-via provided by an exemplary embodiment of the present application, the device being fabricated by any one of the method embodiments described above, the device including:
a substrate 310 having a semiconductor device and a through-silicon via formed on a front surface thereof, the through-silicon via including an upper portion and a lower portion, a top end of the upper portion having a width greater than a width of a bottom end thereof, a top end of the lower portion having a width greater than a width of a bottom end thereof, the upper portion being located on the front surface of the substrate 310, a top end of the lower portion being located on a back surface of the substrate 310, and a bottom end of the upper portion being connected to the bottom end of the lower portion.
Optionally, the upper portion of the tsv includes a barrier layer (first barrier layer 511) and a metal layer (first metal layer 512 and second metal layer 513) in sequence from outside to inside, and the lower portion includes a barrier layer (second barrier layer 514) and a metal layer (third metal layer 515) in sequence from outside to inside. Wherein the barrier layer comprises titanium nitride and the metal layer comprises tungsten.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (10)
1. A method for forming a Through Silicon Via (TSV) comprises the steps of:
providing a substrate, wherein a semiconductor device is formed on the front surface of the substrate, and a first interlayer dielectric layer covers the substrate and the semiconductor device;
etching from the front side, and removing the first interlayer dielectric layer of the first target area to form a first groove;
etching from the front surface, and forming a first through hole in the substrate at the bottom of the first groove;
filling metal in the first through hole to form the upper part of the silicon through hole;
thinning the substrate from the back side of the substrate;
etching from the back of the substrate to form a second through hole, wherein the second through hole is positioned below the first through hole, and the upper part of the through silicon hole at the bottom of the second through hole is exposed;
and filling metal in the second through hole to form the lower part of the through silicon via, wherein the upper part of the through silicon via and the lower part of the through silicon via form the through silicon via.
2. The method of claim 1, wherein the filling of the first via with metal comprises:
forming a first barrier layer on the front surface, wherein the first barrier layer covers the surfaces of the first interlayer dielectric layer, the first trench and the first through hole;
forming a first metal layer on the surface of the first barrier layer;
etching is carried out from the front surface, and the first metal layer except the first through hole is removed;
forming a second metal layer covering the first barrier layer and the first metal layer;
and carrying out planarization to remove the second metal layer except the first through hole.
3. The method of claim 2, wherein the filling the metal in the second via comprises:
forming a second barrier layer on the back surface, wherein the second barrier layer covers the back surface of the substrate and the surface of the second through hole;
forming a third metal layer on the surface of the second barrier layer;
and flattening, and removing the third metal layer except the second through hole.
4. The method of claim 3, wherein the first barrier layer and the second barrier layer comprise titanium nitride.
5. The method of claim 4, wherein the first metal layer, the second metal layer, and the third metal layer comprise tungsten.
6. The method of any of claims 1 to 5, wherein the semiconductor device comprises a gate oxide formed on the front surface, and a gate formed on the gate oxide, wherein a first heavily doped region and a second heavily doped region are formed in the substrate on both sides of the gate.
7. The method of claim 6, wherein after the forming the upper portion of the through-silicon-via and before the forming the lower portion of the through-silicon-via, further comprising:
and forming a metal interconnection structure above the front surface, wherein the metal interconnection structure is used for leading out the first heavily doped region, the second heavily doped region, the grid and the through silicon via.
8. A device including a through silicon via, comprising:
the semiconductor device comprises a substrate, wherein a semiconductor device and a through silicon via are formed on the front surface of the substrate;
the through silicon via comprises an upper part and a lower part, the width of the top end of the upper part is larger than that of the bottom end of the upper part, the width of the top end of the lower part is larger than that of the bottom end of the lower part, the top end of the upper part is positioned on the front surface of the substrate, the top end of the lower part is positioned on the back surface of the substrate, and the bottom end of the upper part is connected with the bottom end of the lower part.
9. The device of claim 8, wherein the upper portion comprises a barrier layer and a metal layer in an outside-in order, and the lower portion comprises a barrier layer and a metal layer in an outside-in order.
10. The device of claim 9, wherein the barrier layer comprises titanium nitride and the metal layer comprises tungsten.
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