CN110783265A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN110783265A CN110783265A CN201911070168.9A CN201911070168A CN110783265A CN 110783265 A CN110783265 A CN 110783265A CN 201911070168 A CN201911070168 A CN 201911070168A CN 110783265 A CN110783265 A CN 110783265A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
Abstract
The application provides a semiconductor device and a manufacturing method thereof, the manufacturing method of the semiconductor device comprises the steps that an isolation structure is arranged in a first semiconductor needing to be subjected to wafer back thinning, the isolation structure is a third insulating layer and is at least positioned above a first conducting layer and a second conducting layer, and one surface of the isolation structure is flush with the surface, facing the first insulating layer, of a first substrate of the first semiconductor, namely, the third insulating layer is filled in a region, needing to be etched, of a TSV through hole through deep trench isolation, the deep trench isolation is adopted to replace shallow trench isolation, on the basis of enhancing the isolation effect between devices, on one hand, the use of a high dielectric constant layer can be omitted, the large stress caused by the high dielectric constant layer is avoided, and the generated defects are avoided, so that the technical process of the TSV is simplified; on the other hand, the silicon through hole can be directly manufactured in the deep groove isolation structure, so that a plurality of process steps can be omitted, and the technical process of the silicon through hole is simpler.
Description
Technical Field
The invention relates to the technical field of semiconductor device manufacturing, in particular to a semiconductor device and a manufacturing method thereof.
Background
Through Silicon Via (TSV) technology is an advanced process for realizing metal interconnection between stacked upper and lower wafers, and is currently considered to be one of the most advanced technologies in the semiconductor industry Through three-dimensional (3D) vertical integration of TSV copper interconnection.
TSVs are an important development technology that utilize short vertical electrical connections or "vias" through the silicon wafer to establish electrical connections from the active side to the back side of the chip. The TSV provides the shortest interconnection path, and a path is created for final 3D integration.
However, in the 3D IC manufacturing process in the prior art, after the back surface of the wafer is thinned, a high dielectric constant layer needs to be deposited to ensure that the device on the front surface of the wafer can work normally, but the high dielectric constant layer usually has a large stress and may cause some defects, and meanwhile, the process of the conventional through silicon via technology is complicated.
Disclosure of Invention
In view of the above, the present invention provides a semiconductor device and a method for manufacturing the same, so as to solve the problems in the prior art that the through silicon via technology is complicated in process and defects are generated due to large stress caused by a high dielectric constant layer.
In order to achieve the purpose, the invention provides the following technical scheme:
a semiconductor device manufacturing method comprises the following steps:
providing a first semiconductor and a second semiconductor, wherein the first semiconductor comprises a first substrate, a first insulating layer positioned on the first substrate, and a first conducting layer positioned in the first insulating layer; the second semiconductor comprises a second substrate, a second insulating layer located on the second substrate and a second conducting layer located in the second insulating layer; the first semiconductor further comprises a plurality of isolation structures located in the first substrate, the isolation structures are third insulating layers, and the plurality of isolation structures at least comprise first isolation structures located above the first conducting layer and second isolation structures located above the second conducting layer; one surface of the isolation structures is flush with the surface of the first substrate facing the first insulating layer;
bonding the first and second semiconductors together, the first insulating layer interfacing with the second insulating layer;
thinning the first substrate until the isolation structure penetrates through the thinned first substrate to form a thinned first isolation structure and a thinned second isolation structure;
forming a first opening in the thinned first isolation structure region, wherein the first opening exposes the first conductive layer, and a third insulating layer is reserved between the side wall of the first opening in the thinned first substrate and the side wall of the thinned first isolation structure;
forming a second opening in the thinned second isolation structure region, wherein the second opening exposes the second conductive layer, and a third insulating layer is reserved between the side wall of the second opening in the thinned first substrate and the side wall of the thinned second isolation structure;
and filling a conductive material into the first opening and the second opening.
Preferably, after thinning the first substrate, before forming the first opening and the second opening, the method further includes:
and depositing a protective layer on the thinned first semiconductor surface.
Preferably, forming a first opening in the thinned first isolation structure region specifically includes:
forming a first sub-opening in the thinned first isolation structure region through a lithography and etching process, and reserving a part of the first insulating layer between the bottom of the first sub-opening and the first conductive layer;
forming a second opening in the thinned second isolation structure region, and specifically comprising:
forming a second sub-opening in the thinned second isolation structure region through a lithography and etching process, wherein a part of the second insulating layer is reserved between the bottom of the second sub-opening and the second conductive layer;
and removing the insulating layer at the bottoms of the first sub-opening and the second sub-opening to form the first opening and the second opening.
Preferably, the providing the first semiconductor in the providing the first semiconductor and the second semiconductor comprises:
providing a first substrate;
forming photoresist on the first substrate to cover the first substrate outside the isolation structure to be formed;
etching the first substrate to form a groove opening;
depositing an insulating layer, filling the groove opening and covering the first substrate, wherein the third insulating layer is filled in the groove opening, and the first insulating layer is covered on the first substrate;
forming a first conductive layer on the first insulating layer;
and forming an insulating material on the first conductive layer to cover the first conductive layer.
Preferably, before forming the first opening and the second opening, the method further includes:
forming a third opening in the protective layer and over the first and second conductive layers.
Preferably, the filling of the conductive material into the first opening and the second opening further comprises filling the conductive material into the third opening;
and planarizing the conductive material until the conductive material in the third opening is flush with the surface of the protective layer, which faces away from the second semiconductor.
Preferably, the method further comprises the following steps:
planarizing the conductive material until the conductive material is flush with the surface of the first substrate facing away from the second substrate;
depositing a fourth insulating layer on the planarized surface of the conductive material;
and forming an aluminum pad on the surface of the semiconductor device through a rewiring layer process, wherein the aluminum pad is electrically connected with the conductive materials in the first opening and the second opening.
The present invention also provides a semiconductor device comprising:
a first semiconductor and a second semiconductor bonded to each other, the first semiconductor including a first substrate, a first insulating layer over the first substrate, a first conductive layer within the first insulating layer; the second semiconductor comprises a second substrate, a second insulating layer located on the second substrate and a second conducting layer located in the second insulating layer, and the first insulating layer and the second insulating layer are bonded to form a bonding interface;
a plurality of isolation structures penetrating through the first substrate, the plurality of isolation structures at least including a first isolation structure located above the first conductive layer and a second isolation structure located above the second conductive layer, the isolation structures being third insulating layers;
the first conductive structure penetrates through a first insulating layer between the first conductive layer and the first isolation structure and is electrically connected with the first conductive layer; the second conductive structure penetrates through the first insulating layer, the second insulating layer and the second isolation structure between the second conductive layer and the second isolation structure and is electrically connected with the second conductive layer;
a third insulating layer is reserved between the side wall of the first isolation structure and the side wall of the first conductive structure in the first substrate;
and a third insulating layer is reserved between the side wall of the second isolation structure and the side wall of the second conductive structure.
Preferably, the display device further comprises a protective layer covering the first substrate, the plurality of isolation structures, and the first conductive structure and the second conductive structure, and a third conductive structure located in the protective layer and electrically connecting the first conductive structure and the second conductive structure.
Preferably, a fourth insulating layer covering the first substrate, the plurality of isolation structures, and the first and second conductive structures is further included.
Preferably, the conductive structure further comprises an aluminum pad, the aluminum pad is located on a surface of the fourth insulating layer, which faces away from the first substrate, and the first conductive structure and the second conductive structure are electrically connected through the aluminum pad.
According to the technical scheme, the method for manufacturing the semiconductor device, provided by the invention, is characterized in that the isolation structure is arranged in the first semiconductor needing to be subjected to wafer back thinning, the isolation structure is the third insulating layer, the isolation structure is at least positioned above the first conducting layer and the second conducting layer, one surface of the isolation structure is flush with the surface, facing the first insulating layer, of the first substrate of the first semiconductor, namely the third insulating layer is filled in the area, needing to be etched, of the TSV through hole through deep trench isolation, the deep trench isolation is adopted to replace the shallow trench isolation in the prior art, on the basis of enhancing the isolation effect among the devices, on one hand, the deep trench isolation can isolate each device, so that unnecessary leakage current generated between adjacent devices due to related processes such as wafer back thinning and the like is prevented, and even if the wafer back is thinned, the accumulation of charges can exist, the isolation relation among the devices can, therefore, the use of a high dielectric constant layer can be omitted, the defects caused by larger stress brought by the high dielectric constant layer can be avoided, and the through silicon via technology can be simplified; on the other hand, in the process between the silicon through holes, the silicon through holes can be directly manufactured at the part isolated by the deep grooves, and compared with the technical process of firstly forming holes on the silicon substrate, then depositing the protective layer at the positions of the holes to perform side wall protection, opening the bottom of the protective layer and filling metal in the prior art, the etching technical process of depositing the protective layer to perform side wall protection and opening the bottom of the protective layer is omitted, the technical process of the silicon through hole technology can be simplified, and the technical process of the silicon through hole technology is simpler.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic cross-sectional structure of a semiconductor device provided in the prior art;
fig. 2-8 are schematic cross-sectional views illustrating a semiconductor device manufacturing process provided in the prior art;
fig. 9 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of a first semiconductor and a second semiconductor according to an embodiment of the present invention;
fig. 11-13 are schematic views of a first semiconductor formation process according to an embodiment of the present invention;
fig. 14-19 are schematic cross-sectional views illustrating a semiconductor device manufacturing process according to an embodiment of the invention;
fig. 20 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention;
fig. 21 is a schematic cross-sectional view of another semiconductor device manufacturing process according to an embodiment of the invention;
fig. 22 is a schematic cross-sectional structure diagram of another semiconductor device according to an embodiment of the present invention.
Detailed Description
As described in the background section, the through-silicon-via technology in the prior art has the problems of complicated process and defects due to the large stress caused by the high-k layer.
The inventors found that the reason for the above phenomenon is:
referring to fig. 1, fig. 1 is a schematic structural diagram of a semiconductor device formed by a through-silicon-via process of the prior art; the semiconductor device formed by the through silicon via process includes at least two wafers stacked in layers, and it should be noted that for convenience of description, only two wafers stacked in layers are taken as an example in the embodiment of the present invention for description.
As shown in fig. 1, the through silicon via technology implements metal interconnection between the first wafer 01 and the second wafer 02 after stack bonding. The first wafer 01 includes a first silicon layer 011, a first insulating layer 012, a first metal layer M01 located in the first insulating layer 012, a shallow trench isolation 013, and a high-k layer 014; the second wafer 02 includes a second silicon layer 021, a second insulating layer 022, a second metal layer M02 in the second insulating layer 022; the first insulating layer 012 and the second insulating layer 022 are used to prevent the Cu metal in the first metal layer M01 and the second metal layer M02 from diffusing, which affects the electrical performance of other areas of the semiconductor device. The front surface of the first wafer 01 and the front surface of the second wafer 02 are bonded together by a bonding process, such as a dotted line portion in fig. 1, which is a bonding surface where the two wafers are bonded together. The first metal layer M01 of the first wafer 01 and the second metal layer M02 of the second wafer 02 are electrically interconnected through TSVs.
The existing manufacturing method specifically comprises the following steps:
providing a first wafer 01 and a second wafer 02, wherein shallow trench isolations 013 have been provided in the first silicon layer 011 of the first wafer 01 for isolating a plurality of adjacent devices; please refer to fig. 2;
bonding the first wafer 01 and the second wafer 02 together;
carrying out a thinning process on the back surface of the first wafer 01; please refer to fig. 3;
manufacturing a high-dielectric-constant layer 014 on the back surface of the thinned first wafer 01 for protection; then forming an insulating layer 015 on the surface of the high-dielectric-constant layer, which is far away from the first wafer; please refer to fig. 4;
etching the shallow through hole SV and the deep through hole DV in sequence to form a shallow through hole SV and a deep through hole DV, wherein the etching of the shallow through hole SV is stopped above the first metal layer M01 in the first wafer 01, namely the shallow through hole SV does not expose the first metal layer M01; the etching of the deep via DV is stopped above the second metal layer M02 in the second wafer 02, i.e., the deep via DV does not expose the second metal layer M02; please refer to fig. 5;
then depositing an insulating layer in the shallow via SV and the deep via DV to protect the sidewall 016 of the first silicon layer; please refer to fig. 6;
etching and opening the residual insulating layer above the metal layer to expose the first metal layer M01 and the second metal layer M02; please refer to fig. 7;
and finally, filling metal Cu017, removing redundant metal Cu through a CMP (chemical mechanical polishing) process, and realizing the electrical connection between the upper wafer and the lower wafer through TSV. Please refer to fig. 8;
as can be seen from the above manufacturing method, after the back surface of the first wafer is thinned, charge accumulation is formed on the thinned surface of the first wafer; if the insulating layer is directly formed, the charges in the insulating layer interfere with the charges on the thinned surface of the wafer due to charge accumulation, and the charges move laterally, thereby affecting adjacent semiconductor devices. For this reason, in the prior art, a high dielectric constant layer must be formed to ensure that devices on the front surface of the wafer can work properly. The presence of the high dielectric constant layer, however, may create a large stress that may cause defects within the semiconductor device.
Moreover, since the first silicon layer and the filled metal Cu cannot be in direct contact, an insulating layer must be formed to protect the sidewalls of the shallow through hole and the deep through hole, which results in that after the through hole is formed by etching, the insulating layer needs to be deposited again, and then an etching process is required to open the bottom of the insulating layer to expose the metal layer, thereby resulting in a complicated TSV process.
Based on this, the invention provides a method for manufacturing a semiconductor device, which comprises the following steps:
providing a first semiconductor and a second semiconductor, wherein the first semiconductor comprises a first substrate, a first insulating layer positioned on the first substrate, and a first conducting layer positioned in the first insulating layer; the second semiconductor comprises a second substrate, a second insulating layer located on the second substrate and a second conducting layer located in the second insulating layer; the first semiconductor further comprises a plurality of isolation structures located in the first substrate, the isolation structures are third insulating layers, and the plurality of isolation structures at least comprise first isolation structures located above the first conducting layer and second isolation structures located above the second conducting layer; one surface of the isolation structures is flush with the surface of the first substrate facing the first insulating layer;
bonding the first and second semiconductors together, the first insulating layer interfacing with the second insulating layer;
thinning the first substrate until the isolation structure penetrates through the thinned first substrate, the thinned first isolation structure and the thinned second isolation structure;
forming a first opening in the thinned first isolation structure region, wherein the first opening exposes the first conductive layer, and a third insulating layer is reserved between the side wall of the first opening in the thinned first substrate and the side wall of the thinned first isolation structure;
forming a second opening in the thinned second isolation structure region, wherein the second opening exposes the second conductive layer, and a third insulating layer is reserved between the side wall of the second opening in the thinned first substrate and the side wall of the thinned second isolation structure;
and filling a conductive material into the first opening and the second opening.
The invention provides a method for manufacturing a semiconductor device, which is characterized in that an isolation structure is arranged in a first semiconductor needing to be subjected to wafer back thinning, the isolation structure is a third insulating layer, the isolation structure is at least positioned above a first conducting layer and a second conducting layer, one surface of the isolation structure is flush with the surface, facing the first insulating layer, of a first substrate of the first semiconductor, namely, a region needing to be etched of a TSV through hole is filled with the third insulating layer through deep trench isolation, the deep trench isolation is adopted to replace shallow trench isolation in the prior art, on the basis of enhancing the isolation effect among devices, on one hand, each device can be isolated due to the deep trench isolation, unnecessary leakage current generated between adjacent devices due to related processes such as wafer back thinning and the like is prevented, and even if the wafer back is thinned, the accumulation of electric charges can not affect the isolation relation among the devices, therefore, the use of a high dielectric constant layer can be omitted, the defects caused by larger stress brought by the high dielectric constant layer can be avoided, and the through silicon via technology can be simplified; on the other hand, in the process between the silicon through holes, the silicon through holes can be directly manufactured at the part isolated by the deep grooves, and compared with the technical process of firstly forming holes on the silicon substrate, then depositing the protective layer at the positions of the holes to perform side wall protection, opening the bottom of the protective layer and filling metal in the prior art, the etching technical process of depositing the protective layer to perform side wall protection and opening the bottom of the protective layer is omitted, the technical process of the silicon through hole technology can be simplified, and the technical process of the silicon through hole technology is simpler.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 9, fig. 9 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, where the method for manufacturing a semiconductor device includes:
s101: providing a first semiconductor and a second semiconductor;
referring to fig. 10, in the embodiment of the invention, the first semiconductor 1 includes a first substrate 11, a first insulating layer 12 located on the first substrate 11, and a first conductive layer M1 located in the first insulating layer 12; the second semiconductor 2 comprises a second substrate 21, a second insulating layer 22 positioned on the second substrate 21, and a second conductive layer M2 positioned in the second insulating layer 22; the first semiconductor further comprises a plurality of isolation structures 13 located within the first silicon substrate, the isolation structures being third insulating layers. The isolation structure can also be referred to as deep trench isolation 13 in the present invention; the plurality of isolation structures comprises at least a first isolation structure 131 located above the first conductive layer and a second isolation structure 132 located above the second conductive layer, and one surface of the plurality of isolation structures 13 is flush with a surface of the first substrate 11 facing the first insulating layer 12.
In the embodiment of the present invention, the isolation structures 13 include a region to be formed with a through-silicon via, and a projection of the region to be formed with the through-silicon via on the first substrate 11 covers a projection of the through-silicon via to be formed on the first substrate. That is, after the through-silicon via is formed, the through-silicon via is located under the isolation structure, and all cross-sectional areas of the through-silicon via along a direction perpendicular to an axis of the through-silicon via are smaller than the area of the isolation structure on the plane where the first substrate is located, so that after the through-silicon via is formed, the through-silicon via is located inside the isolation structure, and therefore the side wall of the through-silicon via is a third insulating layer.
It should be noted that, because the first semiconductor 1 is a wafer whose wafer back is thinned subsequently, one surface of the isolation structure 13 is flush with the surface of the first substrate 11 facing the first insulating layer 12, and the other surface is located in the first silicon substrate, that is, the bottom of the isolation structure is located in the first silicon substrate, and after thinning, the isolation structure forms a structure penetrating through the thinned semiconductor.
In this embodiment, specific materials of the first insulating layer 12 and the second insulating layer 22 are not limited, and alternatively, the first insulating layer and the second insulating layer may be made of the same material and may include nitride or oxide. In the manufacturing process, different materials can be adopted to form the first insulating layer and the second insulating layer in different layers. In addition, the material of the third insulating layer is not limited in the embodiments of the present invention, and may be the same as or different from the material of the first insulating layer and the second insulating layer, and the third insulating layer may be silicon oxide or silicon nitride.
In this embodiment, specific materials of the first conductive layer, the second conductive layer, and the first substrate and the second substrate are not limited, and optionally, the materials of the first conductive layer and the second conductive layer are the same and are both metal layers, such as copper. The first substrate and the second substrate may be selected to be silicon substrates.
In this embodiment, the regions to be formed with the through silicon vias are, as shown in 131 and 132 in fig. 10, where the regions to be formed with the through silicon vias are disposed corresponding to the conductive layers of the first semiconductor and the second semiconductor that need to be electrically interconnected, as shown in fig. 10, the isolation structure 131 is disposed corresponding to the first metal layer M1, and the isolation structure 132 is disposed corresponding to the second metal layer M2. The projection of the isolation structure of the through silicon via to be formed on the first silicon substrate covers the projection of the subsequently formed through silicon via on the first silicon substrate, so that the through silicon via is ensured to be completely surrounded by the filling insulating layer in the deep trench isolation after the through silicon via is formed subsequently, namely the through silicon via is wrapped by the third insulating layer, and the through silicon via is not communicated with the first silicon substrate, so that the filled conductive material is not contacted with the first silicon substrate when the conductive material is filled in the through silicon via subsequently, the isolation structure can insulate the filling metal in the through silicon via from the first silicon substrate, the deposition of a side wall protective layer in the prior art is replaced, and the reliability of a semiconductor device is ensured. In the front end design process of the first wafer, the through-silicon-via region to be formed is well designed according to the position of a metal layer which needs to be interconnected with the through-silicon-via, which is not described in detail in the embodiment of the present invention.
Referring to fig. 11-13, the process of providing the first semiconductor in the present embodiment includes:
providing a first substrate;
referring to fig. 11, a photoresist 110 is formed on the first substrate 11 to cover the first substrate outside the region where the isolation structure is to be formed.
Referring to fig. 12, the first silicon substrate 11 is etched to form a trench opening 111;
referring to fig. 13, an insulating layer 112 is deposited to fill the trench opening 111 and cover the first substrate 11, wherein the third insulating layer 13 is filled in the trench opening, and the first insulating layer 12 is covered on the first substrate;
forming a first conductive layer M1 on the first insulating layer 12;
an insulating layer 113 is formed on the first conductive layer M1, covering the first conductive layer M1.
Although the insulating layer 112 is shown with different filling in fig. 13, the insulating layer may be formed with the same material or with different insulating materials in the actual manufacturing process. Similarly, the insulating layer 113 in fig. 13 is shown with different filling, which means that different insulating materials can be used to form different insulating layers, such as an oxide insulating layer and a nitride insulating layer, which are not described in detail in the embodiment of the present invention. In this embodiment, although the insulating layers 112 and 113 are formed in multiple steps in the forming process, the insulating layers on the first substrate are the first insulating layer 12, the insulating layer in the first substrate is referred to as a third insulating layer 13, and the third insulating layer 13 fills the trench opening 111 to form an isolation structure.
S102: bonding the first and second semiconductors together, the first insulating layer interfacing with the second insulating layer;
referring to fig. 14, the insulating layers of the first semiconductor 1 and the second semiconductor 2 are brought into contact with each other and bonded together by a bonding technique to form a bonding surface, as shown by the dotted line in fig. 14.
S103: thinning the first substrate until the isolation structure penetrates through the thinned first substrate to form a thinned first isolation structure and a thinned second isolation structure;
referring to fig. 15, in the embodiment of the invention, the back surface of the first semiconductor is thinned, wherein the back surface of the first semiconductor is a surface where the substrate is located, and the front surface is a surface where the insulating layer is located. As shown in fig. 15, the first substrate on the back side of the first semiconductor is thinned to at least the bottom of the isolation structure, so that the first substrate is completely insulated and isolated into a plurality of silicon substrates by the isolation structure, and the thinned isolation structure forms the thinned first isolation structure and the thinned second isolation structure.
After the back surface of the first semiconductor is thinned, in order to ensure that the thinned surface of the first semiconductor meets the use requirements of the semiconductor device, a protective layer may be deposited on the thinned surface of the first semiconductor to protect the thinned surface of the first semiconductor, as shown in fig. 16, which is protective layer 3.
S104: forming a first opening in the thinned first isolation structure region;
s105: forming a second opening in the thinned second isolation structure region;
in this embodiment, the first opening exposes the first conductive layer, and a third insulating layer is remained between a sidewall of the first opening in the thinned first substrate and a sidewall of the thinned first isolation structure; the second trompil exposes the second conducting layer, and is located in the first substrate after the attenuate the lateral wall of second trompil with all remain the third insulating layer between the lateral wall of the second isolation structure after the attenuate.
That is, the third insulating layer is reserved around the formed first opening and the second opening, so that the third insulating layer wraps the first opening and the second opening.
It should be noted that, in order to protect the first conductive layer M1 and the second conductive layer M2 during the etching process of the first opening and the second opening, the forming of the first opening in the thinned first isolation structure region and the forming of the second opening in the thinned second isolation structure region provided in the embodiment of the present invention specifically includes:
forming a first sub-opening in the thinned first isolation structure region through a lithography and etching process, and reserving a part of the first insulating layer between the bottom of the first sub-opening and the first conductive layer;
forming a second sub-opening in the thinned second isolation structure region through a lithography and etching process, wherein a part of the second insulating layer is reserved between the bottom of the second sub-opening and the second conductive layer;
and removing the insulating layer at the bottoms of the first sub-opening and the second sub-opening to form the first opening and the second opening.
It should be noted that, before forming the first opening and the second opening, a third opening may be further formed, and the order of forming the first opening, the second opening, and the third opening is not limited, and may be set according to specific process requirements, where the third opening is formed in the protection layer 3, is located above the first conductive layer and the second conductive layer, and simultaneously covers the first isolation structure and the second isolation structure, and is communicated with the first opening and the second opening that are formed subsequently, so as to form the structure shown in fig. 17. Referring to fig. 17, the protection layer 3 is etched to form a third opening 3 ', and then the bottoms of the first sub-opening SV ' and the second sub-opening DV ' are both stopped in the insulating layer, so that the insulating layer above the first conductive layer and the second conductive layer is retained, thereby preventing the conductive layer from being damaged due to over-etching during the etching process.
It should be noted that, in the etching process, a part of the surface of the first substrate is covered by the photoresist, and etching is performed, when only a part of the insulating layer remains, the photoresist may be removed first, then the insulating layer above the conductive layer and the protective layer on the surface of the first semiconductor are etched, and the bottom insulating layer of the first sub-opening and the bottom insulating layer of the second sub-opening are removed, so as to form a first opening SV and a second opening DV, as shown in fig. 18.
S106: filling a conductive material into the first opening and the second opening;
it should be noted that, when the first opening and the second opening are filled with the conductive material, and when the third opening is further included, the conductive material may be filled into the third opening at the same time, so that a third conductive structure is formed in the third opening and is simultaneously in contact with the conductive material in the first opening and the conductive material in the second opening to achieve electrical connection, as shown in fig. 19. The structure shown in fig. 20 is then obtained by planarization.
Referring to fig. 20, the conductive material 14 is filled in the first opening SV and the second opening DV, and it should be noted that in the embodiment, as shown in fig. 20, the first conductive layer of the first semiconductor and the second conductive layer of the second semiconductor are electrically interconnected at the same time when the conductive material is filled. In other embodiments of the present invention, only the first opening and the second opening may be filled without electrically connecting the first conductive layer and the second conductive layer, and the first conductive layer and the second conductive layer may be electrically interconnected by other processes.
As shown in fig. 21, the conductive material is filled only in the first opening and the second opening, and the conductive material in the first opening is not directly electrically connected to the conductive material in the second opening, but an aluminum pad is disposed outside the first opening, so that the first opening and the second opening are electrically connected to each other.
As shown in fig. 21, in order to form a structure after filling the conductive material, the following processes may further include:
planarizing the conductive material until the conductive material is flush with the surface of the first substrate facing away from the second substrate; this insulates the conductive material in the first opening from the conductive material in the second opening.
Referring to fig. 22, a fourth insulating layer 15 is deposited on the planarized surface of the conductive material;
an aluminum pad 16 is formed on the surface of the semiconductor device by a Redistribution Layer (RDL) process, and is electrically connected to the conductive material 141 in the first opening and the conductive material 142 in the second opening.
The planarization in this embodiment may employ a chemical mechanical polishing process to remove the excess conductive material.
According to the manufacturing method, the first semiconductor is provided with the isolation structure which is the deep trench isolation, the deep trench isolation comprises the region of the silicon through hole to be formed, the region of the silicon through hole to be formed is directly opened with the hole, and the projection of the opening on the first silicon substrate is smaller than the projection of the region of the silicon through hole to be formed on the first silicon substrate, so that the first opening and the second opening can be formed in the deep trench isolation, the insulating property of the deep trench isolation is adopted to replace the technology of depositing the opening side wall protection layer in the prior art, at least one etching process and a process of depositing the protection layer can be saved, and the manufacturing process of the semiconductor device is greatly simplified.
In addition, because the deep trench isolation already isolates the first silicon substrate into a plurality of silicon substrates, even if charge accumulation is generated on the thinned surface of the first semiconductor after the wafer is thinned, and then charges are generated and interfered with each other when an insulating layer is deposited, because the deep trench isolation already isolates a plurality of semiconductor devices, even if charge interference is generated, the charges do not move transversely, and the adjacent semiconductor devices are not interfered with each other, so that the use of a high-dielectric-constant layer is avoided, the deposition of the high-dielectric-constant layer can be saved, and the manufacturing process of the semiconductor devices is simplified. Meanwhile, the defects of the semiconductor device caused by larger stress brought by the high dielectric constant layer can be avoided due to the fact that the high dielectric constant layer is omitted.
Based on the same inventive concept, the embodiment of the invention also provides a semiconductor device, which is manufactured by adopting the manufacturing method of the semiconductor device in the embodiment;
referring to fig. 20 and 22, the semiconductor device includes:
a first semiconductor 1 and a second semiconductor 2 bonded to each other, the first semiconductor 1 including a first substrate 11, a first insulating layer 12 on the first substrate 11, a first conductive layer M1 in the first insulating layer 12; the second semiconductor 2 comprises a second substrate 21, a second insulating layer 22 positioned on the second substrate 21 and a second conducting layer M2 positioned in the second insulating layer 22, wherein the first insulating layer 12 and the second insulating layer 22 are bonded to form a bonding interface;
a plurality of isolation structures penetrating the first substrate 11, the plurality of isolation structures including at least a first isolation structure 131 located above the first conductive layer M1 and a second isolation structure 132 located above the second conductive layer M2, the isolation structures being third insulating layers;
a first conductive structure 141 and a second conductive structure 142 (both shown by reference numeral 14 in fig. 19), wherein the first conductive structure 141 penetrates through the first insulating layer between the first conductive layer M1 and the first isolation structure 131, and is electrically connected to the first conductive layer M1; the second conductive structure 142 penetrates through the first insulating layer 12, the second insulating layer 22 and the second isolation structure 132 between the second conductive layer M2 and the second isolation structure 132, and is electrically connected to the second conductive layer M2;
wherein, in the first substrate 11, a third insulating layer is remained between the sidewall of the first isolation structure 131 and the sidewall of the first conductive structure 141;
a third insulating layer remains between the sidewalls of the second isolation structure 132 and the sidewalls of the second conductive structure 142.
In this embodiment, in order to facilitate electrical interconnection, the first conductive layer, the second conductive layer and the conductive structure may be made of the same material, and are all metal, such as copper.
In order to protect the conductive structure, the semiconductor device in the embodiment of the present invention may further include a fourth insulating layer 15 covering the first silicon substrate, the isolation structure, and the conductive structure, and the fourth insulating layer protects the filled conductive structure.
In addition, referring to fig. 22, in order to connect the conductive structure inside the semiconductor device with an external circuit, the present embodiment further includes an aluminum pad 16, where the aluminum pad 16 is located on a surface of the fourth insulating layer 15 away from the first substrate 11 and electrically connected to the metal. Specifically, the aluminum pad 16 may be electrically connected to the first conductive layer and the second conductive layer by punching the fourth insulating layer 15, and may also be electrically connected by other methods, which is not described in this embodiment.
Compared with the semiconductor device formed by the manufacturing method in the prior art, the semiconductor device provided by the embodiment of the invention has the advantages that the use of the protective layer and the high-dielectric-constant layer on the side wall of the opening is reduced, so that the manufacturing cost of the semiconductor device can be saved, the manufacturing process can be simplified in the manufacturing process, and the through silicon via technology is simpler.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (11)
1. A method for manufacturing a semiconductor device, comprising:
providing a first semiconductor and a second semiconductor, wherein the first semiconductor comprises a first substrate, a first insulating layer positioned on the first substrate, and a first conducting layer positioned in the first insulating layer; the second semiconductor comprises a second substrate, a second insulating layer located on the second substrate and a second conducting layer located in the second insulating layer; the first semiconductor further comprises a plurality of isolation structures located in the first substrate, the isolation structures are third insulating layers, and the plurality of isolation structures at least comprise first isolation structures located above the first conducting layer and second isolation structures located above the second conducting layer; one surface of the isolation structures is flush with the surface of the first substrate facing the first insulating layer;
bonding the first and second semiconductors together, the first insulating layer interfacing with the second insulating layer;
thinning the first substrate until the isolation structure penetrates through the thinned first substrate to form a thinned first isolation structure and a thinned second isolation structure;
forming a first opening in the thinned first isolation structure region, wherein the first opening exposes the first conductive layer, and a third insulating layer is reserved between the side wall of the first opening in the thinned first substrate and the side wall of the thinned first isolation structure;
forming a second opening in the thinned second isolation structure region, wherein the second opening exposes the second conductive layer, and a third insulating layer is reserved between the side wall of the second opening in the thinned first substrate and the side wall of the thinned second isolation structure;
and filling a conductive material into the first opening and the second opening.
2. The method for manufacturing a semiconductor device according to claim 1, further comprising, after thinning the first substrate and before forming the first opening and the second opening:
and depositing a protective layer on the thinned first semiconductor surface.
3. The method for manufacturing a semiconductor device according to claim 1, wherein forming a first opening in the thinned first isolation structure region specifically comprises:
forming a first sub-opening in the thinned first isolation structure region through a lithography and etching process, and reserving a part of the first insulating layer between the bottom of the first sub-opening and the first conductive layer;
forming a second opening in the thinned second isolation structure region, and specifically comprising:
forming a second sub-opening in the thinned second isolation structure region through a lithography and etching process, wherein a part of the second insulating layer is reserved between the bottom of the second sub-opening and the second conductive layer;
and removing the insulating layer at the bottoms of the first sub-opening and the second sub-opening to form the first opening and the second opening.
4. The method of claim 1, wherein providing the first semiconductor in the first and second semiconductors comprises:
providing a first substrate;
forming photoresist on the first substrate to cover the first substrate outside the isolation structure to be formed;
etching the first substrate to form a groove opening;
depositing an insulating layer, filling the groove opening and covering the first substrate, wherein the third insulating layer is filled in the groove opening, and the first insulating layer is covered on the first substrate;
forming a first conductive layer on the first insulating layer;
and forming an insulating material on the first conductive layer to cover the first conductive layer.
5. The method of fabricating a semiconductor device according to claim 2, further comprising, before forming the first opening and the second opening:
forming a third opening in the protective layer and over the first and second conductive layers.
6. The method of manufacturing a semiconductor device according to claim 5, wherein the filling of the conductive material into the first opening and the second opening further comprises filling the conductive material into the third opening;
and planarizing the conductive material until the conductive material in the third opening is flush with the surface of the protective layer, which faces away from the second semiconductor.
7. The method for manufacturing a semiconductor device according to claim 1, further comprising:
planarizing the conductive material until the conductive material is flush with the surface of the first substrate facing away from the second substrate;
depositing a fourth insulating layer on the planarized surface of the conductive material;
and forming an aluminum pad on the surface of the semiconductor device through a rewiring layer process, wherein the aluminum pad is electrically connected with the conductive materials in the first opening and the second opening.
8. A semiconductor device, comprising:
a first semiconductor and a second semiconductor bonded to each other, the first semiconductor including a first substrate, a first insulating layer over the first substrate, a first conductive layer within the first insulating layer; the second semiconductor comprises a second substrate, a second insulating layer located on the second substrate and a second conducting layer located in the second insulating layer, and the first insulating layer and the second insulating layer are bonded to form a bonding interface;
a plurality of isolation structures penetrating through the first substrate, the plurality of isolation structures at least including a first isolation structure located above the first conductive layer and a second isolation structure located above the second conductive layer, the isolation structures being third insulating layers;
the first conductive structure penetrates through a first insulating layer between the first conductive layer and the first isolation structure and is electrically connected with the first conductive layer; the second conductive structure penetrates through the first insulating layer, the second insulating layer and the second isolation structure between the second conductive layer and the second isolation structure and is electrically connected with the second conductive layer;
a third insulating layer is reserved between the side wall of the first isolation structure and the side wall of the first conductive structure in the first substrate;
and a third insulating layer is reserved between the side wall of the second isolation structure and the side wall of the second conductive structure.
9. The semiconductor device according to claim 8, further comprising a protective layer covering the first substrate, the plurality of isolation structures, and the first and second conductive structures, and a third conductive structure in the protective layer and electrically connecting the first and second conductive structures.
10. The semiconductor device according to claim 8, further comprising a fourth insulating layer covering the first substrate, the plurality of isolation structures, and the first conductive structure and the second conductive structure.
11. The semiconductor device according to claim 10, further comprising an aluminum pad on a surface of the fourth insulating layer facing away from the first substrate, the first conductive structure and the second conductive structure being electrically connected by the aluminum pad.
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