CN113765519B - Low-power-consumption high-precision dynamic comparator calibration circuit - Google Patents

Low-power-consumption high-precision dynamic comparator calibration circuit Download PDF

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CN113765519B
CN113765519B CN202110861613.4A CN202110861613A CN113765519B CN 113765519 B CN113765519 B CN 113765519B CN 202110861613 A CN202110861613 A CN 202110861613A CN 113765519 B CN113765519 B CN 113765519B
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port
calibration
output
comparator
trigger
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CN113765519A (en
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石春琦
朱晓剑
张润曦
申家齐
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East China Normal University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Theoretical Computer Science (AREA)
  • Manipulation Of Pulses (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

The invention discloses a low-power consumption high-precision dynamic comparator calibration circuit, which is characterized in that the output of a comparator is continuously counted through a counter, an output code word is regulated by a DAC (digital-to-analog converter) to change the threshold voltage of a transistor so as to calibrate offset voltage, wherein the calibration circuit comprises a calibration polarity detection control circuit, and a calibration completion mark signal is generated after the polarity inversion of the output of the comparator is detected, and the calibration is ended. Compared with the traditional scheme of adding the capacitor to the comparator load, the invention has the advantages that the adjusting range is-25.5 mV, the calibration step length is only 150 mu V, the power consumption after the front stage calibration is finished is 18nW, the high-precision low-power consumption ADC has the characteristics of high precision, and the requirement of the high-precision ADC can be met.

Description

Low-power-consumption high-precision dynamic comparator calibration circuit
Technical Field
The invention belongs to the technical field of integrated circuit design, and relates to a low-power consumption high-precision dynamic comparator digital calibration circuit which can be applied to a high-speed high-precision analog-to-digital converter system.
Background
With the continuous development of 5G, higher requirements are put on the speed and the precision of the analog-to-digital converter, wherein the successive approximation type SAR ADC has low power consumption, medium precision and higher speed, but the offset of the comparator in the SAR ADC can deteriorate the effective bit number, so that the offset voltage of the comparator in the SAR ADC with high precision is necessary to calibrate.
The traditional calibration method is to eliminate the input offset voltage by connecting an output end with an alternating current coupling capacitor and storing and subtracting the charge corresponding to the input offset voltage. This approach is very slow, affecting the high speed operation of the ADC. In recent years, the method mainly comprises the steps of adding a unit capacitor with a small capacitance value to the output load of the comparator, and calibrating offset voltage by adding a capacitor calibration load, so that the power consumption of a circuit can be increased, and the design of a high-speed ADC is not facilitated.
Along with the continuous development of integrated circuit technology, the power supply voltage of the ADC is continuously reduced, and the quantization precision of the ADC is continuously improved, so that the full swing range of the ADC is reduced to about 1V, and the minimum resolvable amplitude of the 12Bit ADC is reduced to about 300 mu V, so that higher requirements are put forward on the offset voltage of a comparator in the ADC.
Disclosure of Invention
The invention aims to provide a pure digital low-power-consumption high-precision dynamic comparator calibration circuit for enabling a comparator to distinguish voltage differences of mu V level.
The specific technical scheme for realizing the aim of the invention is as follows:
the utility model provides a low-power consumption high accuracy dynamic comparator calibration circuit, the circuit includes calibration polarity detection control circuit, comparator clock switching circuit, first counter 1, second counter 2, first DAC1, second DAC2 and comparator, and the specific form is: the input end of the comparator clock switching circuit is respectively connected with an inner LOOP clock CLK_LOOP, a calibration clock CLK_CAL and a calibration enabling signal CAL_EN, and the output CLKC of the comparator clock switching circuit is connected with the clock control port of the comparator; the input end of the calibration polarity detection control circuit is respectively connected with the output ends VOP and VON of the comparator, the calibration clock CLK_CAL and the calibration reset signal CAL_RST, and the output end of the calibration polarity detection control circuit is a calibration completion mark signal CAL_FINISH; the output end VOP of the comparator, the calibration completion flag signal CAL_FINISH and the calibration reset signal CAL_RST are respectively connected with the input end of the first counter 1; the output end VON of the comparator, the calibration completion flag signal CAL_FINISH and the calibration reset signal CAL_RST are respectively connected with the input end of the second counter 2; the output data of the first counter 1 is connected to the input end of the first DAC1, and the output voltage VBN of the first DAC1 is connected to the calibration port of the comparator; the output data of the second counter 2 is connected to the input port of the second DAC2, and the output voltage VBP of the second DAC2 is connected to the comparator calibration port; wherein:
the calibration polarity detection control circuit is used for detecting the output polarity of the comparator in calibration, and generating a calibration completion flag signal CAL_FINISH once the polarities of the output VOP and the output VON of the comparator are opposite to the last period, and ending the calibration; the comparator clock switching circuit selects the inner LOOP clock clk_loop or the calibration clock clk_cal as the operation clock of the comparator by controlling the calibration enable signal cal_en.
The invention relates to a calibration polarity detection control circuit, which comprises the following specific forms: the CAL_FINISH port is connected with a first inverter INV1, AND the output of the first inverter is connected with a first input port of a first AND gate AND 1; the port clk_cal is connected to the second input port of the first AND gate AND 1; the output of the first AND gate AND1 is connected to the CLK port of the first flip-flop DFF1, the CLK port of the second flip-flop DFF2, the CLK port of the third flip-flop DFF3 AND the CLK port of the fourth flip-flop DFF 4; the port CAL_RST is connected with the Reset port of the first trigger DFF1, the Reset port of the second trigger DFF2, the Reset port of the third trigger DFF3, the Reset port of the fourth trigger DFF4 and the Reset port of the fifth trigger DFF 5; the port VOP is connected to the D end of the first trigger DFF1, and the Q end of the first trigger DFF1 is output as a port PQ1 and is connected to the D end of the second trigger DFF 2; the QN end output of the first trigger DFF1 is a port PQ1N; the Q end of the second trigger DFF2 is output as a port PQ2; the port VON is connected to the D end of the third trigger DFF3, the Q end output of the third trigger DFF3 is a port NQ1 and is connected to the D end of the fourth trigger DFF4, and the Q end output of the fourth trigger DFF4 is a port NQ2; port PQ2 is connected to the first input port of the second AND gate AND2, port PQ1N is connected to the second input port of the second AND gate AND2, AND port NQ1 is the third input port of the second AND gate AND 2; port NQ2 is connected to the first input port of the third AND gate AND3, port NQ1N is connected to the second input port of the third AND gate AND3, port PQ1 is connected to the third input port of the third AND gate AND 3; the output of the second AND gate AND2 is connected to the first input port of the first OR gate OR1, AND the output of the third AND gate AND3 is connected to the second input port of the first OR gate OR 1; the output of the first OR gate OR1 is connected to the CLK port of the fifth flip-flop DFF5, the D terminal of the fifth flip-flop DFF5 is connected to the power supply VDD, and the Q terminal of the fifth flip-flop DFF5 is output as the port cal_finish.
The invention has the advantages that:
1) The invention provides a novel comparator calibration polarity detection control circuit which has simple structure and low power consumption, can be realized through digital synthesis, and can be conveniently transplanted into different processes.
2) The whole comparator calibration circuit has the characteristics of low power consumption and high precision, only needs to be calibrated once by power-on reset, and the power consumption of the calibration circuit is only 18nW after the calibration is completed. The invention adopts the counter to control the DAC output voltages VBP and VBN so as to change the threshold voltage of the transistor, and can realize high-precision calibration by increasing the bit number of the counter and the DAC and reducing the adjustment step length of the threshold voltage.
Drawings
FIG. 1 is a circuit block diagram of the present invention;
FIG. 2 is a schematic diagram of a calibration polarity detection control circuit according to the present invention;
FIG. 3 is a timing diagram illustrating operation of the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and examples.
The invention relates to a low-power-consumption high-precision dynamic comparator calibration circuit which comprises a comparator, a calibration polarity detection control circuit, a comparator clock switching circuit, a first counter 1, a second counter 2, a first DAC1 and a second DAC2, wherein the first DAC1 is used for detecting the calibration polarity of the comparator; referring to fig. 1, the calibration process of the present invention:
the first step of calibration: the switches S1, S2, S3 are closed and the comparator inputs VIN, VIP are connected together with a common mode level vcm=600 mV.
And a second calibration step: and resetting the output ports VOP and VON of the comparator to a low level, setting the counter, and resetting the counter 1, wherein the calibration voltages VBP and VBN are connected with the lowest level. The flip-flops DFF1, DFF2, DFF3, DFF4 are reset, and the calibration complete flag signal cal_finish is output at a low level.
And a third step of calibration: after the reset is finished, CAL_EN is connected with high level, the clock of the comparator is switched into the calibration clock, the comparator enters the calibration mode, and the output signal of the comparator is necessarily 1 and 0 at the same time due to the offset voltage of the comparator. Assuming vop=1 and von=0, it can be inferred that there is an offset voltage at the VIP port. According to the comparison result of the comparator, the counter 1 controlling the calibration voltage VBN counts, and the counter 2 controlling the calibration voltage VBP does not count, and the counter 1 generates corresponding code words and sends the corresponding code words to the DAC1 to obtain corresponding analog voltages, namely the voltage VBN. As VBN increases, the threshold voltage of the connected VIN input transistor will decrease. Similarly, when VBN increases to a certain extent, the comparator outputs vop=0 and von=1, that is, the offset voltage is considered to be basically eliminated, the offset is far smaller than 1 LSB, and the offset correction purpose is achieved, at this time, the comparator calibration polarity detection circuit detects that the output polarity of the comparator is inverted, the calibration completion flag signal cal_finish will be turned from low level to high level, the counter is controlled to keep the output code word unchanged, and the clock received by the short detection circuit is turned off, so that the calibration is automatically ended.
Examples
Referring to fig. 1, the present invention includes a comparator, a calibration polarity detection control circuit, a comparator clock switching circuit, a counter 1, a counter 2, a DAC1 and a DAC2, wherein an adjustment range of a calibration voltage of the comparator is determined according to a process, and the calibration voltage adjusts a corresponding transistor threshold voltage conversion relationship. In this embodiment, the adjustment range of the bulk voltage is 0-425mV, the corresponding threshold voltage change is 0-25.5mV, the threshold voltage adjustment step length is set to 0.15mV, the corresponding bulk voltage adjustment step length is 2.5mV, the DAC needs to use 9 bits, because the adjustment range is 8 bits, the highest bit of the DAC is connected with GND, and the counter stops counting when the counter is set to 181, so as to prevent the output voltage of the DAC from exceeding the maximum value of the bulk voltage adjustment.
Referring to fig. 2, in order to schematically illustrate the comparator polarity detection control circuit, a calibration reset signal cal_rst is first required to generate a high level to reset the comparator, flip-flops DFF1, DFF2, DFF3, DFF4, DFF5, and a calibration completion flag signal cal_finish is low after reset, and the control detection circuit can accept the calibration clock of clk_cal. The comparator polarity detection control circuit consists of a part 2, wherein one part is an edge detection circuit of the output results VOP and VON of the comparator, and a D trigger triggered by a 2-level falling edge is adopted to latch temporary quantized results of the current moment and the last moment of the comparator; and the other part is a circuit for judging and generating a calibration completion mark signal according to the overturning state of the comparator. When the inversion of the output result of the comparator AND the last period result is detected, a high-level flag signal CAL_FINISH is generated AND the counter keeps the current value, AND meanwhile, the first AND gate AND1 outputs a low-level clock for closing the polarity detection control circuit, AND the calibration is completed.
Referring to fig. 3, in the operation timing chart of the present embodiment, the reset signal clk_rst outputs a high level pulse width to reset, wherein VOP, VON, PQ1, PQ2, NQ1, and the calibration complete flag signal cal_finish is reset to a low level and PQ1N is reset to a high level. Since the calibration complete flag signal cal_finish is low, the clk_cal clock input starts calibration, and since the comparator VIP has an offset voltage, the VOP output is high. Since the VOP output is high, PQ1 changes from low to high, PQ1N changes from high to low, and the calibration voltage VBN increases. During the second clk_cal clock cycle, the calibration voltage VBN continues to rise because the VOP output is high and the PQ2 output is high. In the sixth clk_cal clock period, VON outputs a high level and VOP outputs a low level, at this time, PQ1 changes from a high level to a low level, PQ1N changes from a low level to a high level, NQ1 changes from a low level to a high level, at this time, the calibration completion flag signal cal_finish changes from a low level to a high level, and the calibration is ended.
The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to the specific details of the above embodiments, and various equivalent changes can be made to the technical solutions of the present invention within the scope of the technical concept of the present invention, and these equivalent changes all fall within the scope of the present invention.

Claims (1)

1. The utility model provides a low-power consumption high accuracy dynamic comparator calibration circuit which characterized in that, the circuit includes calibration polarity detection control circuit, comparator clock switching circuit, first counter 1, second counter 2, first DAC1, second DAC2 and comparator, and the specific form is: the input end of the comparator clock switching circuit is respectively connected with an inner LOOP clock CLK_LOOP, a calibration clock CLK_CAL and a calibration enabling signal CAL_EN, and the output CLKC of the comparator clock switching circuit is connected with the clock control port of the comparator; the input end of the calibration polarity detection control circuit is respectively connected with the output ends VOP and VON of the comparator, the calibration clock CLK_CAL and the calibration reset signal CAL_RST, and the output end of the calibration polarity detection control circuit is a calibration completion mark signal CAL_FINISH; the output end VOP of the comparator, the calibration completion flag signal CAL_FINISH and the calibration reset signal CAL_RST are respectively connected with the input end of the first counter 1; the output end VON of the comparator, the calibration completion flag signal CAL_FINISH and the calibration reset signal CAL_RST are respectively connected with the input end of the second counter 2; the output data of the first counter 1 is connected to the input end of the first DAC1, and the output calibration voltage VBN of the first DAC1 is connected to the calibration port of the comparator; the output data of the second counter 2 is connected to the input port of the second DAC2, and the output calibration voltage VBP of the second DAC2 is connected to the comparator calibration port; wherein:
the calibration polarity detection control circuit is used for detecting the output polarity of the comparator in calibration, and generating a calibration completion flag signal CAL_FINISH once the polarities of the output VOP and the output VON of the comparator are opposite to the last period, and ending the calibration; the comparator clock switching circuit selects the inner LOOP clock clk_loop or the calibration clock clk_cal as the operation clock of the comparator by controlling the calibration enable signal cal_en;
the calibration polarity detection control circuit comprises the following specific forms: the CAL_FINISH port is connected with a first inverter INV1, AND the output of the first inverter is connected with a first input port of a first AND gate AND 1; the port clk_cal is connected to the second input port of the first AND gate AND 1; the output of the first AND gate AND1 is connected to the CLK port of the first flip-flop DFF1, the CLK port of the second flip-flop DFF2, the CLK port of the third flip-flop DFF3 AND the CLK port of the fourth flip-flop DFF 4; the port CAL_RST is connected with the Reset port of the first trigger DFF1, the Reset port of the second trigger DFF2, the Reset port of the third trigger DFF3, the Reset port of the fourth trigger DFF4 and the Reset port of the fifth trigger DFF 5; the port VOP is connected to the D end of the first trigger DFF1, and the Q end of the first trigger DFF1 is output as a port PQ1 and is connected to the D end of the second trigger DFF 2; the QN end output of the first trigger DFF1 is a port PQ1N; the Q end of the second trigger DFF2 is output as a port PQ2; the port VON is connected to the D end of the third trigger DFF3, the Q end output of the third trigger DFF3 is a port NQ1 and is connected to the D end of the fourth trigger DFF4, and the Q end output of the fourth trigger DFF4 is a port NQ2; port PQ2 is connected to the first input port of the second AND gate AND2, port PQ1N is connected to the second input port of the second AND gate AND2, AND port NQ1 is the third input port of the second AND gate AND 2; port NQ2 is connected to the first input port of the third AND gate AND3, port NQ1N is connected to the second input port of the third AND gate AND3, port PQ1 is connected to the third input port of the third AND gate AND 3; the output of the second AND gate AND2 is connected to the first input port of the first OR gate OR1, AND the output of the third AND gate AND3 is connected to the second input port of the first OR gate OR 1; the output of the first OR gate OR1 is connected to the CLK port of the fifth flip-flop DFF5, the D terminal of the fifth flip-flop DFF5 is connected to the power supply VDD, and the Q terminal of the fifth flip-flop DFF5 is output as the port cal_finish.
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