CN113411085A - Successive approximation type capacitance detection circuit - Google Patents
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Abstract
The invention discloses a successive approximation type capacitance detection circuit which comprises a step counter module, wherein an upper counter and a lower counter respectively receive a voltage to be detected and an inverted value thereof, and output four-digit numbers in a successive approximation manner to control a current switch array. And the current array is coupled with the four-bit output of the asynchronous counter and charges the boost resistor to output a voltage value after successive approximation. The comparator used by the circuit is insensitive to the process and the working temperature, so that the change of an overvoltage protection threshold value at different working temperatures or the influence of a process angle in the chip manufacturing process can be avoided, and the reliability of an overvoltage protection function is improved; the adoption of the open-loop comparator can enhance the overall operation speed and effectively improve the gain.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a successive approximation type capacitance detection circuit.
Background
With the development of computer technology, multimedia technology, signal processing technology and microelectronic technology, the popularity of IC chips is increasing, which has led to great changes in the requirements of technology, structure, performance and reliability of IC chips, and has developed towards high speed, low power consumption, small volume and on-chip integration.
In the aspect of analog design, the detection of the capacitance value is an important part, once the matching condition of the input capacitance is insufficient, a huge error can be caused to the whole function, and even the service life of the chip is influenced.
In a conventional capacitance detection circuit, an analog-to-digital converter ADC is mainly used, and a capacitance to be detected is converted into a physical quantity such as voltage, frequency or time through an afe (analog Front end) architecture, for example, a charge amplifier structure. Then, the capacitance variation at the input end is converted into a Digital signal to be output by an ADC (analog to Digital converter), mainly an SAR ADC (successive approximation analog to Digital converter), or a TDC architecture. The circuit is complex, not only needs to provide different reference voltages, but also needs complex time sequence signal control logic, and external environment interference (temperature change and humidity change) has high influence on parasitic capacitance, thereby resulting in low reliability.
Disclosure of Invention
In view of the above-mentioned deficiencies in the prior art, the present invention provides a successive approximation type capacitance detection circuit.
In order to achieve the purpose of the invention, the invention adopts the technical scheme that:
a successive approximation type capacitance detection circuit comprises a comparison selection module, a step counter module, a current array module and a sampling switch;
one input end of the comparison selection module is connected with a charging current source and is grounded through a capacitor to be tested, and the other input end of the comparison selection module is connected with the output end of the current array module;
the input end of the step counter module is connected to the output end of the comparison selection module;
the input end of the current array module is connected with the output end of the step counting module, and the output end of the current array module passes through the sampling switch and then is used as the output of the successive approximation type capacitance detection circuit;
the sampling switch is also grounded through a sampling capacitor.
The counter used by the output stage has the advantages of simple structure, high efficiency and high speed, and is quicker than that of adopting SAR ADC successive approximation voltage; the range of the capacitor to be tested is high, the mode setting is simple, and the required time sequence signal control logic is simple and efficient; the structure is simple and convenient to upgrade, and the whole test circuit can be remarkably improved no matter by improving the digit of a counter or improving the performance of a comparator; the integral comparison circuit is started only when the capacitor is charged, so that the integral comparison circuit is closed when the system is in an overvoltage state, and power consumption is reduced.
Further, the comparison selection module comprises a comparator, a counter D6, a NAND gate NAND1, a NAND2, a NAND3, a NAND4, a NAND5, and NOR gates NOR15 and NOR16, wherein input ends of the comparator are respectively connected with an output of the successive approximation type capacitance detection circuit and a charging current source, and an output end of the comparator is connected with a D end of the counter D6; a clock signal is input into a CLK terminal of the counter D6, a Q terminal is output to the step counter module through a NAND gate NAND1 and a NAND gate NAND2 in sequence, and is output to the step counter module through a NOR gate NOR15, a NAND gate NAND4 and a NAND gate NAND5 in sequence; the input ends of the NAND gates 3 are respectively connected with the reset signals of the step counter, and the output ends are connected with one input end of the NOR gate NOR16 and are respectively output to the other input ends of the NAND gates NAND2 and NAND gates NAND5 through the NOR gates NOR 16; the other input terminal of the NAND gate NAND1 is connected to a clock signal, and the other input terminal of the NOR gate NOR15 and the other input terminal of the NOR gate NOR16 are grounded.
The beneficial effects of the further scheme are as follows: the comparison selection module uses a simple D trigger to store the level, the opening of each counter is controlled by the output of the comparator and the self RESET signal, and a series of gate circuits are used to control the selection of the counter AB. The feedback structure is simple and fast, and transmission delay is effectively reduced.
Further, the comparator adopts a two-stage open-loop comparator.
The beneficial effects of the further scheme are as follows: the amplifier circuit formed by cascading two stages of amplifiers working in an open loop makes up for the defects of insufficient gain and bandwidth, and brings the advantages of small offset voltage, higher precision and higher speed for the whole comparator structure.
Further, the step counter module comprises a first step counter and a second step counter, the first step counter comprises rising edge flip-flops D1, D2, D3, D4 and D5, NOR gates NOR1, NOR2, NOR3, NOR4, NOR5, NOR6, NOR7, NOR8, NOR9, NOR10, NOR11, NOR12, NOR13 and NOR14, and exclusive-OR gates XOR1, XOR2, XOR3 and XOR4, wherein the D end and the Q non-end of the rising edge flip-flops D1, D2, D3, D4 and D5 are short-circuited to form an asynchronous counter; one input end of the NOR gate NOR1 is connected with the output end of the NAND gate NAND2 in the comparison selection module, the other input end is grounded, and the output end is connected with the CLK end of the rising edge flip-flop D1; the Q end of the rising edge trigger D1 is output to one input end of a NOR gate NOR2 and is output to the current array module through a NOR gate NOR13, a NOR14 and an XOR gate XOR1 in sequence; the output end of the NOR gate NOR2 is connected with the CLK end of a rising edge trigger D2; the Q end of the rising edge trigger D2 is output to one input end of a NOR gate NOR3 and is output to the current array module through a NOR gate NOR11, a NOR12 and an XOR gate XOR2 in sequence; the output end of the NOR gate NOR3 is connected with the CLK end of a rising edge trigger D3; the Q end of the rising edge trigger D3 is output to one input end of a NOR gate NOR4 and is output to the current array module through a NOR gate NOR9, a NOR10 and an XOR gate XOR3 in sequence; the output end of the NOR gate NOR4 is connected with the CLK end of a rising edge trigger D4; the Q end of the rising edge trigger D4 is output to one input end of a NOR gate NOR5 and is output to the current array module through a NOR gate NOR7, a NOR8 and an XOR gate XOR4 in sequence; the output end of the NOR gate NOR5 is connected with the CLK end of the rising edge flip-flop D5, the Q end of the rising edge flip-flop D5 is output to one input end of the NOR gate NOR6, the reset signal of the ladder counter of the NOR gate NOR6 is output to one input end of the NAND gate NAND3 and is output to the other input end of the exclusive-OR gates XOR1, XOR2, XOR3 and XOR 4; the other input terminals of the NOR gates NOR1 to NOR14 are grounded; the second step counter is identical in structure to the first step counter. The outputs of the exclusive or gates XOR1, XOR2, XOR3 and XOR4 output a four-bit binary code as the output of the first step counter.
The beneficial effects of the further scheme are as follows: the step counter structure adds limitation to each counting cycle in a state identification mode, so that the jump from counting to a limit value can be avoided, the jump of an output current value and an output voltage value is further avoided, and the generation of errors is greatly reduced.
Further, the current array module comprises a first current array, a second current array, a power supply ICC and a charging resistor Rc, wherein an input end of the first current array is connected to an output end of the first step counter, and an input end of the second current array is connected to an output end of the second step counter; the first current array module comprises current sources I1, I2, I3 and I4, current limiting diodes Dio1, Dio2, Dio3 and Dio4, switches SW1, SW2, SW3 and SW 4; the second current array module comprises current sources I5, I6, I7 and I8, current-limiting diodes Dio5, Dio6, Dio7 and Dio8, switches SW5, SW6, SW7 and SW8, wherein the current source I1 is connected with the current-limiting diode Dio1 in parallel, the current source I5 is connected with the current-limiting diode Dio5, one end of a parallel structure formed by the current source I1 and the current-limiting diode Dio1 is connected with a system high level, and the other end of the parallel structure is grounded through the switch SW1, the switch SW5 and a parallel structure formed by the current source I5 and the current-limiting diode Dio5 in sequence; the current source I2 is connected with the current-limiting diode Dio2 in parallel, and the current source I6 is connected with the current-limiting diode Dio6, wherein one end of a parallel structure consisting of the current source I2 and the current-limiting diode Dio2 is connected with a system high level, and the other end of the parallel structure sequentially passes through the switch SW2, the switch SW6, the current source I6 and the current-limiting diode Dio6 to be grounded; the current source I3 is connected with the current-limiting diode Dio3 in parallel, and the current source I7 is connected with the current-limiting diode Dio7, wherein one end of a parallel structure consisting of the current source I3 and the current-limiting diode Dio3 is connected with a system high level, and the other end of the parallel structure sequentially passes through the switch SW3, the switch SW7, the current source I7 and the current-limiting diode Dio7 to be grounded; the current source I4 is connected with the current-limiting diode Dio4 in parallel, and the current source I8 is connected with the current-limiting diode Dio8, wherein one end of a parallel structure consisting of the current source I4 and the current-limiting diode Dio4 is connected with a system high level, and the other end of the parallel structure sequentially passes through the switch SW4, the switch SW8, the current source I8 and the current-limiting diode Dio8 to be grounded; the four-bit binary code output by the first step counter is respectively output to switches SW1, SW2, SW3 and SW 4; the four-bit binary code output by the second step counter is respectively output to switches SW5, SW6, SW7 and SW 8; and one end of the power supply ICC is connected to a system power supply end, and the other end of the power supply ICC is grounded through a charging resistor Rc.
The beneficial effects of the further scheme are as follows: the current array is simple in structure, the current sources are not affected with each other, the current array is controlled only by the four-bit binary code output by the counter, the interference possibility is reduced, and the accuracy of the current during charging is improved.
Further, when the binary code received by the switches SW1 to SW8 is 1, the corresponding switches are turned off; when the received binary code is 0, the corresponding switch is turned on and charges the charging resistor Rc.
The beneficial effects of the further scheme are as follows: only half of the current array is awakened by the corresponding switch, and the switch which is not charged and the current source are in a turn-off state, so that the power consumption of the whole switch array is reduced.
Further, the middle point of the switches SW1 and SW5, the middle point of the switches SW2 and S6, the middle point of the switches SW3 and SW7, the middle point of the switches SW4 and SW8, and the middle point of the power source ICC and the charging resistor Rc are shorted as the output of the current array module. The current magnitude ratios of the current sources I1, I2, I3 and I3 and the ratios of the current sources I5, I6, I7 and I8 are all 1:2:4: 8.
the beneficial effects of the further scheme are as follows: the output is determined by the intermediate value of the upper array and the lower array, the size of the charging current source corresponds to the binary code bit number, therefore, the output result is directly related to the output result of the comparator, the result is more accurate, and the accuracy of successive approximation can be improved.
Drawings
FIG. 1 is a schematic diagram of a successive approximation type capacitance detection circuit according to the present invention.
Fig. 2 is a schematic diagram of a circuit structure of a step counter according to an embodiment of the present invention.
Fig. 3 is a schematic view of a current array structure according to an embodiment of the invention.
Fig. 4 is a schematic circuit diagram of a comparison selection module according to an embodiment of the invention.
Fig. 5 is a schematic diagram of a comparator circuit according to an embodiment of the invention.
FIG. 6 is a simulation graph of input voltage and output voltage of capacitive sensing according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.
A successive approximation type capacitance detection circuit is shown in figure 1 and comprises a comparison selection module, a step counter module, a current array module and a sampling switch;
one input end of the comparison selection module is connected with a charging current source and is grounded through a capacitor to be tested, and the other input end of the comparison selection module is connected with the output end of the current array module;
the input end of the step counter module is connected to the output end of the comparison selection module;
the input end of the current array module is connected with the output end of the step counting module, and the output end of the current array module passes through the sampling switch and then is used as the output of the successive approximation type capacitance detection circuit;
the sampling switch is also grounded through a sampling capacitor.
Specifically, as shown in fig. 4, the comparison selection module includes a comparator, a counter D6, a NAND gate NAND1, a NAND2, a NAND3, a NAND4, a NAND5, and NOR gates NOR15 and NOR16, wherein the input terminals of the comparator are respectively connected to the output of the successive approximation type capacitance detection circuit and the charging current source, and the output terminal of the comparator is connected to the D terminal of the counter D6; a clock signal is input into a CLK terminal of the counter D6, a Q terminal is output to the step counter module through a NAND gate NAND1 and a NAND gate NAND2 in sequence, and is output to the step counter module through a NOR gate NOR15, a NAND gate NAND4 and a NAND gate NAND5 in sequence; the input ends of the NAND gates 3 are respectively connected with the reset signals of the step counter, and the output ends are connected with one input end of the NOR gate NOR16 and are respectively output to the other input ends of the NAND gates NAND2 and NAND gates NAND5 through the NOR gates NOR 16; the other input terminal of the NAND gate NAND1 is connected to a clock signal, and the other input terminal of the NOR gate NOR15 and the other input terminal of the NOR gate NOR16 are grounded.
In this embodiment, the comparison control module is mainly divided into two parts, one of which is a key comparator of the successive approximation circuit, and the two parts are compared for multiple times to achieve the purpose of measuring the voltage. In the embodiment of the present invention, a two-stage open-loop comparator is adopted, and the specific structure thereof is shown in fig. 5.
The comparator adopted by the embodiment of the invention is based on an SMIC0.13 process, and the specific parameter requirements are as follows: the power supply voltage is 3V and 5V, the gain is more than 50dB, the unit gain bandwidth is more than 50MHz, the transmission delay is less than 100ns, and the power supply voltage is 2.8V-5.2V. When the power supply voltage is 5V, the output high level is more than 4.5V, the output low level is less than 1V, and the input range is as follows: 1V-4.5V, 1pF of load capacitance, more than 1000V/us of slew rate and less than 1mW of power consumption.
In order to obtain a larger common-mode input range, a folded cascode differential amplifier is used as an input stage of a comparator, and a common-source amplifier is used as an output amplification stage. The amplifier circuit formed by cascading two stages of amplifiers working in an open loop makes up for the defects of insufficient gain and bandwidth, and brings the advantages of small offset voltage, higher precision and higher speed for the whole comparator mechanism. In the figure, M1 and M2 are differential input ends, and M6 and M8 form a cascode current mirror as a load.
In small signal analysis, all MOS tubes in the comparator are kept in a saturation region to be used as a basis for determining the common-mode input range. According to the circuit configuration in the figure, the common mode input range of the comparator can be expressed as:
Vin max＝VDD-VSD7+VTHN
compared with a differential amplifier loaded by a common current mirror, the common-mode input range of the differential amplifier is as follows:
Vin max＝VDD-VGS3+VTHN
Vinmin＝VGS1+VDS5
in general, VGS is much larger than VDS, and thus, the common mode input range is increased.
The structure of the comparator adopted by the embodiment of the invention is a simplified folded cascode structure. Because the requirement on the gain is not high, the drain voltage of M3 can be used as the bias of M6-M9, the NMOS corresponding to M6-M9 is simplified into current mirrors M3 and M4, the bias is provided by VREF, two bias circuits are saved under the condition of compromising a part of the gain, and the whole area is reduced. In small signal, the transmission delay of the comparator is mainly determined by the input voltage and the minimum resolution voltage, and when the input voltage is gradually increased, the comparator enters a large signal state, the transmission delay depends on the capacity of the output stage of the comparator to share or draw out current, and the total small signal gain is the product of the gains of the two stages of amplifiers.
The whole comparator structure is responsible for comparing the charging voltage of the capacitor to be tested with the conversion voltage after successive approximation of the counters, and outputting high and low levels to control selection of the positive and negative counters in the next round. If the voltage is too low, the output of the comparator is 1, the counter A works to charge the upper part of the current array, and the current on the charging resistor is increased. And if the voltage is too high, the comparator outputs 0, the counter B works to charge the lower part of the current array, and the current on the charging resistor is reduced. So that Vout approaches the voltage Vc to be measured again.
Wherein the comparator output is coupled to a D flip-flop (D6) that functions to achieve the stored level value.
In the embodiment of the invention, the opening of each counter is controlled by two types of output of the comparator and the self RESET signal, and a series of gate circuits are used for controlling the selection of the counter AB.
As shown in fig. 4, the specific working principle is as follows:
the high and low levels output by the comparator firstly pass through the NAND gate 1 together with the clock signal, taking the charging voltage higher than the conversion voltage after successive approximation of the counter as an example:
according to the working principle of the NAND gate:
Y＝(A·B)'＝A'+B'
when the conversion voltage after successive approximation of the counter is lower, the high level output by the comparator can only pass through when the CLK signal is high, and the output level passes through the NAND gate 2. Meanwhile, the RESET signal output by the up-down counter passes through a NAND gate NAND3, because the up-down counter only works one at the same time, when the counter works to complete one cycle, one of RESET _ a and RESET _ B must be 1, and the other one is 0, and the output of the NAND gate NAND3 must be 1. The value output by the inverter INV1 is compared with 0, and is accessed into the NAND 2. Therefore, when the comparator output is 0 or the RESET signal output by the counter a is 1, the Count pulse (Count _ a) is 1, and the upper half counter a starts to operate to compensate for the lower switching voltage.
The charging voltage is lower than the conversion voltage after successive approximation of the counter, and the NAND4 and the NAND5 act on the NAND1, and the NAND2 is the same. However, since the charging voltage is lower than the converted voltage comparator output 1 after successive approximation of the counter, it needs to be converted to a low level by the inverter INV 2. And the counter B is started through the NAND4 and the NAND5, and the purpose of reducing the conversion voltage after successive approximation is finally achieved because the counter B is started.
As shown in fig. 2, the step counter module includes a first step counter and a second step counter, the first step counter includes rising edge flip-flops D1, D2, D3, D4 and D5, NOR gates NOR1, NOR2, NOR3, NOR4, NOR5, NOR6, NOR7, NOR8, NOR9, NOR10, NOR11, NOR12, NOR13 and NOR14, and exclusive or gates XOR1, XOR2, XOR3 and XOR4, wherein the rising edge flip-flops D1, D2, D3, D4 and D5 have their D and Q non-terminals shorted to constitute an asynchronous counter; one input end of the NOR gate NOR1 is connected with the output end of the NAND gate NAND2 in the comparison selection module, the other input end is grounded, and the output end is connected with the CLK end of the rising edge flip-flop D1; the Q end of the rising edge trigger D1 is output to one input end of a NOR gate NOR2 and is output to the current array module through a NOR gate NOR13, a NOR14 and an XOR gate XOR1 in sequence; the output end of the NOR gate NOR2 is connected with the CLK end of a rising edge trigger D2; the Q end of the rising edge trigger D2 is output to one input end of a NOR gate NOR3 and is output to the current array module through a NOR gate NOR11, a NOR12 and an XOR gate XOR2 in sequence; the output end of the NOR gate NOR3 is connected with the CLK end of a rising edge trigger D3; the Q end of the rising edge trigger D3 is output to one input end of a NOR gate NOR4 and is output to the current array module through a NOR gate NOR9, a NOR10 and an XOR gate XOR3 in sequence; the output end of the NOR gate NOR4 is connected with the CLK end of a rising edge trigger D4; the Q end of the rising edge trigger D4 is output to one input end of a NOR gate NOR5 and is output to the current array module through a NOR gate NOR7, a NOR8 and an XOR gate XOR4 in sequence; the output end of the NOR gate NOR5 is connected with the CLK end of the rising edge flip-flop D5, the Q end of the rising edge flip-flop D5 is output to one input end of the NOR gate NOR6, the reset signal of the ladder counter of the NOR gate NOR6 is output to one input end of the NAND gate NAND3 and is output to the other input end of the exclusive-OR gates XOR1, XOR2, XOR3 and XOR 4; the other input terminals of the NOR gates NOR1 to NOR14 are grounded; the second step counter is identical in structure to the first step counter.
In this embodiment, the outputs of the exclusive or gates XOR1, XOR2, XOR3 and XOR4 output a four-bit binary code as the output of the first ladder counter.
The asynchronous counter principle is as follows:
the input terminals of the edge D flip-flops triggered by four rising edges are all connected to Q-bar to form an asynchronous counter, so that each D flip-flop also forms a frequency division of two, and the four flip-flops are connected to form a modulo-16 counter. The output of the counter is sequentially decremented each time a clock falling edge passes. When the 16 th clock falling edge arrives, the counter output is decremented to the last count state 0000 and then ready for the next cycle, so that a down counter is formed by 4 edge D flip-flops.
In the step counter provided by the embodiment of the invention, 4 rising edge triggered edge D flip-flops (D1, D2, D3 and D4) are adopted, so that a 1111 to 0000 modulo 16 counter is formed. In contrast, as shown in fig. 2, an inverter (NOR1, NOR2, NOR3, NOR4) is connected to the clock terminal of each D flip-flop input, and the transition is to an addition counter of 0000 to 1111. The inverter is composed of a NOR gate circuit with one end grounded.
The remaining inverters, except the input side inverter, are used to increase the driving capability, so that the signal has good rising and falling edges, and at the same time, the resistance is optimized in terms of power consumption delay product when the required driving capability is obtained, wherein on each branch, the size of the latter inverter is twice that of the former one, for example, the size of the NOR14 is twice that of the NOR 13.
When 1111 counts in each round, an inverter and a D trigger (D5) are used to record the inverted value 0 of the value 1 of the counter, the output of the trigger is connected to one end of the exclusive-OR gate, and the other end is connected to the output of each bit. According to the logic expression of the exclusive-or gate:
the output of the next round at 1111 is exclusive-ored with 0 and then output as 1111. At this point 1111 is the end of each counting cycle, and the counter then operates to no longer affect the switching of the current array, the specific principle being illustrated by the latter comparative control module.
Further, the current array module comprises a first current array, a second current array, a power supply ICC and a charging resistor Rc, wherein an input end of the first current array is connected to an output end of the first step counter, and an input end of the second current array is connected to an output end of the second step counter; the first current array module comprises current sources I1, I2, I3 and I4, current limiting diodes Dio1, Dio2, Dio3 and Dio4, switches SW1, SW2, SW3 and SW 4; the second current array module comprises current sources I5, I6, I7 and I8, current-limiting diodes Dio5, Dio6, Dio7 and Dio8, switches SW5, SW6, SW7 and SW8, wherein the current source I1 is connected with the current-limiting diode Dio1 in parallel, the current source I5 is connected with the current-limiting diode Dio5, one end of a parallel structure formed by the current source I1 and the current-limiting diode Dio1 is connected with a system high level, and the other end of the parallel structure is grounded through the switch SW1, the switch SW5 and a parallel structure formed by the current source I5 and the current-limiting diode Dio5 in sequence; the current source I2 is connected with the current-limiting diode Dio2 in parallel, and the current source I6 is connected with the current-limiting diode Dio6, wherein one end of a parallel structure consisting of the current source I2 and the current-limiting diode Dio2 is connected with a system high level, and the other end of the parallel structure sequentially passes through the switch SW2, the switch SW6, the current source I6 and the current-limiting diode Dio6 to be grounded; the current source I3 is connected with the current-limiting diode Dio3 in parallel, and the current source I7 is connected with the current-limiting diode Dio7, wherein one end of a parallel structure consisting of the current source I3 and the current-limiting diode Dio3 is connected with a system high level, and the other end of the parallel structure sequentially passes through the switch SW3, the switch SW7, the current source I7 and the current-limiting diode Dio7 to be grounded; the current source I4 is connected with the current-limiting diode Dio4 in parallel, and the current source I8 is connected with the current-limiting diode Dio8, wherein one end of a parallel structure consisting of the current source I4 and the current-limiting diode Dio4 is connected with a system high level, and the other end of the parallel structure sequentially passes through the switch SW4, the switch SW8, the current source I8 and the current-limiting diode Dio8 to be grounded; the four-bit binary code output by the first step counter is respectively output to switches SW1, SW2, SW3 and SW 4; the four-bit binary code output by the second step counter is respectively output to switches SW5, SW6, SW7 and SW 8; and one end of the power supply ICC is connected to a system power supply end, and the other end of the power supply ICC is grounded through a charging resistor Rc.
When the binary codes received by the switches SW1 to SW8 are 1, the corresponding switches are turned off; when the received binary code is 0, the corresponding switch is turned on and charges the charging resistor Rc.
The middle points of the switches SW1 and SW5, the middle points of the switches SW2 and S6, the middle points of the switches SW3 and SW7, the middle points of the switches SW4 and SW8, and the middle points of the power source ICC and the charging resistor Rc are short-circuited as the output of the current array module.
The current magnitude ratios of the current sources I1, I2, I3 and I3 and the ratios of the current sources I5, I6, I7 and I8 are all 1:2:4: 8.
in this embodiment, the current array is composed of two upper and lower switch current source groups, as shown in fig. 3, only the upper half or the lower half works in each successive approximation voltage process, and is controlled by the front end, and the two groups are respectively connected to the counter. The two counters respectively measure the voltage to be compared and the inverted value thereof, and each switch current source group is provided with four switches and four current sources. Wherein, the current source I1: i2: i3: the ratio of I4 is 1:2:4:8 (the ratios of I5, I6, I7 and I8 are the same), the current sources correspond to the outputs Q1, Q2, Q3 and Q4 of the asynchronous counter, the charging and discharging of the current sources are controlled by corresponding switches Sw, the charging resistors are charged by the upper current group and the lower current group to form output voltage, and the diode (Dio1-8) only performs a limiting function, namely only uses the current sources for charging. The power ICC is set to the middle value of the upper and lower current arrays, i.e., the value that the charging resistor flows when the current arrays are not operated is ensured, which is the same as I1.
In the embodiment of the invention, the output of the counter A or B is a binary code with four bits, and when 1 is received, the switch is turned off, and the resistor is not charged; when 0 is received, the switch is turned on, charging the resistor, generating the voltage Vout, to form a measure of the magnitude of the input voltage.
Overall, according to the capacitive charge formula:
where IT-Q represents the charge of the overall capacitor and U represents the voltage between the capacitors. When the charging current I and the charging time T are fixed, the capacitance can be derived through a formula only by measuring the charging voltage between the capacitors.
In the embodiment of the present invention, the charging capacitor is charged by the charging current source Iref, and the charging current Iref is fixed.
The charging time T is set by the clock signal CLK, and the whole circuit is started only when CLK is high. Meanwhile, when the CLK is high, the counter module starts to operate, and the charging time T is set to be a half period T/2 of the clock signal CLK.
Finally, the charging voltage of the capacitor is tested by a successive approximation type circuit, and the current array under the control of the counter charges the charging resistor (Rc) to simulate the charging voltage U ═ Vout of the capacitor, and it should be noted that the charging time and the charging current of the capacitor need to be kept appropriate to prevent the occurrence of invalid charging time after the capacitor is fully charged.
As shown in fig. 6, Vout approaches Vc during each time of charging the current array by the counter operation, the selection of the counter a or B is determined by the size of the two, and finally Vout approaches Vc after multiple approaches until the error between the two is smaller than the input range of the comparator.
In the embodiment of the present invention, the charging current source Iref is set to 2uA, the clock cycle is 2uS, and Vout is measured to be 1.8V. Then according to the capacitance charging formula:
C＝(2uA*1us)/1.8V＝1.1pf
the whole capacitance measurement precision is determined by the digit of the counter, the measurement range is determined by the capacitance charging time and the charging current source, and the measurement voltage is within the input range of 1V-4.5V of the comparator. Therefore, the upgrading of the whole measuring circuit is simple and convenient, the superposition of the number of bits of the counter can bring the improvement of the precision, the charging time and the charging current can bring the improvement of the range, and the power consumption increase brought by the circuit upgrading is very weak and small, and belongs to the completely controllable range.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The principle and the implementation mode of the invention are explained by applying specific embodiments in the invention, and the description of the embodiments is only used for helping to understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.
Claims (9)
1. A successive approximation type capacitance detection circuit is characterized by comprising a comparison selection module, a step counter module, a current array module and a sampling switch;
one input end of the comparison selection module is connected with a charging current source and is grounded through a capacitor to be tested, and the other input end of the comparison selection module is connected with the output end of the current array module;
the input end of the step counter module is connected to the output end of the comparison selection module;
the input end of the current array module is connected with the output end of the step counting module, and the output end of the current array module passes through the sampling switch and then is used as the output of the successive approximation type capacitance detection circuit;
the sampling switch is also grounded through a sampling capacitor.
2. The successive approximation type capacitance detection circuit according to claim 1, wherein the comparison selection module comprises a comparator, a counter D6, a NAND gate NAND1, a NAND2, a NAND3, a NAND4, a NAND5, and an OR gate NOR15 and NOR16, wherein the input terminals of the comparator are respectively connected with the output of the successive approximation type capacitance detection circuit and a charging current source, and the output terminal of the comparator is connected with the D terminal of the counter D6; a clock signal is input into a CLK terminal of the counter D6, a Q terminal is output to the step counter module through a NAND gate NAND1 and a NAND gate NAND2 in sequence, and is output to the step counter module through a NOR gate NOR15, a NAND gate NAND4 and a NAND gate NAND5 in sequence; the input ends of the NAND gates 3 are respectively connected with the reset signals of the step counter, and the output ends are connected with one input end of the NOR gate NOR16 and are respectively output to the other input ends of the NAND gates NAND2 and NAND gates NAND5 through the NOR gates NOR 16; the other input terminal of the NAND gate NAND1 is connected to a clock signal, and the other input terminal of the NOR gate NOR15 and the other input terminal of the NOR gate NOR16 are grounded.
3. The successive approximation capacitance detection circuit according to claim 2, wherein the comparator is a two-stage open-loop comparator.
4. The successive approximation type capacitance detection circuit according to claim 3, wherein the step counter module comprises a first step counter and a second step counter, the first step counter comprises rising edge flip-flops D1, D2, D3, D4 and D5, NOR gates NOR1, NOR2, NOR3, NOR4, NOR5, NOR6, NOR7, NOR8, NOR9, NOR10, NOR11, NOR12, NOR13 and NOR14, XOR gates XOR1, 2, XOR3 and XOR4, wherein D terminals and Q non-terminals of the rising edge flip-flops D1, D2, D3, D4 and D5 are shorted to form an asynchronous counter; one input end of the NOR gate NOR1 is connected with the output end of the NAND gate NAND2 in the comparison selection module, the other input end is grounded, and the output end is connected with the CLK end of the rising edge flip-flop D1; the Q end of the rising edge trigger D1 is output to one input end of a NOR gate NOR2 and is output to the current array module through a NOR gate NOR13, a NOR14 and an XOR gate XOR1 in sequence; the output end of the NOR gate NOR2 is connected with the CLK end of a rising edge trigger D2; the Q end of the rising edge trigger D2 is output to one input end of a NOR gate NOR3 and is output to the current array module through a NOR gate NOR11, a NOR12 and an XOR gate XOR2 in sequence; the output end of the NOR gate NOR3 is connected with the CLK end of a rising edge trigger D3; the Q end of the rising edge trigger D3 is output to one input end of a NOR gate NOR4 and is output to the current array module through a NOR gate NOR9, a NOR10 and an XOR gate XOR3 in sequence; the output end of the NOR gate NOR4 is connected with the CLK end of a rising edge trigger D4; the Q end of the rising edge trigger D4 is output to one input end of a NOR gate NOR5 and is output to the current array module through a NOR gate NOR7, a NOR8 and an XOR gate XOR4 in sequence; the output end of the NOR gate NOR5 is connected with the CLK end of the rising edge flip-flop D5, the Q end of the rising edge flip-flop D5 is output to one input end of the NOR gate NOR6, the reset signal of the ladder counter of the NOR gate NOR6 is output to one input end of the NAND gate NAND3 and is output to the other input end of the exclusive-OR gates XOR1, XOR2, XOR3 and XOR 4; the other input terminals of the NOR gates NOR1 to NOR14 are grounded; the second step counter is identical in structure to the first step counter.
5. The successive approximation capacitance detection circuit of claim 4, wherein the outputs of the exclusive or gates XOR1, XOR2, XOR3 and XOR4 output a four-bit binary code as the output of the first step counter.
6. The successive approximation capacitance detection circuit according to claim 5, wherein the current array module comprises a first current array, a second current array, a power supply ICC and a charging resistor Rc, wherein an input end of the first current array is connected to an output end of the first step counter, and an input end of the second current array is connected to an output end of the second step counter; the first current array module comprises current sources I1, I2, I3 and I4, current limiting diodes Dio1, Dio2, Dio3 and Dio4, switches SW1, SW2, SW3 and SW 4; the second current array module comprises current sources I5, I6, I7 and I8, current-limiting diodes Dio5, Dio6, Dio7 and Dio8, switches SW5, SW6, SW7 and SW8, wherein the current source I1 is connected with the current-limiting diode Dio1 in parallel, the current source I5 is connected with the current-limiting diode Dio5, one end of a parallel structure formed by the current source I1 and the current-limiting diode Dio1 is connected with a system high level, and the other end of the parallel structure is grounded through the switch SW1, the switch SW5 and a parallel structure formed by the current source I5 and the current-limiting diode Dio5 in sequence; the current source I2 is connected with the current limiting diode Dio2 in parallel, the current source I6 is connected with the current limiting diode Dio6, one end of a parallel structure consisting of the current source I2 and the current limiting diode Dio2 is connected with a system high level, and the other end of the parallel structure consists of a switch SW2, a switch SW6 and a current source I6 current limiting diode Dio6 in sequence and is grounded; the current source I3 is connected with the current-limiting diode Dio3 in parallel, and the current source I7 is connected with the current-limiting diode Dio7, wherein one end of a parallel structure consisting of the current source I3 and the current-limiting diode Dio3 is connected with a system high level, and the other end of the parallel structure sequentially passes through the switch SW3, the switch SW7, the current source I7 and the current-limiting diode Dio7 to be grounded; the current source I4 is connected with the current-limiting diode Dio4 in parallel, and the current source I8 is connected with the current-limiting diode Dio8, wherein one end of a parallel structure consisting of the current source I4 and the current-limiting diode Dio4 is connected with a system high level, and the other end of the parallel structure sequentially passes through the switch SW4, the switch SW8, the current source I8 and the current-limiting diode Dio8 to be grounded; the four-bit binary code output by the first step counter is respectively output to switches SW1, SW2, SW3 and SW 4; the four-bit binary code output by the second step counter is respectively output to switches SW5, SW6, SW7 and SW 8; and one end of the power supply ICC is connected to a system power supply end, and the other end of the power supply ICC is grounded through a charging resistor Rc.
7. The successive approximation type capacitance detection circuit according to claim 6, wherein when the binary code received by the switches SW1 to SW8 is 1, the corresponding switch is turned off; when the received binary code is 0, the corresponding switch is turned on and charges the charging resistor Rc.
8. The successive approximation capacitance detection circuit according to claim 7, wherein the midpoint of the switches SW1 and SW5, the midpoint of the switches SW2 and S6, the midpoint of the switches SW3 and SW7, the midpoint of the switches SW4 and SW8, and the midpoint of the power source ICC and the charging resistor Rc are shorted as the output of the current array block.
9. The successive approximation capacitance detection circuit according to claim 8, wherein the current magnitude ratios of the current sources I1, I2, I3 and I3 and the ratios of the current sources I5, I6, I7 and I8 are all 1:2:4: 8.
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| Publication number | Priority date | Publication date | Assignee | Title |
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Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102655393A (en) * | 2012-05-21 | 2012-09-05 | 无锡中科微电子工业技术研究院有限责任公司 | ASK (Amplitude Shift Keying) modulator with self-calibration function |
| CN104617957A (en) * | 2015-01-30 | 2015-05-13 | 中国电子科技集团公司第二十四研究所 | Asynchronous successive approximation type A/D (analog to digital) converter |
| CN104779954A (en) * | 2015-04-13 | 2015-07-15 | 浙江大学 | Successive approximation type analog-to-digital converter and error code detection based digital correction method thereof |
| CN104811203A (en) * | 2015-05-19 | 2015-07-29 | 中国电子科技集团公司第二十四研究所 | 2bits per circle high-speed successive approximation type analog-digital converter |
| US9500686B1 (en) * | 2007-06-29 | 2016-11-22 | Cypress Semiconductor Corporation | Capacitance measurement system and methods |
| US20160357288A1 (en) * | 2014-06-06 | 2016-12-08 | Shenzhen Huiding Technology Co., Ltd. | Self-capacitance touch detection circuit |
| CN106796259A (en) * | 2016-11-08 | 2017-05-31 | 深圳市汇顶科技股份有限公司 | Capacitive detection circuit and its control method |
| CN109444556A (en) * | 2018-11-06 | 2019-03-08 | 湖南品腾电子科技有限公司 | A kind of novel sigma-delta capacitance touch detection circuit |
| US20200007144A1 (en) * | 2018-06-29 | 2020-01-02 | Luxtera, Inc. | Method and system for an asynchronous successive approximation register analog-to-digital converter with word completion algorithm |
| CN111525924A (en) * | 2020-06-16 | 2020-08-11 | 成都信息工程大学 | Self-calibration composite structure ADC |
| CN112737592A (en) * | 2020-12-24 | 2021-04-30 | 重庆邮电大学 | Window type successive approximation analog-to-digital converter and control method |
-
2021
- 2021-06-29 CN CN202110727143.2A patent/CN113411085B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9500686B1 (en) * | 2007-06-29 | 2016-11-22 | Cypress Semiconductor Corporation | Capacitance measurement system and methods |
| CN102655393A (en) * | 2012-05-21 | 2012-09-05 | 无锡中科微电子工业技术研究院有限责任公司 | ASK (Amplitude Shift Keying) modulator with self-calibration function |
| US20160357288A1 (en) * | 2014-06-06 | 2016-12-08 | Shenzhen Huiding Technology Co., Ltd. | Self-capacitance touch detection circuit |
| CN104617957A (en) * | 2015-01-30 | 2015-05-13 | 中国电子科技集团公司第二十四研究所 | Asynchronous successive approximation type A/D (analog to digital) converter |
| CN104779954A (en) * | 2015-04-13 | 2015-07-15 | 浙江大学 | Successive approximation type analog-to-digital converter and error code detection based digital correction method thereof |
| CN104811203A (en) * | 2015-05-19 | 2015-07-29 | 中国电子科技集团公司第二十四研究所 | 2bits per circle high-speed successive approximation type analog-digital converter |
| CN106796259A (en) * | 2016-11-08 | 2017-05-31 | 深圳市汇顶科技股份有限公司 | Capacitive detection circuit and its control method |
| US20200007144A1 (en) * | 2018-06-29 | 2020-01-02 | Luxtera, Inc. | Method and system for an asynchronous successive approximation register analog-to-digital converter with word completion algorithm |
| CN109444556A (en) * | 2018-11-06 | 2019-03-08 | 湖南品腾电子科技有限公司 | A kind of novel sigma-delta capacitance touch detection circuit |
| CN111525924A (en) * | 2020-06-16 | 2020-08-11 | 成都信息工程大学 | Self-calibration composite structure ADC |
| CN112737592A (en) * | 2020-12-24 | 2021-04-30 | 重庆邮电大学 | Window type successive approximation analog-to-digital converter and control method |
Non-Patent Citations (3)
| Title |
|---|
| JIE SUN等: "Background Calibration of Bit Weights in Pipelined-SAR ADCs Using Paired Comparators", 《IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS》, vol. 28, no. 4, pages 1074 - 1078, XP011779676, DOI: 10.1109/TVLSI.2019.2961149 * |
| 孟昊等: "一种18位SAR ADC的设计实现", 《中国集成电路》, no. 4, pages 45 - 49 * |
| 陈功等: "一种用于图像采集的复合结构ADC", 《成都信息工程大学学报》, vol. 35, no. 5, pages 499 - 504 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115840075A (en) * | 2023-02-17 | 2023-03-24 | 紫光同芯微电子有限公司 | Current detection comparison circuit |
| CN115840075B (en) * | 2023-02-17 | 2023-08-15 | 紫光同芯微电子有限公司 | Current detection comparison circuit |
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