CN113760189A - Load data filling storage method and system - Google Patents
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- 238000013461 design Methods 0.000 description 4
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/0644—Management of space entities, e.g. partitions, extents, pools
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
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Abstract
The invention provides a load data filling storage method and a system, comprising the following steps: step 1: receiving load data and storing the load data according to the priority; step 2: opening up different cache spaces and performing classified storage on different load data; and step 3: in the process of receiving and storing different load data, periodically recording write pointers of cache spaces of the different load data; and 4, step 4: after receiving a ground load data filling instruction, searching a latest writing pointer, generating a corresponding filling frame, forming a whole page of filling data together with load data, and writing the filling data into a FLASH memory according to priority; and 5: after receiving a ground load data playback instruction, searching corresponding load data, and playing back the load data which is written into the FLASH memory. The invention realizes that the load data does not meet the accurate filling of FLASH storage page data, and improves the utilization rate of FLASH storage space.
Description
Technical Field
The invention relates to the technical field of load data filling and storing, in particular to a load data filling and storing method and system.
Background
The mode of load time delay shutdown is generally adopted on the spacecraft at present, the tail of effective load data is filled with invalid load data to realize that the effective data is completely written into a data storage space, so that the descending of the effective load data is realized, the mode can not realize the accurate filling of the effective load data, and under the condition that a data transmission channel for deep space exploration is nervous, the mode has certain limitation, so that the accurate filling mode of the load data can effectively solve the timely descending of the effective load data, the utilization rate of the storage space of the effective load data is improved, and the spacecraft has better applicability and popularization.
Patent document CN104253719A (application number: CN201410461829.1) discloses a telemetry error code testing method based on subpackage telemetry filling data, which mainly describes that in the process of carrying out error code rate statistics by using the subpackage telemetry filling data, the observation of real-time telemetry is not influenced, and the content of the loading data filling aspect is not involved.
Patent document CN101304408A (application number: CN200810018359.6) discloses a processing method of remote sensing satellite load data, mainly describing a method for storing and retrieving load data according to address information, and not relating to the implementation of storage according to time information, and not relating to the description of the load data filling requirement.
Patent document CN105245313A (application number: CN201510674340.7) discloses a method for dynamically multiplexing multiple load data of an unmanned aerial vehicle, which divides the communication of the unmanned aerial vehicle into 3 application scenes of high, medium and low speed, and combines the practical characteristics of each application scene, and adopts a protocol processing device comprising a programmable gate array chip FPGA and a digital signal processing chip DSP to initiate multiplexing of transmission frames according to a timing period, and adopts a hybrid multiplexing scheme based on fixed multiplexing of low-speed data and dynamic multiplexing of high-speed data in a high-speed scene; a dynamic multiple connection scheme based on a fixed length unit is adopted in a medium-speed scene; and a pure dynamic multiplexing scheme is adopted in a low-speed scene. After various load data are accessed into the protocol processing equipment, the operation processes of data segmentation, data adaptation, storage, dynamic multiplexing framing and the like are respectively and sequentially carried out. However, the patent does not relate to the implementation of storage according to time information, and does not relate to the description of payload data stuffing requirements.
Disclosure of Invention
In view of the defects in the prior art, the invention aims to provide a payload data filling storage method and system.
The load data filling and storing method provided by the invention comprises the following steps:
step 1: receiving load data and storing the load data according to the priority;
step 2: according to the SCID and the VCID, different cache spaces are opened up, and different load data are stored in a classified manner;
and step 3: in the process of receiving and storing different load data, periodically recording write pointers of cache spaces of the different load data;
and 4, step 4: after receiving a ground load data filling instruction, searching a latest writing pointer according to SCID and VCID, generating a corresponding filling frame, forming whole page filling data together with load data, and writing the whole page filling data into a FLASH memory according to priority;
and 5: after receiving a ground load data playback instruction, searching corresponding load data according to SCID and VCID, and playing back the load data which is written into the FLASH memory.
Preferably, the payload generates data during the operation, and if the data amount does not reach 256 frames, the data is written into the DRAM and no return transfer is performed.
Preferably, after the load data filling instruction is received, the information in the filling instruction is analyzed through the field programmable gate array FPGA, a corresponding write pointer is read, and the number of filling frames is controlled to complement the load data.
Preferably, when the buffer area where the load data is located is full of 256 frames and reaches the threshold value, the load data is automatically pushed and written into the FLASH memory; when the playback command of the payload data is sent from the ground, the payload data is automatically downloaded.
Preferably, after receiving the data filling command of the load data, sending an arbitration request signal to the internal bus, generating a filling frame after the internal bus returns an arbitration authorization signal, sending the filling frame to the internal bus, and sending an arbitration clearing signal to the internal bus after the transmission of the filling frame is finished.
According to the present invention there is provided a payload data population storage system comprising:
module M1: receiving load data and storing the load data according to the priority;
module M2: according to the SCID and the VCID, different cache spaces are opened up, and different load data are stored in a classified manner;
module M3: in the process of receiving and storing different load data, periodically recording write pointers of cache spaces of the different load data;
module M4: after receiving a ground load data filling instruction, searching a latest writing pointer according to SCID and VCID, generating a corresponding filling frame, forming whole page filling data together with load data, and writing the whole page filling data into a FLASH memory according to priority;
module M5: after receiving a ground load data playback instruction, searching corresponding load data according to SCID and VCID, and playing back the load data which is written into the FLASH memory.
Preferably, the payload generates data during the operation, and if the data amount does not reach 256 frames, the data is written into the DRAM and no return transfer is performed.
Preferably, after the load data filling instruction is received, the information in the filling instruction is analyzed through the field programmable gate array FPGA, a corresponding write pointer is read, and the number of filling frames is controlled to complement the load data.
Preferably, when the buffer area where the load data is located is full of 256 frames and reaches the threshold value, the load data is automatically pushed and written into the FLASH memory; when the playback command of the payload data is sent from the ground, the payload data is automatically downloaded.
Preferably, after receiving the data filling command of the load data, sending an arbitration request signal to the internal bus, generating a filling frame after the internal bus returns an arbitration authorization signal, sending the filling frame to the internal bus, and sending an arbitration clearing signal to the internal bus after the transmission of the filling frame is finished.
Compared with the prior art, the invention has the following beneficial effects:
(1) according to the invention, the data multiplexing module writes the load data frame into the data storage module according to the priority, so that the problem of data transmission is solved;
(2) according to the invention, different cache spaces are respectively opened up for different loads according to SCID + VCID through the data storage module, so that the problem of classified storage of load data according to SCID + VCID is solved;
(3) according to the invention, the data storage module periodically returns SCID + VCID and the corresponding buffer area write pointer design, so that the problem of the data volume of subsequent load data filling frame is solved;
(4) according to the method, the data multiplexing module searches the corresponding latest write pointer parameter according to the SCID + VCID content contained in the ground filling frame instruction and the SCID + VCID contained in the instruction, so that the accurate generation and storage of the filling page data of the specific load data are realized;
(5) according to the invention, after the data storage module receives the specific load data playback instruction, the corresponding load data is searched according to SCID + VCID contained in the instruction, so that the timely downlink of the specific load data is realized.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
FIG. 1 is a data processing flow diagram of a data storage module;
fig. 2 is a schematic diagram of a data multiplexing module stuffing frame.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.
Example 1:
according to the method for realizing accurate filling and storing of the load data, which is provided by the invention, a minimum system is composed of a data multiplexing module and a data storage module, the data storage module periodically returns load SCID + VCID and write pointer parameters of corresponding cache regions to the data multiplexing module through an internal bus, the data multiplexing module automatically generates a certain number of filling frames of specific load after receiving a filling instruction of ground specific load, and the number of the filling frames is generated on a loader according to the write pointer parameters returned by the data storage module, so that the load data can be completely and accurately written into a FLASH storage space when needed, and the timely and efficient downloading of the specific load data is realized.
The method comprises the following steps: step 1: receiving the load data through a data multiplexing module, and writing the load data into a data storage module according to the priority; step 2: the data storage module opens up different cache spaces for different loads according to SCID + VCID, so as to realize classified storage of load data according to SCID + VCID; and step 3: in the process of receiving and storing different SCID + VCID load data, the data storage module periodically returns write pointers of different load data cache spaces to the data multiplexing module; and 4, step 4: after receiving a ground load data filling instruction, the data multiplexing module searches a corresponding latest writing pointer returned by the data storage module according to SCID + VCID, generates a certain number of filling frames of the SCID + VCID load, forms whole page filling data together with the original load data, and writes the whole page filling data into a FLASH of the data storage module according to priority; and 5: after receiving a ground load data playback instruction, the data multiplexing module searches for corresponding load data according to SCID + VCID, plays back the load data written in FLASH, and solves the problem that part of the load data is not full and cannot be obtained in time;
and (3) the data storage module in the step (2) opens up different cache spaces for different loads according to the SCID + VCID, so that the load data are stored according to the SCID + VCID classification. The design method of the write pointer corresponding to the load data periodically returned by the data storage module in the step 3 solves the problem of the amount of the filling frame data in the later period. And when the data multiplexing module receives the special filling instruction of the specific load in the step 4, searching the corresponding latest write pointer parameter according to the SCID + VCID contained in the instruction, thereby realizing the accurate generation and storage of the filling data of the specific load data. And when the data storage module receives the data playback instruction of the specific load in the step 5, searching for corresponding load data according to the SCID + VCID contained in the instruction, thereby realizing the timely downlink of the specific load data.
Example 2:
example 2 is a preferred example of example 1.
By adopting the method for realizing the accurate filling and storing of the load data, as shown in fig. 1, in the process of designing the data storage module, a buffer space is separately opened up according to SCID + VCID, and a write pointer of the buffer space is returned for the data multiplexing module to generate a filling frame instruction for use.
Under some working conditions, the data volume generated by the load is small and cannot reach the data volume threshold of 1 logical page of the data storage module, but the load data under the working conditions has a certain (quasi-) real-time downloading requirement, and if the load data cannot be written into the FLASH storage medium in time, the load data cannot be (quasi-) real-time replayed and downloaded.
When the payload generates a certain amount of data (SCID + VCID is 0x7D51) in a certain operation, but the amount of data does not reach 256 frames (assumed to be 100 frames), the input data is written into the cache DRAM by the data storage module; these data cannot be played back and downloaded because they are not written to FLASH storage media.
At this time, the data storage module periodically returns a write pointer (100) of the payload 7D51 to the data multiplexing module, after the data multiplexing module receives a 7D51 padding instruction, the FPGA of the data multiplexing module analyzes (7D51 information) in the padding instruction, reads that the corresponding write pointer is 100, designs a "padding data" function module in the FPGA, controls the padding data module to output 156 frames (256 and 100 are 156) of the padding frame (256 and 156) of the payload data 7D51 to the data storage module, the data storage module writes the payload data into a buffer area of the payload data 7D51 according to the original design, automatically pushes the payload data of the payload data 7D51 into a FLASH memory when the buffer area is full of 256 frames and reaches a threshold, and when a playback command of the payload data 7D51 is sent on the ground, the data storage module automatically multiplexes the payload data of the payload data 7D51 for downlink.
In fig. 2, after receiving a 7D51 padding data instruction, the data module enters a working mode, sends an arbitration request signal (pending _ req) to the internal bus multiplexing module, and after the internal bus multiplexing module returns an arbitration grant signal (pending _ gnt), generates 7D51 padding data in a format of a CADU frame, and sends the padding data to the internal bus control module; after the current CADU frame is transmitted, sending an arbitration _ clr signal to the internal bus complex data multiplexing module; the operational mode ends after the amount of filler data sent reaches the calculated value (156). The data filling module can perform complete priority request, arbitration and empowerment operation every time the data filling module sends 1 frame, and normal writing of other load data cannot be influenced.
According to the present invention there is provided a payload data population storage system comprising: module M1: receiving load data and storing the load data according to the priority; module M2: according to the SCID and the VCID, different cache spaces are opened up, and different load data are stored in a classified manner; module M3: in the process of receiving and storing different load data, periodically recording write pointers of cache spaces of the different load data; module M4: after receiving a ground load data filling instruction, searching a latest writing pointer according to SCID and VCID, generating a corresponding filling frame, forming whole page filling data together with load data, and writing the whole page filling data into a FLASH memory according to priority; module M5: after receiving a ground load data playback instruction, searching corresponding load data according to SCID and VCID, and playing back the load data which is written into the FLASH memory.
The payload generates data during the operation, and if the data amount does not reach 256 frames, the data is written into the DRAM without a wrap-around transfer. After the load data filling instruction is received, the information in the filling instruction is analyzed through the field programmable gate array FPGA, a corresponding writing pointer is read, and the number of filling frames is controlled to complement the load data. When the buffer area where the load data is located is full of 256 frames and reaches a threshold value, automatically pushing and writing the load data into a FLASH memory; when the playback command of the payload data is sent from the ground, the payload data is automatically downloaded. After receiving the load data filling data instruction, sending an arbitration request signal to the internal bus, generating a filling frame after the internal bus returns an arbitration authorization signal, sending the filling frame to the internal bus, and sending an arbitration clearing signal to the internal bus after the filling frame is transmitted.
Those skilled in the art will appreciate that, in addition to implementing the systems, apparatus, and various modules thereof provided by the present invention in purely computer readable program code, the same procedures can be implemented entirely by logically programming method steps such that the systems, apparatus, and various modules thereof are provided in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Therefore, the system, the device and the modules thereof provided by the present invention can be considered as a hardware component, and the modules included in the system, the device and the modules thereof for implementing various programs can also be considered as structures in the hardware component; modules for performing various functions may also be considered to be both software programs for performing the methods and structures within hardware components.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.
Claims (10)
1. A payload data stuffing storage method, comprising:
step 1: receiving load data and storing the load data according to the priority;
step 2: according to the SCID and the VCID, different cache spaces are opened up, and different load data are stored in a classified manner;
and step 3: in the process of receiving and storing different load data, periodically recording write pointers of cache spaces of the different load data;
and 4, step 4: after receiving a ground load data filling instruction, searching a latest writing pointer according to SCID and VCID, generating a corresponding filling frame, forming whole page filling data together with load data, and writing the whole page filling data into a FLASH memory according to priority;
and 5: after receiving a ground load data playback instruction, searching corresponding load data according to SCID and VCID, and playing back the load data which is written into the FLASH memory.
2. The method of claim 1, wherein the payload generates data during the operation, and if the amount of data does not reach 256 frames, the data is written into the DRAM without a set-down transfer.
3. The method for filling and storing the load data according to claim 1, wherein after the load data filling instruction is received, the information in the filling instruction is analyzed through a Field Programmable Gate Array (FPGA), a corresponding writing pointer is read, and the number of filling frames is controlled to complement the load data.
4. The method for filling and storing the load data according to claim 1, wherein when the buffer area where the load data is located is full of 256 frames and then reaches a threshold value, the load data is automatically pushed and written into a FLASH memory; when the playback command of the payload data is sent from the ground, the payload data is automatically downloaded.
5. The method as claimed in claim 1, wherein after receiving the data stuffing command, sending an arbitration request signal to the internal bus, generating a stuffing frame after the arbitration grant signal is returned from the internal bus, and sending the stuffing frame to the internal bus, and after the transmission of the stuffing frame is completed, sending an arbitration clear signal to the internal bus.
6. A payload data-populating storage system, comprising:
module M1: receiving load data and storing the load data according to the priority;
module M2: according to the SCID and the VCID, different cache spaces are opened up, and different load data are stored in a classified manner;
module M3: in the process of receiving and storing different load data, periodically recording write pointers of cache spaces of the different load data;
module M4: after receiving a ground load data filling instruction, searching a latest writing pointer according to SCID and VCID, generating a corresponding filling frame, forming whole page filling data together with load data, and writing the whole page filling data into a FLASH memory according to priority;
module M5: after receiving a ground load data playback instruction, searching corresponding load data according to SCID and VCID, and playing back the load data which is written into the FLASH memory.
7. A payload data-filled memory system according to claim 6 wherein the payload generates data during operation, and if the amount of data does not reach 256 frames, the data is written to DRAM without a drop-back.
8. The payload data stuffing storage system of claim 6 wherein after receiving the payload data stuffing instructions, parsing information in the stuffing instructions by the Field Programmable Gate Array (FPGA), reading the corresponding write pointers, and controlling the number of stuffing frames to complement the payload data.
9. The system according to claim 6, wherein when the buffer area where the payload data is located is full of 256 frames and reaches the threshold, the payload data is automatically pushed and written into the FLASH memory; when the playback command of the payload data is sent from the ground, the payload data is automatically downloaded.
10. A load data stuffing memory system according to claim 6 wherein upon receipt of a load data stuffing command, an arbitration request signal is issued to the internal bus, a stuffing frame is generated and sent to the internal bus upon return of an arbitration grant signal from the internal bus, and an arbitration clear signal is sent to the internal bus after transmission of the stuffing frame is complete.
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