CN114546281A - High-capacity solid-state storage control device for deep space exploration and read-write method thereof - Google Patents
High-capacity solid-state storage control device for deep space exploration and read-write method thereof Download PDFInfo
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Abstract
A mass solid-state storage control device for deep space exploration, comprising: the frame format checking unit is used for carrying out frame format checking on the load data, carrying out data synchronization on the load data passing the checking, and sending the frame data to the multi-port storage unit under the condition that the data synchronization sequence is successful; the multi-port storage unit is used for caching load data; the data scheduling unit is used for controlling the multi-port storage unit to input the cached load data into an SDRAM (synchronous dynamic random access memory) according to the received control instruction; a first control unit; and a file management control unit; wherein: when the SDRAM storage reaches a preset value, load data reaching the preset value is written into the NAND Flash through fifo under the control of the first control unit, and meanwhile attribute information of the load data is established and written into the MRAM under the control of the file management control unit. Fault tolerance measures are added in the data receiving process, and the reliability of the product is improved; and the classified caching and the fine management of the load data are realized.
Description
Technical Field
The invention belongs to the technical field of space navigation solid-state storage, and particularly relates to a high-capacity solid-state storage control device for deep space exploration and a read-write method thereof.
Background
The aerospace solid-state memory can provide support for load data acquisition, storage, on-track processing and playback. The aerospace products generally adopt NAND Flash as a main storage medium, DRAM (dynamic Random Access memory) is used as a cache, and the NAND Flash is written in after a certain amount of data is cached.
In recent years, satellite load data shows a trend that the types of the satellite load data are gradually increased and the data volume is gradually increased, particularly, deep space exploration projects have the characteristics of multiple load types, long transmission distance, low data transmission rate and the like, higher requirements are provided for the design level of space memory, and the traditional solid-state memory mostly adopts a block-based mixed storage mode, is not beneficial to the accuracy and the timeliness of data scheduling, and cannot meet application occasions with higher requirements such as deep space exploration.
Disclosure of Invention
To solve the above problems, it is an object of the present invention to provide a large-capacity solid-state storage control device for deep space exploration. The storage control device adds fault-tolerant measures in the data receiving process, thereby improving the reliability of the product; the classified cache of the load data is realized, and the files are finely managed according to pages, so that the file retrieval accuracy and timeliness of the memory are improved.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a mass solid-state storage control device for deep space exploration, comprising:
the frame format checking unit is used for carrying out frame format checking on the load data, carrying out data synchronization on the load data passing the checking, and sending the frame data to the double-port RAM unit under the condition that the data synchronization sequence is successful;
the multi-port storage unit is used for caching the load data;
the data scheduling unit is used for controlling the multi-port storage unit to input the cached load data into an SDRAM (synchronous dynamic random access memory) according to the received control instruction;
a first control unit; and a file management control unit;
wherein: under the condition that the SDRAM storage reaches a preset value, load data reaching the preset value is written into the NAND Flash through fifo under the control of the first control unit, and meanwhile attribute information of the load data is established and written into the MRAM under the control of the file management control unit.
The device adds a frame format check unit as a fault-tolerant measure in the data receiving process, thereby improving the reliability of the product; meanwhile, the load data are classified and cached by dividing channels of the SDRAM, and files are finely managed according to pages, so that the file retrieval accuracy and timeliness of the memory are improved.
The first control unit may be a NAND Flash control unit, and is configured to control NAND Flash so that written data is stored in a preset manner.
Preferably, the large-capacity solid-state storage control device for deep space exploration further comprises a serial-parallel conversion unit, and the serial-parallel conversion unit is used for increasing the bandwidth and reducing the transmission frequency of the load data subjected to frame format verification and then sending the load data to the multi-port storage unit.
Preferably, the large-capacity solid-state storage control device for deep space exploration further comprises a data output unit, and the data output unit is used for performing parallel-to-serial conversion on target data and outputting the target data. Correspondingly, the control device may further include a data output unit configured to complete conversion of the target format after data back reading.
Preferably, the large-capacity solid-state storage control device for deep space exploration further comprises a second control unit, and the second control unit is used for partitioning the SDRAM memory and caching different loads into corresponding SDRAM partition channels according to preset conditions, so as to implement load data classification caching.
The second control unit is an SDRAM control unit and is used for controlling the SDRAM.
Preferably, the second control unit is controlled by an external state machine according to a preset program.
Based on the same conception, the invention also provides a data writing method of the large-capacity solid-state storage control device for deep space exploration, which comprises the following steps:
carrying out frame format verification on the load data, and carrying out data synchronization on the load data passing the verification;
under the condition that the data synchronization sequence is successful, performing serial-parallel conversion on the frame data;
caching and transmitting the data;
performing data synchronization and writing the data into an SDRAM write cache;
and when the SDRAM write cache reaches a preset value, writing the page file into the NAND Flash through fifo, and simultaneously establishing attribute information of the page file and writing the page file into the MRAM.
Frame format verification is carried out in the data receiving process to serve as a fault-tolerant measure, so that the reliability is improved; meanwhile, the load data are classified and cached by dividing channels of the SDRAM, and files are finely managed according to pages, so that the file retrieval accuracy and timeliness of the memory are improved.
Preferably, the step of establishing that the attribute information of the page file is written to the MRAM includes:
inquiring blank block information in the MRAM;
and establishing file attribute information of the received load data, writing the attribute information into MRAM (magnetic random access memory) and writing the load data into NAND Flash.
Based on the same conception, the invention also provides a data reading method of the large-capacity solid-state storage control device for deep space exploration, which comprises the following steps:
receiving a read command, retrieving file attribute information in the MRAM, and reading data in the NAND Flash memory array to an SDRAM read cache through fifo according to pages;
the SDRAM read buffer is not empty and is output through fifo.
Optionally, the step of retrieving the file attribute information in the MRAM comprises:
the address information in the read command is extracted, the file information in the MRAM that meets the conditions is retrieved, and the file information is read out to the SDRAM read cache page by page via fifo.
Based on the same concept, the present invention also provides an electronic device, comprising:
a memory for storing a processing program;
and the processor realizes the data writing and reading method of the large-capacity solid-state storage control device for deep space exploration when executing the processing program.
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects:
the large-capacity solid-state storage control device for deep space exploration increases fault-tolerant measures in the data receiving process, and improves the reliability of products; the classified caching of the load data is realized, the files are managed finely according to pages, and the file retrieval accuracy and timeliness of the memory are improved; the method has higher integration level and is suitable for occasions with high capacity, small volume and light application requirements.
Drawings
The following detailed description of embodiments of the invention is provided in conjunction with the appended drawings, in which:
FIG. 1 is a schematic diagram of a mass solid-state storage control device;
FIG. 2 is a schematic diagram of a storage board;
FIG. 3 is a schematic diagram of a data scheduling unit;
FIG. 4 is a diagram of a SDRAM read-write control unit;
FIG. 5 is a diagram of a SDRAM read-write control unit state machine;
FIG. 6 is a diagram of an MRAM file management unit.
Detailed Description
The invention is described in further detail below with reference to the figures and specific examples. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are all used in a non-precise ratio for the purpose of facilitating and distinctly aiding in the description of the embodiments of the invention.
It should be noted that all the directional indicators (such as up, down, left, right, front, and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the movement situation, etc. in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indicator is changed accordingly.
First embodiment
Referring to fig. 1, an embodiment of the present invention provides a large-capacity solid-state storage control device for deep space exploration, which includes a frame format checking unit 1, a serial-parallel conversion unit 2, a dual-port RAM unit 3, a data scheduling unit 4, an SDRAM control unit 5, an MRAM file management control unit 6, a NAND Flash control unit 7, and a data output unit 8.
The frame format checking unit 1, the payload data format is formatted according to CCSDS AOS, the frame length is fixed to 1024 bytes, and the frame length includes a synchronization sequence, a payload type flag, an effective data area, a checking area, and the like. The load data transmission protocol adopts a 1-path clock, 1-path gating and 1-path data synchronous transmission mode, and the data bit width is 8 bits. In order to ensure the reliability of the on-track application, the situation that a certain frame of the load data is incomplete is considered, for example, fault tolerance measures aiming at load data receiving are taken when the power is on initially and the load data is in burst suspension. The method comprises the steps of judging the initial bit of each frame of load data, and discarding the abnormal data of the frame if the data synchronization sequence is judged to be failed, so as to avoid the interference to a storage system.
And the serial-parallel conversion unit 2 is used for realizing transmission bit width increase of the data stream and speed reduction processing of the transmission frequency.
And the double-port RAM unit 3 realizes clock domain crossing processing of load data. Dividing two areas according to the addresses of the double-port RAM, sending out an identification request for the data of the area after the 1 st RAM area is full of the 1 st frame, writing the frame data into a corresponding SDRAM cache channel according to the identification result of the load data, simultaneously storing the 2 nd frame load data in the 2 nd RAM area, and sequentially circulating.
As shown in fig. 3, after receiving a write instruction, the data scheduling unit 4 performs data synchronization on input data through the cache in2buf, the in2buf is full of one frame of data to be written into the SDRAM write cache channel, when the SDRAM write cache channel is full of one page of 2Mb load data, the data scheduling unit sends a write-fix request, writes the page of data into the NAND Flash through the cache buf2ssr, and simultaneously establishes attribute information of the page of file to be written into the MRAM file management control unit 6; and after receiving the read command, retrieving the file attribute information in the MRAM file management control unit 6, reading the data meeting the retrieval condition in the NAND Flash to an SDRAM read cache channel through a cache ssr2buf, and outputting the data through a cache buf2out when the SDRAM read cache channel is not empty.
As shown in fig. 4, the SDRAM control unit 5, i.e. SDRAM read/write controller, is divided into an application layer and a transport layer, where the application layer is mainly used for arbitrating requests and sending the arbitration result to the transport layer. The transmission layer mainly realizes protocol conversion of the arbitration result and generates a bottom layer operation time sequence of the SDRAM. As shown in fig. 2, the bottom layer control is implemented by using a state machine, and mainly includes a power-on initialization operation, a read-write operation, and a refresh operation, and converts the request of the application layer into a bottom layer operation timing sequence, and 8192 times of refresh are performed within 64ms by using power-on initialization stability of 200us, so as to improve the reliability of the system.
As a preferred scheme of this embodiment, 32Mb partitions (16 write channels and 16 read cache channels) are performed on the sdam arm, and different loads are cached in corresponding SDRAM partition channels according to priority. SDRAM throughput is a key factor that constrains the indexes of solid state memory. A65 MHz clock is designed, refreshing, activating, pre-charging and other operations are considered, and an SDRAM throughput rate calculation formula is as follows:
wherein f issdramIs the operating frequency of SDRAM, GsdramSubstituting f for the throughput of SDRAMsdramCalculate throughput rate G at 65MHzsdramIs 2080 Mbps.
As shown in fig. 6, the MRAM file management control unit 6 implements its file management during the read, write, erase and maintenance operations of the solid-state memory: in the writing process of the solid-state memory, firstly, blank block information in the MRAM is inquired, secondly, file attribute information of the load data is established for the received load data, and the attribute information is written into the MRAM; in the reading process of the solid-state memory, retrieving file information meeting the conditions in the MRAM; in the solid-state memory erasing process, erasing the file information of the MRAM and marking a NAND Flash bad block; and in the maintenance process of the solid-state memory, the bad block information and the file attribute information stored in the MRAM are downloaded or the data of the designated MRAM address is modified according to a ground instruction.
The NAND Flash control unit 7 completes operations such as NAND Flash writing, reading, erasing, resetting, refreshing and the like, and realizes functions such as file recording, playback, erasing and the like. In the writing process, data is written into the NAND Flash by pages through the scheduling unit 4; in the reading process, reading data in the NAND Flash by pages through the scheduling unit 4; in the erasing process, erasing or completely erasing the specified file according to an erasing instruction; in the resetting process, the NAND Flash resetting is completed through an FF resetting command word; and finishing the refreshing of the NAND Flash configuration area through an EF command word in the refreshing process.
And the data output unit 8 completes the parallel-serial conversion of the data and outputs the data to the outside after multiplexing.
As shown in fig. 2, as a preferred scheme of this embodiment, 1 FPGA is used to implement solid-state memory control, and a memory chip, an interface, and a control FPGA are integrated on a single board, so that the maximum storage capacity of the single board with a size of 6U can reach 3.375Tbits, and the single board is suitable for occasions with application requirements of large capacity, small volume, and light weight.
As a preferred scheme of this embodiment, the FPGA design is implemented by using an anti-fuse technology FPGA (field Programmable Gate Array) device AX2000-1CGS624M based on Verilog hardware description language.
As a preferable scheme of the embodiment, a 128Gb NAND Flash device 3DFN128G08 is selected for NAND Flash, and the interior of the device is formed by stacking 8 substrates MT29F16G 08. 3 sets of depth expansion are designed on the storage board, 9 pieces of parallel expansion in each set are adopted, a 9-out-of-8 fault-tolerant design is adopted, Flash read-write flows according to 8 levels, and each flow page has the capacity of 2 Mb. The invention is called page for short, which is the minimum file management unit of the invention.
As a preferred scheme of the embodiment, the MRAM adopts a 3DMR64M08 stacked device with the capacity of 64Mbits and the bit width of 8bits of 3D-PLUS company to realize file management.
As a preferred scheme of this embodiment, the SDARM selects a 3D-PLUS company 3DSD1G32VS2141 stacked device with a capacity of 1Gb and a bit width of 32bits, so as to implement payload data classification caching.
Second embodiment
Based on the same conception, the invention also provides a data writing method of the large-capacity solid-state storage control device for deep space exploration, which comprises the following steps:
carrying out frame format check on the load data, discarding the abnormal data of the frame under the condition that the data synchronization sequence fails, and sending the frame data to a serial-parallel conversion unit under the condition that the data synchronization sequence succeeds;
the serial-parallel conversion unit increases the data transmission bit width, reduces the transmission frequency and caches the data to the double-port RAM unit;
the double-port RAM caches and transmits the data;
the input data is firstly subjected to data synchronization through fifo (First In First Out, First In First Out data buffer) and then written into SDRAM write buffer;
and under the condition that the SDRAM is full of a page of data in the write cache, writing the page of data into the NAND Flash through fifo, and simultaneously establishing attribute information of the page of file and writing the attribute information into the MRAM.
Wherein the step of establishing that the attribute information of the page file is written into the MRAM comprises:
inquiring blank block information in the MRAM;
and establishing file attribute information of the received load data, writing the attribute information into MRAM (magnetic random access memory) and writing the load data into NAND Flash.
Third embodiment
Based on the same conception, the invention also provides a data reading method of the large-capacity solid-state storage control device for deep space exploration, which comprises the following steps:
after receiving a read command, retrieving file attribute information in the MRAM, and reading data in the NAND Flash memory array to an SDRAM read cache through fifo according to pages;
the SDRAM read buffer is not empty and is output through fifo.
Wherein the step of retrieving the file attribute information in the MRAM comprises:
the address information in the read command is extracted, and the file information in the MRAM that meets the condition is retrieved.
Fourth embodiment
Based on the same concept, the present invention also provides an electronic device, comprising:
a memory for storing a processing program;
and the processor is used for realizing the data writing and reading method of the large-capacity solid-state storage control device for deep space exploration when executing the processing program.
Fifth embodiment
Based on the same concept, the invention also provides a readable storage medium, which stores a processing program, and the processing program realizes the data writing and reading method of the large-capacity solid-state storage control device for deep space exploration when being executed by a processor.
The invention has the following effects:
the large-capacity solid-state storage control device for deep space exploration increases fault-tolerant measures in the data receiving process, and improves the reliability of products; the classified caching of the load data is realized, the files are managed finely according to pages, and the file retrieval accuracy and timeliness of the memory are improved; the invention realizes higher integration level of the control device of the high-capacity NAND Flash memory, the traditional solid-state memory adopts a plurality of pieces of FPGA to realize the control of the solid-state memory, the invention adopts 1 piece of FPGA to realize the control of the solid-state memory, and integrates a memory chip, an interface and the control FPGA on a single board, for example, the maximum storage capacity of the single board with the size of 6U can reach 3.375Tbits, thus being suitable for occasions with the application requirements of high capacity, small volume and light weight.
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments. Even if various changes are made to the present invention, it is still within the scope of the present invention if they fall within the scope of the claims of the present invention and their equivalents.
Claims (10)
1. A mass storage solid-state storage control device for deep space exploration, comprising:
the frame format checking unit is used for carrying out frame format checking on the load data, carrying out data synchronization on the load data passing the checking, and sending the frame data to the double-port RAM unit under the condition that the data synchronization sequence is successful;
the multi-port storage unit is used for caching the load data;
the data scheduling unit is used for controlling the multi-port storage unit to input the cached load data into an SDRAM (synchronous dynamic random access memory) according to the received control instruction;
a first control unit; and a file management control unit;
wherein: under the condition that the SDRAM storage reaches a preset value, load data reaching the preset value is written into the NAND Flash through fifo under the control of the first control unit, and meanwhile attribute information of the load data is established and written into the MRAM under the control of the file management control unit.
2. The mass solid-state storage control device for deep space exploration according to claim 1, characterized by further comprising a serial-parallel conversion unit, wherein said serial-parallel conversion unit is used for sending the payload data subjected to frame format check to the multi-port storage unit after increasing bandwidth and reducing transmission frequency.
3. The mass storage solid-state control device for deep space exploration according to claim 2, characterized by further comprising a data output unit, wherein said data output unit is used for outputting target data after parallel-to-serial conversion.
4. The large-capacity solid-state storage control device for deep space exploration according to claim 1, further comprising a second control unit, wherein the second control unit is used for partitioning the SDRAM memory and caching different loads into corresponding SDRAM partition channels according to preset conditions, so as to realize load data classification caching.
5. The mass solid-state storage control device for deep space exploration according to claim 1, characterized in that said second control unit is controlled by an external state machine according to a preset program.
6. The data read-write method of the large-capacity solid-state storage control device for deep space exploration according to any one of claims 1 to 5, characterized by comprising the following steps:
carrying out frame format verification on the load data, and carrying out data synchronization on the load data passing the verification;
under the condition that the data synchronization sequence is successful, performing serial-parallel conversion on the frame data;
caching and transmitting the data;
performing data synchronization and writing the data into an SDRAM write cache;
and when the SDRAM write cache reaches a preset value, writing the page file into the NAND Flash through fifo, and simultaneously establishing attribute information of the page file and writing the page file into the MRAM.
7. The data writing method of a large-capacity solid-state storage control device for deep space exploration according to claim 6, wherein the step of establishing that the attribute information of the page file is written to the MRAM comprises:
inquiring blank block information in the MRAM;
and establishing file attribute information of the received load data, writing the attribute information into MRAM (magnetic random access memory) and writing the load data into NAND Flash.
8. The data reading method of the large-capacity solid-state storage control device for deep space exploration according to any one of claims 1 to 5, characterized by comprising the following steps:
receiving a read command, retrieving file attribute information in the MRAM, and reading data in the NAND Flash memory array to an SDRAM read cache through fifo according to pages;
the SDRAM read buffer is not empty and is output through fifo.
9. The data reading method of the large-capacity solid-state storage control device for deep space exploration according to claim 8, wherein the step of retrieving file attribute information in MRAM comprises:
the address information in the read command is extracted, the file information in the MRAM that meets the conditions is retrieved, and the file information is read out to the SDRAM read cache page by page via fifo.
10. An electronic device, comprising:
a memory for storing a processing program;
a processor, which executes the processing program to implement the data writing or reading method of the large-capacity solid-state storage control device for deep space exploration according to any one of claims 6 to 9.
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| CN116361061A (en) * | 2023-06-01 | 2023-06-30 | 中国科学院国家空间科学中心 | Satellite-borne storage system for multi-stage data verification |
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