CN113746481A - Pipeline successive approximation analog-to-digital converter - Google Patents

Pipeline successive approximation analog-to-digital converter Download PDF

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CN113746481A
CN113746481A CN202111066435.2A CN202111066435A CN113746481A CN 113746481 A CN113746481 A CN 113746481A CN 202111066435 A CN202111066435 A CN 202111066435A CN 113746481 A CN113746481 A CN 113746481A
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stage
triode
digital converter
successive approximation
ith
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CN113746481B (en
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江文宁
诸嫣
陈知行
马许愿
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University of Macau
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

The application provides a pipeline successive approximation analog-to-digital converter, and relates to the field of analog-to-digital converters. The method comprises the following steps: the digital signal processor comprises N stages of successive approximation analog-to-digital converters and N-1 residual difference amplifiers, wherein N is an integer larger than or equal to 3, and each residual difference amplifier is an open-loop residual difference amplifier. The ith-stage successive approximation analog-to-digital converter comprises: the ith stage capacitor array and the ith stage comparator, i is any integer between 2 and N-1. The method and the device can avoid high power consumption and have high conversion precision and conversion rate.

Description

Pipeline successive approximation analog-to-digital converter
Technical Field
The application relates to the field of analog-to-digital converters, in particular to a pipeline successive approximation analog-to-digital converter.
Background
With the increasing demands for sampling accuracy and effectiveness in the fields of measurement and control systems, digital image acquisition, wireless communication, and the like, the development of an ADC (Analog-to-digital converter) is promoted. A typical analog-to-digital converter is located at an input end of a device, and converts an analog voltage signal obtained by sampling into a digital signal representing a voltage value of a certain proportion, and the conversion precision and performance of the analog-to-digital converter have a great influence on the reliability of subsequent devices.
Commonly used ADCs include Pipeline ADCs, SAR (successive approximation register) ADCs, flash ADCs, and the like. The Pipeline ADC adopts a full-parallel structure, so that the conversion speed is high, but the power consumption is high and the precision is low; the SAR ADC needs to perform comparison for multiple times in each period, the conversion precision is high, but the conversion speed is slow.
In recent years, Pipeline ADCs (successive approximation ADCs) that are a combination of Pipeline ADCs and SAR ADCs have been advanced at high speed and high accuracy, and are the focus of research in recent years. However, in the existing multistage pipeline successive approximation type analog-to-digital converter circuit, under the scene of high speed and high resolution, the requirements on the number and performance of the residual error amplifiers are still high, the power consumption of the residual error amplifier accounts for a large proportion of the overall power consumption of the ADC, and the residual error amplifier serving as a closed-loop operational amplifier needs to be designed with a high open-loop gain, so that the power consumption of the ADC is increased.
Disclosure of Invention
The application aims to provide a pipeline successive approximation analog-to-digital converter, which is used for solving the problems that the existing pipeline analog-to-digital converter is low in residual voltage amplification speed and high in overall power consumption of a circuit in a high-speed and high-resolution scene.
In order to achieve the above purpose, the technical solutions adopted in the embodiments of the present application are as follows:
the embodiment of the application provides a pipeline successive approximation analog-to-digital converter, which comprises:
the digital signal processor comprises N stages of successive approximation analog-to-digital converters and N-1 residual difference amplifiers, wherein N is an integer larger than or equal to 3, and each residual difference amplifier is an open-loop residual difference amplifier.
The ith-stage successive approximation analog-to-digital converter comprises: the ith-stage capacitor array and the ith-stage comparator, wherein i is any integer from 2 to N-1;
the input end of the ith-stage capacitor array is electrically connected with the output end of the (i-1) th residual error amplifier to receive the voltage signal amplified by the (i-1) th residual error amplifier, and the output end of the ith-stage capacitor array is electrically connected with the positive input end of the ith residual error amplifier and the positive input end of the ith-stage comparator to convert the amplified voltage signal and output the converted voltage signal to the ith residual error amplifier; the output end of the ith-stage comparator is electrically connected with the input end of the ith-stage capacitor array;
the first-stage successive approximation analog-to-digital converter comprises: the first-stage capacitor array and the first-stage comparator;
the input end of the first-stage capacitor array is used for accessing an input voltage signal, the output end of the first-stage capacitor array is electrically connected with the positive input end of the first residual error amplifier and the positive input end of the first-stage comparator, and the output end of the first-stage comparator is electrically connected with the input end of the first-stage capacitor array;
the N-th-stage successive approximation analog-to-digital converter comprises: an Nth-stage capacitor array and an Nth-stage comparator;
the input end of the Nth-stage capacitor array is electrically connected with the output end of the (N-1) th residual error amplifier, the output end of the Nth-stage capacitor array is electrically connected with the positive input end of the Nth-stage comparator, and the input end of the Nth-stage comparator is electrically connected with the input end of the Nth-stage capacitor array.
In an alternative embodiment, the residual amplifier comprises: the first triode, the second triode, the third triode and the fourth triode;
the first end of the first triode is used for being connected with a fixed voltage value of an upper polar plate of the upper-stage capacitor array, the second end of the first triode is used for outputting positive residual current, and the third end of the first triode is connected with the third end of the second triode;
the first end of the second triode is used for accessing an input voltage signal, and the second end of the second triode is used for accessing a direct current source after the current source is adjusted to be biased;
the first end of the third triode is used for accessing a fixed voltage value of an upper polar plate of the upper-stage capacitor array, the second end of the third triode is used for accessing a direct current source after the current source is adjusted to be biased, and the third end of the third triode is connected with the third end of the fourth triode;
the first end of the fourth triode is used for connecting an input voltage signal, and the second end of the fourth triode is used for outputting the residual current of the negative electrode.
In an optional implementation, the residual error amplifier further includes: a fifth triode and a sixth triode;
the first end of the fifth triode is connected with the second end of the second triode, the second end of the fifth triode is connected with the third end of the second triode, and the third end of the fifth triode is connected with the third end of the sixth triode;
the first end of the sixth triode is connected with the second end of the third triode, the second end of the sixth triode is connected with the third end of the third triode, and the third end of the sixth triode is connected with the third end of the fifth triode.
In an optional implementation, the residual error amplifier further includes: an inverter, a first switch, and a second switch;
one end of the phase inverter is electrically connected with the second switch and receives the driving signal, and the other end of the phase inverter is electrically connected with the first switch.
In an optional implementation, the residual error amplifier further includes: a seventh triode and an eighth triode;
the first end of the seventh triode is connected with the first end of the eighth triode;
the third end of the eighth triode is connected with the second end of the second triode;
and the third end of the eighth triode is connected with the second end of the third triode.
In an optional implementation, the residual error amplifier further includes: the circuit comprises a first capacitor, a third switch, a first resistor, a second capacitor, a fourth switch and a second resistor;
one end of the first capacitor is electrically connected with one end of the third switch, and the other end of the third switch is respectively connected with the first resistor and the second end of the first triode;
one end of the second capacitor is electrically connected with one end of the fourth switch, and the other end of the fourth switch is respectively connected with the first resistor and the second end of the first triode.
In an optional implementation, the i-th stage successive approximation analog-to-digital converter further includes: an ith-stage reset circuit;
one end of the ith level reset circuit is electrically connected with the ith level comparator, the other end of the ith level reset circuit is electrically connected with the ith residual error amplifier and the (i + 1) th level capacitor array of the (i + 1) th level successive approximation analog-to-digital converter, and the ith level reset circuit is used for receiving a driving signal through the ith level comparator and inputting the driving signal to the ith residual error amplifier and the (i + 1) th level capacitor array, and the driving signal is received by the ith level capacitor array from the reset circuit of the (i-1) th level successive approximation analog-to-digital converter and is transmitted to the ith level comparator;
the first stage successive approximation analog-to-digital converter further comprises: a first stage reset circuit;
one end of the first-stage reset circuit is electrically connected with the first-stage comparator, and the other end of the first-stage reset circuit is electrically connected with the first residual error amplifier and the second-stage capacitor array of the second-stage successive approximation analog-to-digital converter.
In an alternative embodiment, the pipelined successive approximation analog-to-digital converter further comprises: a clock generating circuit and a sampling switch;
one end of the sampling switch is used for accessing the input voltage signal, and the other end of the sampling switch is electrically connected with the input end of the first-stage capacitor array;
the clock generation circuit is respectively electrically connected with the sampling switch and the first-stage capacitor array.
In an alternative embodiment, the pipelined successive approximation analog-to-digital converter further comprises: a bias circuit;
the bias circuit is respectively connected with each residual difference amplifier and used for outputting bias voltage. In an alternative embodiment, the pipelined successive approximation analog-to-digital converter further comprises: offset and gain calibration circuitry;
the offset and gain calibration circuit is respectively connected with each comparator and each residual difference amplifier in each stage of successive approximation analog-to-digital converter and is used for outputting a calibration signal to each comparator and each residual difference amplifier to carry out offset and gain calibration.
The beneficial effects of the embodiment of the application are that:
by adopting the pipeline successive approximation analog-to-digital converter provided by the application, since the successive approximation analog-to-digital converter is adopted at each stage of the pipeline analog-to-digital converter to carry out multi-bit conversion, the power consumption of the analog-to-digital converter is reduced and the number of rear-end residual error amplifiers is reduced under the high-speed and high-resolution scene. Meanwhile, the residual error amplifier adopts an open-loop structure, and power consumption of the residual error amplifier for closed-loop operation due to open-loop gain is avoided.
Furthermore, the residual error amplifier adopts an open-loop structure, residual error current is directly converted into output voltage through a resistance load, a capacitance negative feedback structure of the residual error amplifier with a closed-loop structure is omitted, the amplification speed is improved, and the power consumption of the analog-to-digital converter is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a schematic structural diagram of a pipeline analog-to-digital converter proposed in the present application;
fig. 2 is a schematic diagram of a capacitor arrangement of an i-th stage successive approximation analog-to-digital converter of the pipeline analog-to-digital converter proposed in the present application;
fig. 3 is a schematic structural diagram of a residual error amplifier with an open-loop structure of a pipeline analog-to-digital converter proposed in the present application;
FIG. 4 is a graph of the output spectrum of the pipeline successive approximation analog-to-digital converter proposed in the present application;
FIG. 5 is a DNL/INL simulation result of the pipeline successive approximation analog-to-digital converter proposed in the present application.
Icon: 10-a pipeline successive approximation analog-to-digital converter; 100-a sampling switch; 101-a first stage successive approximation analog-to-digital converter; 1011-first stage capacitor array; 1012-first stage comparator; 1013-a first stage reset circuit; 102-a first residual amplifier; 103-ith stage successive approximation analog-to-digital converter; 1031-ith stage capacitor array; 1032-ith stage comparator; 1033-ith stage reset circuit; 104-ith residual amplifier; 105-nth stage successive approximation analog-to-digital converter; 1051-nth stage capacitor array; 1052-nth stage comparator; 106-a bias circuit; 107-offset and gain calibration circuitry; 108-a clock generation circuit; 20-a residual amplifier; 201-positive circuit of the residual difference amplifier; 202-negative pole circuit of residual error amplifier.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
The structure of the pipeline analog-to-digital converter has great requirements in high-speed and high-resolution application, the traditional pipeline analog-to-digital converter has great power consumption when carrying out multi-bit quantization, and meanwhile, the power consumption generated by a residual error amplifier of a closed loop structure accounts for a great proportion of the power consumption of the whole analog-to-digital converter. In order to improve the conversion speed of the analog-to-digital converter and reduce the power consumption, the application provides the assembly line successive approximation analog-to-digital converter, and each stage of the assembly line analog-to-digital converter adopts a successive approximation type analog-to-digital converter to perform multi-bit conversion, so that the power consumption of the analog-to-digital converter is reduced, and the number of rear-end residual error amplifiers is reduced. Meanwhile, the application also provides a residual error amplifier with an open-loop structure, and compared with the residual error amplifier with the closed-loop structure, the residual error amplifier has higher amplification speed and lower power consumption.
The following explains a pipelined successive approximation analog-to-digital converter provided by the embodiment of the present application with reference to a plurality of specific application examples.
The application provides a pipeline successive approximation analog-to-digital converter, including: the digital signal processor comprises N stages of successive approximation analog-to-digital converters and N-1 residual difference amplifiers, wherein N is an integer larger than or equal to 3, and each residual difference amplifier is an open-loop residual difference amplifier. For convenience of description, the following description will be made with reference to fig. 1 in which N is 3.
Fig. 1 is a schematic structural diagram of a pipeline successive approximation analog-to-digital converter provided in the present application. As shown in fig. 1, the i-th stage successive approximation analog-to-digital converter 103 of the pipeline successive approximation analog-to-digital converter 10 includes:
the ith stage capacitor array 1031 and the ith stage comparator 1032 i are any integer from 2 to N-1. In the example of fig. 1, i is 2. An input end of the ith-stage capacitor array 1031 is electrically connected to an output end of the (i-1) th residual amplifier, that is, the first residual amplifier 102, so as to receive the voltage signal amplified by the (i-1) th residual amplifier, that is, the first residual amplifier 102, an output end of the ith-stage capacitor array 1031 is electrically connected to a positive input end of the ith residual amplifier 104 and a positive input end of an ith-stage comparator 1032, so as to convert the amplified voltage signal and output the converted voltage signal to the ith residual amplifier 104, and an output end of the ith-stage comparator 1032 is electrically connected to an input end of the ith-stage capacitor array 1031.
In this embodiment, the analog-to-digital conversion process of the i-th successive approximation analog-to-digital converter 103 is as follows: the residual difference voltage amplified by the i-1 th residual difference amplifier, i.e. the first residual difference amplifier 102, is input to the top plate of the i-th capacitor array 1031 and fixed, and the i-th comparator 1032 compares the reference voltage signal V input to the i-th capacitor array 1031refAnd the magnitude of the voltage signal amplified by the i-1 th residual amplifier, i.e., the first residual amplifier 102, if the voltage signal amplified by the i-1 th residual amplifier, i.e., the first residual amplifier 102, is greater than the reference voltage signal VrefOutput logic of comparator of i-th stageAnd a high level "1" is input to the top plate of the ith-stage capacitor array 1031 for fixing, otherwise, the ith-stage comparator outputs a logic low level "0" and is input to the top plate of the ith-stage capacitor array 1031 for fixing. Subsequently, the reference voltage signal V is changedrefTo VrefAnd/2, the next comparison is performed, and the comparison process continues until the lowest bit. After the conversion is finished, outputting an ith-level analog-to-digital conversion result DoutiAnd fixed on the top plate of the capacitive array of the i-th stage capacitive array 1031. Then, the input voltage signal V is converted into the voltage signaliniAnd ith-stage analog-to-digital conversion result DoutiThe difference value of (a), i.e. the ith stage residual difference voltage signal, is transmitted to the ith residual difference amplifier. Wherein, the input voltage signal V of the ith-stage successive approximation analog-to-digital converter ini1/2 being the input voltage signal of the i-1 th stage successive approximation analog-to-digital converter, i.e. the input voltage signal V of the i-th stage successive approximation analog-to-digital converteriniIs a Vini-1/2。
Optionally, the first-stage successive approximation analog-to-digital converter 101 includes: a first stage capacitor array 1011 and a first stage comparator 1012. The input end of the first-stage capacitor array 1011 is used for receiving an input voltage signal, the output end of the first-stage capacitor array 1011 is electrically connected with the positive input end of the first residual error amplifier 102 and the positive input end of the first-stage comparator 1012, and the output end of the first-stage comparator 1012 is electrically connected with the input end of the first-stage capacitor array 1011.
The analog-to-digital conversion process of the first-stage successive approximation analog-to-digital converter 101 is as follows: input voltage signal V sampled by sampling switch 100inThe reference voltage is inputted to the top plate of the first-stage capacitor array 1011, and the reference voltage signal V is inputted to the first-stage capacitor arrayrefThe first stage comparator 1012 compares the reference voltage signal V input to the first stage capacitor array 1011refAnd an input voltage signal VinIf the voltage signal V is inputinThe amplified voltage signal is greater than the reference voltage signal VrefIf the voltage is lower than the threshold voltage, the first-stage comparator outputs a logic high level "1" and inputs the logic high level "1" to the top plate of the first-stage capacitor array 1011 for fixing, otherwise, the first-stage comparator outputs a logic low level "0" and inputs the logic low level "0" to the second-stage capacitor arrayThe top plate of the primary capacitor array 1011 is fixed. Subsequently, the reference voltage signal V is changedrefTo VrefAnd/2, the next comparison is performed, and the comparison process continues until the lowest bit. After the conversion is finished, a first-stage analog-to-digital conversion result D is obtainedout1And is fixed on the top plate of the capacitor array of the first stage capacitor array 1011. Then, the input voltage signal V is converted into the voltage signalinAnd first stage analog-to-digital conversion result Dout1The difference of (a), the first stage residual voltage signal, is transmitted to the first residual amplifier 102. Wherein, the input voltage signal V of the first-stage successive approximation analog-to-digital converterinInput voltage signal V sampled by sampling switch 100inThe same is true.
Optionally, the nth-stage successive approximation analog-to-digital converter 105 includes: an nth stage capacitor array 1051 and an nth stage comparator 1052. An input terminal of the nth stage capacitor array 1051 is electrically connected to an output terminal of an N-1 th residual amplifier, i.e., the ith residual amplifier 104 in fig. 1, an output terminal of the nth stage capacitor array 1051 is electrically connected to a positive input terminal of the nth stage comparator 1052, and an input terminal of the nth stage comparator 1052 is electrically connected to an input terminal of the nth stage capacitor array 1051.
The analog-to-digital conversion process of the nth-stage successive approximation analog-to-digital converter 105 is as follows: the residual voltage amplified by the nth-1 residual amplifier, i.e., the ith residual amplifier 104 in the figure, is input to the top plate of the capacitor array of the nth capacitor array 1051 and fixed, and the nth comparator 1052 compares the reference voltage signal V input to the nth capacitor array 1051refAnd the magnitude of the voltage signal amplified by the nth-1 residual amplifier, i.e., the ith residual amplifier 104 in the figure, if the voltage signal amplified by the nth-1 residual amplifier, i.e., the ith residual amplifier 104 in the figure, is greater than the reference voltage signal VrefIf not, the nth comparator outputs a logic low level "0" and inputs the logic low level "1" to the top plate of the nth capacitor array 1051. Subsequently, the reference voltage signal V is changedrefTo VrefAnd/2, the next comparison is performed, and the comparison process continues until the lowest bit. The above-mentioned rotary shaftAfter the conversion is finished, outputting an Nth-stage analog-to-digital conversion result DoutNAnd is fixed on the top plate of the capacitor array of the nth stage capacitor array 1051. Wherein, the input voltage signal V of the Nth-stage successive approximation analog-to-digital converter inN1/2 being the input voltage signal of the N-1 st stage successive approximation analog-to-digital converter, i.e. the input voltage signal V of the N-th stage successive approximation analog-to-digital converterinNIs a VinN-1/2。
After the multistage analog-to-digital conversion is completed, the first stage analog-to-digital conversion result Dout1To Nth stage analog-to-digital conversion result DoutNAdding the results of (1), and outputting an addition result Dout. Wherein, the bit number of the analog-to-digital conversion result of any stage is determined by the set result bit number DoutI.e. the requirements of accuracy and speed are approximately equally distributed.
Alternatively, as shown in fig. 2, the capacitance sizes of any stage of the capacitance array of the N-stage successive approximation analog-to-digital converter are arranged according to 2 raised to the power of exponent. Taking the i-th-stage successive approximation analog-to-digital converter as an example, the reference capacitance is set to be CuiThen, the size of any stage of capacitor array is: 8Cui、4Cui、2Cui、Cui、Cdumi. Wherein, CdumiIs the weight capacitance.
In the multistage pipeline successive approximation analog-to-digital converter adopted in the embodiment, a successive approximation analog-to-digital converter is adopted at each stage of the pipeline analog-to-digital converter, so that the power consumption of the analog-to-digital converter is reduced and the number of back-end residual error amplifiers is reduced in a high-speed high-resolution scene. The residual error amplifier connected with the rear end of each stage of successive approximation type analog-to-digital converter adopts an open loop structure, so that the amplification speed is improved, and the power consumption of the analog-to-digital converter is reduced.
With continued reference to fig. 1, the i-th stage successive approximation analog-to-digital converter 103 further includes: the ith stage reset circuit 1033. One end of the ith stage reset circuit 1033 is electrically connected to the ith stage comparator 1032, and the other end of the ith stage reset circuit 1033 is electrically connected to the ith residual amplifier 104 and the (i + 1) th stage capacitor array of the (i + 1) th stage successive approximation analog-to-digital converter, for receiving the driving signal Φ through the ith stage comparator 1032CiAnd to the ith residual amplifier 104 and the ith+1 stage capacitor array input drive signal phiRAiOf the drive signal phiRAi-1The ith stage capacitor array 1031 receives and transfers the reset circuit from the ith-1 stage successive approximation analog-to-digital converter to the ith stage comparator 1032. As shown in fig. 1, the first-stage successive approximation analog-to-digital converter 101 further includes: the first stage reset circuit 1013. One end of the first stage reset circuit 1013 is electrically connected to the first stage comparator 1012, and the other end of the first stage reset circuit 1013 is electrically connected to the first residual amplifier 102 and the second stage capacitor array of the second stage successive approximation analog-to-digital converter.
In the first stage successive approximation analog-to-digital converter 101, the first stage reset circuit 1013 is used to transfer a clock signal, and mainly includes two aspects: on the one hand, the clock signal phi is received through the first-stage capacitor array 1011C1On the other hand from the received clock signal phiC1Sending a drive signal phiRA1And the second-stage capacitor array of the second-stage successive approximation analog-to-digital converter and the first residual error amplifier 102 drive the second-stage successive approximation analog-to-digital converter and the first residual error amplifier 102 to start working.
In the i-th successive approximation analog-to-digital converter 103, the i-th reset circuit is used for transferring a clock signal, and mainly includes two aspects: on one hand, receives the driving signal phi generated by the i-1 th stage reset circuitRAi-1I.e. phi in fig. 1RA1Clock signal phi via ith-stage capacitor arrayCiOn the other hand from the received clock signal phiCiSending a drive signal phiRAiAnd driving the (i + 1) th stage successive approximation analog-to-digital converter and the ith residual error amplifier 104 to start working from the (i + 1) th stage capacitor array of the (i + 1) th stage successive approximation analog-to-digital converter and the ith residual error amplifier 104.
In the N-th stage successive approximation analog-to-digital converter 105, the driving signal phi generated by the reset circuit of the N-1-th stageRAN-1I.e. phi in fig. 1RAiClock signal phi via Nth stage capacitor arrayCNAnd driving the Nth-stage successive approximation analog-to-digital converter to start working.
In this embodiment, the reset circuit is used to implement the transition and transmission of the clock signal, so as to drive the sequential operation of the successive approximation analog-to-digital converter of the whole pipeline.
Optionally, as shown in fig. 1, the pipelined successive approximation analog-to-digital converter further includes: a clock generation circuit 108 and a sampling switch 100. One end of the sampling switch 100 is used for connecting an input electrical signal VinThe other end of the sampling switch 100 is electrically connected to an input terminal of the first-stage capacitor array 1011. The clock generation circuit 108 is electrically connected to the sampling switch 100 and the first-stage capacitor array 1011, respectively.
The clock generation circuit 108 is used for generating a clock signal and driving different parts of the pipeline successive approximation analog-to-digital converter to work at different time intervals, so that asynchronous logic of the circuit is realized.
The sampling switch 100 is used for inputting an electrical signal VinSampling is performed on the clock signal phi generated by the clock generation circuit 108SWhen the value is "1", the sampling switch 100 is closed to input the electric signal VinThe top plate of the capacitor array input to the first-stage capacitor array 1011 is fixed.
With continued reference to fig. 1, the pipelined successive approximation analog-to-digital converter further comprises: a bias circuit 106. The bias circuit 106 is connected to each residual error amplifier, and is configured to output a bias voltage to the seventh transistor and the eighth transistor, so as to maintain stability of the seventh transistor and the eighth transistor.
As shown in fig. 1, the pipeline successive approximation analog-to-digital converter further includes: an imbalance and gain calibration circuit 107. The circuit is respectively connected with each comparator and each residual difference amplifier in each stage of successive approximation analog-to-digital converter and is used for outputting a calibration signal to each comparator and each residual difference amplifier for offset and gain calibration.
The role of the detuning and gain calibration circuit 107 includes two aspects: on the one hand, for the first-stage analog-to-digital conversion result Dout1To Nth stage analog-to-digital conversion result DoutNOutput result of (D) merging, output digital conversion result Dout. Wherein the digital conversion result DoutThe more the number of bits, the more accurate the result. On the other hand, the offset and gain calibration circuit 107 is used for calibrating the output of the first stage according to the analog-to-digital conversion result Dout1To Nth stage analog-to-digital conversion result DoutNAnd sending a calibration signal to each stage of successive approximation analog-to-digital converter to adjust the offset voltage of each stage of successive approximation analog-to-digital converter.
The above-described residual amplifier having an open-loop structure is explained as follows.
Alternatively, as shown in fig. 3, the residual amplifier 20 having an open loop structure includes: a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4. Wherein, the first end of the first triode M1 is used for accessing the fixed voltage signal V of the upper polar plate of the upper-stage capacitor arrayipThe second end of the first triode M1 is used for outputting the residual current of the positive pole, and the third end of the first triode M1 is connected with the third end of the second triode. The first end of the second triode M2 is used for receiving the input voltage signal VinAnd the second end of the second triode M2 is connected with a direct current source after the current source is adjusted to be biased. The first end of the triode M3 is used for connecting a fixed voltage signal V of the upper polar plate of the upper-stage capacitor arrayipThe second end of the third triode M3 is used for accessing a direct current source after the current source is adjusted to be biased, and the third end of the third triode M3 is connected with the third end of the fourth triode. The first end of the fourth triode M4 is used for receiving the input voltage signal VinAnd the second end of the fourth triode M4 is used for outputting the residual current of the negative pole.
Optionally, the residual amplifier 20 having the open-loop structure further includes: a fifth transistor M5 and a sixth transistor M6. A first end of the fifth triode M5 is connected to a second end of the second triode M2, a second end of the fifth triode M5 is connected to a third end of the second triode M2, and a third end of the fifth triode M5 is connected to a third end of the sixth triode M6. A first end of the sixth triode M6 is connected to the second end of the third triode M3, a second end of the sixth triode M6 is connected to the third end of the third triode M3, and a third end of the sixth triode M6 is connected to the third end of the fifth triode M5.
In the present embodiment, because the circuit of the residual error amplifier 20 adopts a differential design, the transistors of the residual error amplifier 20 are arranged in a left-right symmetrical manner, and the residual error amplifierThe positive electrode circuit 201 comprises a first triode M1, a second triode M2, a fifth triode M5, a seventh triode M7 and a first resistor RO1And a third switch Sr3And a first capacitor CS1. The negative circuit 202 of the residual error amplifier comprises a third triode M3, a fourth triode M4, a sixth triode M6, an eighth triode M8 and a second resistor RO2And a fourth switch Sr4And a second capacitor CS2. In the residual amplifier 20, the signal input terminal is defined as a first terminal of a transistor, an upward terminal in the drawing is defined as a second terminal, and a downward terminal in the drawing is defined as a third terminal.
The first triode M1, the second triode M2, the third triode M3, the fourth triode M4, the fifth triode M5 and the sixth triode M6 form a transconductance with current negative feedback, and the input voltage V is inputinAnd a fixed voltage signal V of the upper plate of the upper-stage capacitor arrayipThe difference, i.e., the residual voltage, is converted to a residual current. The transconductance part is designed by adopting a current negative feedback structure, namely a fifth triode M5 and a sixth triode M6, and is used for realizing a small output equivalent impedance at the source ends of the second triode M2 and the third triode M3.
In this embodiment, a transconductance structure with current negative feedback is adopted, so that the linearity of the residual difference voltage-residual difference current conversion process of the residual difference amplifier is greatly improved. In addition, the current negative feedback structure formed by the second triode and the third triode also enables the residual error amplifier in the embodiment to be stable under different input signals.
Optionally, the residual amplifier 20 further includes: inverter and first switch Sr1And a second switch Sr2. One end of the inverter is connected to the second switch Sr2Electrically connected to and receiving the driving signal, the other end of the inverter and the first switch Sr1And (6) electrically connecting.
The residual error amplifier 20 in this embodiment adopts a dynamic working process, and when the residual error amplifier 20 works, the second switch Sr2Closed, drive signal phiRAThrough a second switch Sr2Is input to a residual difference amplifier 20 and,the residual difference amplifier 20 is driven to amplify the residual difference voltage signal. After the amplification is finished, the second switch Sr2Open, first switch Sr1Closed, residual amplifier 20 receives the phase-inverted drive signal Φ from the inverterRAThe residual amplifier 20 stops operating.
In the present embodiment, a first switch S is utilizedr1And a second switch Sr2And the dynamic working mode can effectively reduce the power consumption of the residual error amplifier, thereby reducing the total power consumption of the pipeline successive approximation analog-to-digital converter.
Optionally, the residual amplifier further includes: a seventh transistor M7 and an eighth transistor M8. A first end of the seventh transistor M7 is connected to a first end of the eighth transistor M8, a third end of the eighth transistor M8 is connected to a second end of the second transistor M2, and a third end of the eighth transistor M8 is connected to a second end of the third transistor M3.
It can be seen that the second terminals of the seventh transistor M7 and the eighth transistor M8 are connected to a dc current source, and in order to make the operation state of the seventh transistor M7 and the eighth transistor M8 amplifying the voltage more stable, a bias voltage is connected to the first terminals of the seventh transistor M7 and the eighth transistor M8. After the voltage bias of the dc current source is adjusted, the seventh transistor M7 and the eighth transistor M8 transmit the dc current source after the current source bias is adjusted to the second transistor M2 and the third transistor M3 to supply power to the residual error amplifier.
In this embodiment, the seventh transistor M7 and the eighth transistor M8 of the residual error amplifier 20 regulate the dc current source by the applied bias voltage, so that the residual error amplifier operates in an amplifying state stably.
Optionally, the residual amplifier further includes: a first capacitor CS1And a third switch Sr3A first resistor RO1A second capacitor CS2And a fourth switch Sr4And a second resistor RO2. A first capacitor CS1And a third switch Sr3Is electrically connected to the third switch Sr3The other end of the first resistor R is respectively connected with the first resistor RO1And a firstAnd the second end of the transistor M1 is connected. Second capacitor CS2And a fourth switch Sr4Is electrically connected to the fourth switch Sr4The other end of the first resistor is respectively connected with a second resistor RO2And a second terminal of the fourth transistor M4.
Wherein the third switch and the fourth switch control the driving signal phiS1And phiS2，ΦS1And phiS2Equal to the drive signal phi input to the residual amplifier 20RA. After the first triode M1 and the fourth triode M4 output residual current, a resistance load is output, namely a first resistor RO1And a second resistor RO2Converting the residual current into positive residual voltage VOPAnd negative residual voltage VONAnd stored in the first capacitor CS1And a second capacitor CS2In (1). A first capacitor CS1And a second capacitor CS2The difference of the voltage signals is the residual amplified signal.
In this embodiment, the residual error amplifier is designed by a differential circuit, and the positive residual error voltage V is converted into a positive residual error voltage VOPAnd negative residual voltage VONThe difference value of the two outputs is used as a residual amplified signal, so that errors are avoided. In addition, the residual error amplifier in the embodiment adopts an open-loop structure, residual error current is directly converted into output voltage through a resistance load, a capacitance negative feedback structure of the residual error amplifier in a closed-loop structure is omitted, the amplification speed is improved, and the power consumption of the analog-to-digital converter is reduced.
Fig. 4 is a diagram of an output spectrum of the pipeline successive approximation analog-to-digital converter proposed in the present application. The pipelined analog-to-digital converter adopts a 28nm standard CMOS process to carry out circuit design and carries out tape-out verification. The whole circuit works under the voltage of a 1V power supply, the sampling frequency is 1GS/s, the amplitude of an input signal is 1.2Vpp-diff, and the power consumption of the pipeline successive approximation analog-to-digital converter is 7.6 mW. When the input frequency is 495.19MHz, the test results in the output frequency spectrum (down-decimated by 225 times) of the pipeline successive approximation analog-to-digital converter shown in FIG. 4. Through calculation of fig. 4, a signal-to-noise and distortion ratio (SNDR) of the pipeline successive approximation analog-to-digital converter provided by the present application is 60dB, a quality factor reaches 9.3 fJ/con-step, and the highest energy efficiency and quality factor under the same speed and signal-to-noise ratio index are achieved.
FIG. 5 is a DNL/INL simulation result of the pipeline successive approximation analog-to-digital converter proposed in the present application. The result obtained by inputting a sinusoidal signal, converting by the ADC millions of times and counting the code density output by the ADC is shown.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A pipelined successive approximation analog-to-digital converter, comprising:
the digital signal processing circuit comprises N stages of successive approximation analog-to-digital converters and N-1 residual difference amplifiers, wherein N is an integer greater than or equal to 3, and each residual difference amplifier is an open-loop residual difference amplifier;
the ith-stage successive approximation analog-to-digital converter comprises: the ith-stage capacitor array and the ith-stage comparator, wherein i is any integer from 2 to N-1;
the input end of the ith-stage capacitor array is electrically connected with the output end of the (i-1) th residual error amplifier to receive the voltage signal amplified by the (i-1) th residual error amplifier, and the output end of the ith-stage capacitor array is electrically connected with the positive input end of the ith residual error amplifier and the positive input end of the ith-stage comparator to convert the amplified voltage signal and output the converted voltage signal to the ith residual error amplifier; the output end of the ith-stage comparator is electrically connected with the input end of the ith-stage capacitor array;
the first-stage successive approximation analog-to-digital converter comprises: the first-stage capacitor array and the first-stage comparator;
the input end of the first-stage capacitor array is used for accessing an input voltage signal, the output end of the first-stage capacitor array is electrically connected with the positive input end of a first residual error amplifier and the positive input end of the first-stage comparator, and the output end of the first-stage comparator is electrically connected with the input end of the first-stage capacitor array;
the N-th-stage successive approximation analog-to-digital converter comprises: an Nth-stage capacitor array and an Nth-stage comparator;
the input end of the Nth-level capacitor array is electrically connected with the output end of the (N-1) th residual error amplifier, the output end of the Nth-level capacitor array is electrically connected with the positive input end of the Nth-level comparator, and the input end of the Nth-level comparator is electrically connected with the input end of the Nth-level capacitor array.
2. The pipelined successive approximation analog-to-digital converter of claim 1, wherein said residual amplifier comprises: the first triode, the second triode, the third triode and the fourth triode;
the first end of the first triode is used for being connected with a fixed voltage value of an upper polar plate of the upper-stage capacitor array, the second end of the first triode is used for outputting positive residual current, and the third end of the first triode is connected with the third end of the second triode;
the first end of the second triode is used for accessing an input voltage signal, and the second end of the second triode is used for accessing a direct current source after the current source is adjusted to be biased;
the first end of the third triode is used for being connected with a fixed voltage value of an upper polar plate of the upper-stage capacitor array, the second end of the third triode is used for being connected with a direct current source after the current source is adjusted to be biased, and the third end of the third triode is connected with the third end of the fourth triode;
the first end of the fourth triode is used for accessing an input voltage signal, and the second end of the fourth triode is used for outputting residual current of a negative electrode.
3. The pipelined successive approximation analog-to-digital converter of claim 2, wherein said residual amplifier further comprises: a fifth triode and a sixth triode;
a first end of the fifth triode is connected with a second end of the second triode, a second end of the fifth triode is connected with a third end of the second triode, and a third end of the fifth triode is connected with a third end of the sixth triode;
the first end of the sixth triode is connected with the second end of the third triode, the second end of the sixth triode is connected with the third end of the third triode, and the third end of the sixth triode is connected with the third end of the fifth triode.
4. The pipelined successive approximation analog-to-digital converter of claim 3, wherein said residual amplifier further comprises: an inverter, a first switch, and a second switch;
one end of the phase inverter is electrically connected with the second switch and receives a driving signal, and the other end of the phase inverter is electrically connected with the first switch.
5. The pipelined successive approximation analog-to-digital converter of claim 4, wherein said residual amplifier further comprises: a seventh triode and an eighth triode;
the first end of the seventh triode is connected with the first end of the eighth triode;
the third end of the eighth triode is connected with the second end of the second triode;
and the third end of the eighth triode is connected with the second end of the third triode.
6. The pipelined successive approximation analog-to-digital converter of claim 5, wherein said residual amplifier further comprises: the circuit comprises a first capacitor, a third switch, a first resistor, a second capacitor, a fourth switch and a second resistor;
one end of the first capacitor is electrically connected with one end of the third switch, and the other end of the third switch is respectively connected with the first resistor and the second end of the first triode;
one end of the second capacitor is electrically connected with one end of the fourth switch, and the other end of the fourth switch is respectively connected with the first resistor and the second end of the first triode.
7. The pipelined successive approximation analog-to-digital converter according to any one of claims 1 to 6, wherein the i-th stage successive approximation analog-to-digital converter further comprises: an ith-stage reset circuit;
one end of the ith-stage reset circuit is electrically connected with the ith-stage comparator, the other end of the ith-stage reset circuit is electrically connected with the ith residual error amplifier and an i +1 th-stage capacitor array of the (i + 1) th-stage successive approximation analog-to-digital converter, and is used for receiving a driving signal through the ith-stage comparator and inputting the driving signal to the ith residual error amplifier and the i +1 th-stage capacitor array, and the driving signal is received by the ith-stage capacitor array from a reset circuit of the (i-1) th-stage successive approximation analog-to-digital converter and is transmitted to the ith-stage comparator;
the first stage successive approximation analog-to-digital converter further comprises: a first stage reset circuit;
one end of the first-stage reset circuit is electrically connected with the first-stage comparator, and the other end of the first-stage reset circuit is electrically connected with the first residual error amplifier and a second-stage capacitor array of the second-stage successive approximation analog-to-digital converter.
8. The pipelined successive approximation analog-to-digital converter according to any one of claims 1 to 6, further comprising: a clock generating circuit and a sampling switch;
one end of the sampling switch is used for accessing the input voltage signal, and the other end of the sampling switch is electrically connected with the input end of the first-stage capacitor array;
the clock generation circuit is respectively electrically connected with the sampling switch and the first-stage capacitor array.
9. The pipelined successive approximation analog-to-digital converter according to any one of claims 1 to 6, further comprising: a bias circuit;
the bias circuit is respectively connected with each residual difference amplifier and used for outputting bias voltage.
10. The pipelined successive approximation analog-to-digital converter according to any one of claims 1 to 6, further comprising: offset and gain calibration circuitry;
the offset and gain calibration circuit is respectively connected with each comparator and each residual amplifier in each successive approximation analog-to-digital converter, and is used for outputting a calibration signal to each comparator and each residual amplifier to perform offset and gain calibration.
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