CN113703843A - Register data processing method and device and memory - Google Patents
Register data processing method and device and memory Download PDFInfo
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Abstract
The embodiment of the invention provides a register data processing method, a register data processing device and a memory. And further performing read-write operation on the register according to the register operation information, and sending the read target data to the upper computer, so that the read-write operation on the register data is realized. Compared with the message processed by the register data transmitted by the single channel in the prior art, the invention improves the utilization rate of channel resources by multiplexing the service data and the register operation data, thereby saving the interface resources of the FPGA and avoiding the increase of the development work of an upper computer.
Description
Technical Field
The invention relates to the field of communication, in particular to a register data processing method, a register data processing device and a memory.
Background
Currently, a Field Programmable Gate Array (FPGA) is widely used in various industries, and has the advantages of high Programmable flexibility, short development period, high parallel computing efficiency, and the like.
The internal register function of the FPGA is one of important functions of development and application, is interconnected with other equipment, can effectively obtain real information of the equipment, can also control the function realization of the equipment, and usually realizes the data processing of the register by connecting an upper computer.
In the prior art, an upper computer is usually connected with an FPGA through an independent transmission channel to perform read-write control on register data of the upper computer, but the interface resource of the FPGA can be wasted through the independent channel, and meanwhile, the development work of the upper computer can be increased.
Disclosure of Invention
Embodiments of the present invention provide a register data processing method, a register data processing apparatus, and a memory, so as to solve the problems in the prior art.
In order to achieve the above purpose, the embodiment of the present application adopts the following technical solutions:
in a first aspect, an embodiment of the present invention provides a register data processing method, including:
receiving a first data message sent by an upper computer through a service data channel;
analyzing the first data message to obtain register operation information contained in the first data message;
and performing read-write operation on the register according to the register operation information.
With reference to the first aspect, in a first possible implementation manner, the analyzing the first data packet to obtain register operation information included in the first data packet includes:
and analyzing a first target field of the first data message to obtain the register operation information, wherein the first target field is used for storing the register operation information corresponding to the read-write operation.
With reference to the first aspect, in a second possible implementation manner, the step of performing a read-write operation on the register according to the register operation information includes:
judging the operation type of the register operation information;
if the operation type is reading operation, reading the target data of the register and sending the target data to an upper computer;
and if the operation type is a write operation, writing write data corresponding to the write operation into the register.
With reference to the second possible implementation manner of the first aspect, in a third possible implementation manner, the register operation information further includes an operation address, and the step of reading the target data of the register and sending the target data to the upper computer includes:
when the operation address is a target reading address, reading target data corresponding to the register according to the target reading address;
sending a second data message to the upper computer, wherein a second target field of the second data message stores the target data;
the step of writing the write data corresponding to the write operation into the register includes:
and when the operation address is a target write address, writing the write data into the register according to the target write address.
In a second aspect, an embodiment of the present invention provides another register data processing method, including:
generating a first data message containing register operation information, wherein the register operation information is operation information for performing read-write operation on a register;
and sending the first data message to a register through a service data channel.
With reference to the second aspect, in a first possible implementation manner, the generating a first data packet including register operation information includes:
and generating a first data message containing a first target field according to the register operation information, wherein the first target field is used for storing the register operation information corresponding to the read-write operation.
With reference to the second aspect, in a second possible implementation manner, the method further includes:
receiving a second data message sent by the register through a service data channel, wherein a second target field of the second data message stores target data of the register corresponding to the reading operation;
and analyzing a second target field of the second data message to obtain target data of the register.
In a third aspect, an embodiment of the present invention provides a register data processing apparatus, including:
the receiving module is used for receiving a first data message sent by an upper computer through a service data channel, and the register operation information is operation information for performing read-write operation on a register;
the analysis module is used for analyzing the first data message to obtain register operation information contained in the first data message;
and the processing module is used for performing read-write operation on the register according to the register operation information.
With reference to the third aspect, in a first possible implementation manner, the processing module is further configured to;
judging the operation type of the register operation information;
and sending a second data message to the upper computer, wherein a second target field of the second data message stores target data of the register corresponding to the reading operation.
In a fourth aspect, an embodiment of the present invention provides another register data processing apparatus, including:
the control module is used for generating a first data message containing register operation information, wherein the register operation information is operation information for performing read-write operation on a register;
and the sending module is used for sending the first data message to a register through a service data channel.
With reference to the fourth aspect, in a possible implementation manner, the control module is further configured to:
receiving a second data message sent by the register through a service data channel, wherein a second target field of the second data message is used for storing target data of the register corresponding to the reading operation;
and analyzing a second target field of the second data message to obtain target data of the register.
In a fifth aspect, an embodiment of the present invention provides a memory, where a computer program is stored on the memory, and the computer program, when executed, implements the register data processing method according to any one of the possible implementations of the first aspect or the second aspect.
According to the register data processing method, the device and the memory provided by the embodiment of the invention, after receiving a first data message sent by an upper computer through a service data channel, an FPGA device analyzes the first data message to obtain register operation information contained in the first data message. And further performing read-write operation on the register according to the register operation information, and sending the read target data to the upper computer, so that the read-write operation on the register data is realized. The embodiment of the invention has the beneficial effects that: compared with the message processed by the register data transmitted by the single channel in the prior art, the invention improves the utilization rate of channel resources by multiplexing the service data and the register operation data, thereby saving the interface resources of the FPGA and avoiding the increase of the development work of an upper computer.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 is a schematic diagram of data transmission between an upper computer and an FPGA device in the prior art;
FIG. 2 is a schematic diagram of data transmission between an upper computer and an FPGA device according to the present invention;
FIG. 3 is a flowchart illustrating a register data processing method according to an embodiment of the present invention;
FIG. 4 is a flowchart illustrating another register data processing method according to an embodiment of the present invention;
FIG. 5 is a flowchart illustrating another register data processing method according to an embodiment of the present invention;
FIG. 6 is a flowchart illustrating another register data processing method according to an embodiment of the present invention;
FIG. 7 is a flowchart illustrating another register data processing method according to an embodiment of the present invention;
FIG. 8 is a flowchart illustrating another register data processing method according to an embodiment of the present invention;
FIG. 9 is a flowchart illustrating another register data processing method according to an embodiment of the present invention;
fig. 10 is a schematic signaling interaction diagram of an upper computer and an FPGA device according to an embodiment of the present invention;
FIG. 11 is a functional block diagram of a register data processing apparatus according to an embodiment of the present invention;
fig. 12 is a functional block diagram of another register data processing apparatus according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. indicate an orientation or a positional relationship based on that shown in the drawings or that the product of the present invention is used as it is, this is only for convenience of description and simplification of the description, and it does not indicate or imply that the device or the element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention.
Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
It should be noted that the features of the embodiments of the present invention may be combined with each other without conflict.
Fig. 1 is a diagram of data interaction between an upper computer 10 and an FPGA device 20 in the prior art.
Optionally, the specific type of the upper computer 10 is not limited, and may be set according to the actual application requirement, and may be a computer or a single chip microcomputer that directly sends an operation instruction. For example, in an alternative example, the upper computer 10 may be: desktop computers, smart phones, tablets, notebooks, etc.
Referring to fig. 1, in the prior art: when the service data is processed, the upper computer 10 and the FPGA device 20 are connected by a service data channel, and are used for transmitting relevant messages of service data information to the service data processing unit 21; when processing register data, the upper computer 10 and the FPGA device 20 are usually connected by a separate transmission channel to transmit the relevant message of the register data processing information to the register 22.
For example, when the FPGA is applied to a mass spectrometer, the ion intensity data collected by an Analog-to-digital converter (ADC) is transmitted using a traffic data channel; the register data processing information is transmitted by using a separate transmission channel to realize writing of configuration parameters or control commands into the register or reading of state information (such as scanning exception interrupt information).
However, with the solution shown in fig. 1, when processing register data of the FPGA device 20, an interface needs to be designed separately for the FPGA device 20 because a separate transmission channel is used to connect the upper computer 10. For example, in the prior art, the upper computer 10 performs read-write control and information storage on available Random Access Memory (RAM) resources such as Block Random Access Memory (BRAM) resources or Static Random Access Memory (SRAM) resources inside the FPGA through an individual channel, which wastes interface resources of the FPGA and increases development work of the upper computer 10. Moreover, if the channel for transmitting the read-write control information is a high-speed channel, for example, when a gigabit high-speed port is used, the polled data per second is less than 1kb, which causes waste of high-speed channel resources; if the channel is a low-speed channel, such as a universal asynchronous Receiver/Transmitter (UART), for a scene requiring more polling status information, sometimes the effect of real-time monitoring is not achieved because the timeliness of the low-speed channel is poor.
Therefore, in order to solve the above technical problem, a core solution idea of the register data processing method provided by the present invention is provided, specifically, fig. 2 is a data interaction diagram of the upper computer 10 and the FPGA device 20 in the present invention, and refer to fig. 2:
the upper computer 10 and the FPGA device 20 are connected through a service data channel, and relevant messages of service data information and register operation information are transmitted through the service data channel.
Therefore, channel multiplexing is realized, the utilization rate of channel resources is improved, the interface resources of the FPGA equipment 20 are saved, and the increase of development work of the upper computer 10 is avoided.
It is to be understood that the configurations shown in fig. 1 and 2 are merely exemplary, and that FPGA device 20 may include more or fewer components than those shown in fig. 1 and 2, or have a different configuration, and is not limited herein.
Based on the data interaction diagram of the upper computer 10 and the FPGA device 20 in fig. 2, the embodiment of the present invention provides a possible implementation manner to implement read/write operations on register data, and the following describes an embodiment of the present application by taking the FPGA device 20 as an execution main body, specifically, fig. 3 is a schematic flow diagram of a register data processing method provided in the embodiment of the present invention, and referring to fig. 3, the method includes the steps of:
and step S300, receiving a first data message sent by the upper computer through the service data channel.
It should be noted that, the service data channel is a channel for transmitting data at a high speed, which is commonly used by the FPGA device 20, and the relevant messages of the service data information and the register operation information are all transmitted through the service data channel, and the first data message includes the service data information and/or the register operation information, which may have the following three situations:
case 1: the first data message only contains service data information;
case 2: the first data message only contains register operation information;
case 3: the first data message contains service data information and register operation information.
In an alternative example, the traffic data channel may be a high speed channel. Such as an ethernet channel or a Peripheral Component Interconnect Express (PCIE), i.e., a PCIE high-speed channel. It should be noted that this example is only an example, and the specific implementation manner thereof is not limited herein.
Step S301, the first data message is analyzed, and register operation information contained in the first data message is obtained.
It can be understood that the specific parsing method is not limited, and may be any one of the existing message parsing methods, or when a new or improved protocol is adopted, a parsing scheme meeting the requirements of the protocol may be adopted.
And step S302, performing read-write operation on the register according to the register operation information.
According to the register data processing method provided by the embodiment of the invention, after receiving a first data message sent by an upper computer through a service data channel, the FPGA equipment analyzes the first data message to obtain the register operation information contained in the first data message. And further, reading and writing the register according to the register operation information, so that the reading and writing operation of the register data is realized. The invention improves the utilization rate of channel resources by multiplexing the service data and the register operation data, thereby saving the interface resources of the FPGA and avoiding the increase of the development work of an upper computer.
Accordingly, the register operation information includes an operation type, an operation address, and write data.
With reference to fig. 2, it should be noted that the register 22 may be custom-designed according to requirements, and is formed by designing slice LUTs logic resources inside the FPGA device 20, the number of the register 22 and the bit width of the stored data may be defined according to actual requirements, and the specific design may be implemented by using verilog language programming. The required number of registers is large, the width of data storage bits is large, and the required slice LUTs logical resources are large. Moreover, the portability and the modification flexibility of the custom design register are high, and the custom design register can be transplanted to another device for use after being adaptively modified.
It will be appreciated that the registers 22 include both readable and writable registers and read-only registers. The readable and writable register is characterized by being capable of both read and write operations. The read-only register is characterized in that only reading operation can be carried out on register data, and writing operation cannot be carried out.
It is understood that the data read from the readable and writable register is generally used to determine whether the write data is normally written. Reading the data of the read-only register is typically a query for some information state, such as: the FPGA device 20 is connected with a fan, the upper computer 10 needs to know the working state of the fan, sends a first data message to the FPGA device 20, reads information of a register related to the fan to know the working state of the fan, and feeds back the read information to the upper computer 10. It should be noted that this example is only an example, and the specific implementation manner thereof is not limited herein.
The write operation is generally to perform corresponding signal configuration or function control on the inside, such as: the FPGA device 20 is connected with a digital display tube, the upper computer 10 can send a first data message to the FPGA device 20 to control the digital display tube to display corresponding numbers, or the FPGA device 20 is connected with a switch, and the upper computer 10 can send the first data message to the FPGA device 20 to control the on-off of the switch. It should be noted that this example is only an example, and the specific implementation manner thereof is not limited herein.
Further, in a case that the first data message includes register operation information, in order to obtain the register operation information in the message, with reference to step S301 in fig. 3, a possible implementation manner is provided in the embodiment of the present invention to obtain the register operation information, specifically, on the basis of fig. 3, fig. 4 is a schematic flow diagram of another register data processing method provided in the embodiment of the present invention, referring to fig. 4, and the sub-step of step S301 includes:
step S301-1, a first target field of the first data message is analyzed, and register operation information is obtained.
It will be appreciated that the first target field is used to store register operation information corresponding to read and write operations. Taking a PCIE high-speed channel as an example, for an original service data packet, the first target field may be obtained by multiplexing a self-defined field of the packet, for example, the first target field is some 5 consecutive bytes in the first data packet, where the first byte represents an operation type, and 1 is a write operation, 2 is a read operation, and the others are no operations; the second byte and the third byte represent operation addresses, and the bit width of the operation addresses is 16 bits; the fourth byte and the fifth byte are write data, and the data bit width is 16 bits. It should be noted that this example is only an example, and the specific implementation manner thereof is not limited herein.
Optionally, in a case that the first data message includes register operation information, in order to read data of a register or write data into the register, with reference to step S302 in fig. 3, an embodiment of the present invention provides a possible implementation manner to implement reading and writing of register data, specifically, on the basis of fig. 3, fig. 5 is a flowchart of another register data processing method provided by the embodiment of the present invention, and referring to fig. 5, the sub-step of step S302 includes:
and step S302-1, judging the operation type of the register operation information.
And S302-2, if the operation type is a reading operation, reading the target data of the register and sending the target data to the upper computer.
In one possible implementation, when the operation type is a read operation, the write data of the register operation information is ignored, and the write data portion of the first target field is filled with all 0's.
Step S302-3, if the operation type is a write operation, writing write data corresponding to the write operation into a register.
It is to be understood that when the operation type is no operation, no operation is performed on the register data.
Optionally, in order to read target data of a register corresponding to an operation address or write data into a register corresponding to the operation address, with reference to step S302-2 and step S302-3 in fig. 5, an embodiment of the present invention provides a possible implementation manner to achieve the above object, specifically, on the basis of fig. 5, fig. 6 is a flowchart of another register data processing method provided by the embodiment of the present invention, and referring to fig. 6, sub-steps of step S302-2 include:
and S302-21, when the operation address is the target reading address, reading the target data corresponding to the register according to the target reading address.
And S302-22, sending a second data message to the upper computer.
And the second target field of the second data message is used for storing target data.
Taking the PCIE highway as an example, for the original service data packet, the second target field may be obtained by multiplexing the custom field of the packet, for example, multiplexing the first byte and the second byte of the custom field as the second target field to store the target data. It should be noted that this example is only an example, and the specific implementation manner thereof is not limited herein.
The substep of step S302-3, comprising:
and step S302-31, writing the write data into the register according to the target write address when the operation address is the target write address.
It is understood that the operation address has two types of target read address and target write address. When the operation type is a read operation, the operation address is a target read address, and when the operation type is a write operation, the operation address is a target write address.
According to the register data processing method provided by the embodiment of the invention, after receiving a first data message sent by an upper computer through a service data channel, the FPGA equipment analyzes the first data message to obtain the register operation information contained in the first data message. And further performing read-write operation on the register according to the register operation information, and sending the read target data to the upper computer, so that the read-write operation on the register data is realized. Compared with the message processed by the register data transmitted by the single channel in the prior art, the invention improves the utilization rate of channel resources by multiplexing the service data and the register operation data, thereby saving the interface resources of the FPGA and avoiding the increase of the development work of an upper computer.
With reference to the above, the method of execution of the upper computer 10 in fig. 2 is described below. The present invention provides a possible implementation manner to implement that the upper computer 10 controls the register to perform read/write operations, specifically, fig. 7 is a schematic flow diagram of another register data processing method provided in an embodiment of the present invention, and referring to fig. 7, the method includes the steps of:
step S400, a first data packet including register operation information is generated.
It is understood that the register operation information is operation information for performing read and write operations on the register.
Step S401, send the first data packet to the register 22 through the service data channel.
According to the register data processing method provided by the embodiment of the invention, after the upper computer generates the first data message containing the register operation information, the first data message is sent to the register through the service data channel, so that the upper computer controls the register to perform read-write operation. Compared with the message processed by the register data transmitted by the single channel in the prior art, the invention improves the utilization rate of channel resources by multiplexing the service data and the register operation data, thereby saving the interface resources of the FPGA and avoiding the increase of the development work of an upper computer.
Further, in order to put the register operation information into a certain field of the first data packet, with respect to step S400 in fig. 7, a possible implementation manner is provided in the embodiment of the present invention, specifically, on the basis of fig. 7, fig. 8 is a flowchart of another register data processing method provided in the embodiment of the present invention, referring to fig. 8, and the sub-step of step S400 includes:
step S400-1, generating a first data message containing a first target field according to the register operation information.
It is to be understood that the first target field is for storing register operation information corresponding to read and write operations.
Further, in order to obtain target data of the read register, the embodiment of the present invention provides a possible implementation manner, specifically, on the basis of fig. 7, fig. 9 is a flowchart of another register data processing method provided in the embodiment of the present invention, and referring to fig. 9, after step S401, the steps further include:
and step S402, receiving a second data message sent by the register through the service data channel.
It will be appreciated that the second destination field of the second data packet stores destination data for a register corresponding to a read operation.
Step S403, analyzing the second target field of the second data packet to obtain the target data of the register.
According to the register data processing method provided by the embodiment of the invention, after the upper computer generates the first data message containing the register operation information, the first data message is sent to the register through the service data channel, and the read target data of the register is received, so that the upper computer controls the register to perform read-write operation. Compared with the message processed by the register data transmitted by the single channel in the prior art, the invention improves the utilization rate of channel resources by multiplexing the service data and the register operation data, thereby saving the interface resources of the FPGA and avoiding the increase of the development work of an upper computer.
Optionally, in order to better explain an implementation manner of the present application, in combination with the foregoing method flows executed by the upper computer 10 and the FPGA device 20, taking read-write control of register data of the FPGA device 20 by the upper computer 10 in fig. 2 as an example, an interaction implementation manner between the upper computer 10 and the FPGA device 20 is provided below, specifically, fig. 10 is a signaling interaction schematic diagram of the upper computer 10 and the FPGA device 20, and referring to fig. 10, the flow includes:
step 2, the upper computer sends a first data message to the FPGA device;
step 3, the FPGA equipment analyzes a first target field of the first data message to obtain register operation information;
step 4, the FPGA equipment determines the operation type of the register operation information;
step 5, if the operation is a reading operation, searching a target reading address, reading target data, generating a second data message according to the target data and sending the second data message to an upper computer; the upper computer analyzes a second target field of the second data message to obtain target data;
and 6, if the operation is a write-in operation, searching a target write-in address, and writing write-in data into a register.
With reference to fig. 11, an embodiment of the present invention further provides a register data processing apparatus 500, which can be applied to the FPGA device 20. It should be noted that the basic principle and the technical effect are the same as those of the corresponding method embodiments, and for the sake of brief description, the corresponding contents in the method embodiments may be referred to for the parts not mentioned in this embodiment. The register data processing apparatus may include a receiving module 510, a parsing module 520, and a processing module 530.
The receiving module 510 is configured to receive a first data packet sent by an upper computer through a service data channel.
In this embodiment, the receiving module 510 may be configured to execute step S300 shown in fig. 3.
The parsing module 520 is configured to parse the first data packet to obtain register operation information included in the first data packet.
In this embodiment, the parsing module 520 may be configured to perform step S301 shown in fig. 3, and for the relevant content of the parsing module 520, reference may be made to the foregoing detailed description of step S301.
And the processing module 530 is configured to perform read/write operations on the register according to the register operation information.
In this embodiment, the processing module 530 may be configured to execute step S302 shown in fig. 3, and reference may be made to the foregoing detailed description of step S302 regarding the relevant content of the parsing module.
Further, the processing module 530 of the register data processing apparatus 500 is further configured to:
judging the operation type of the register operation information;
and sending a second data message to the upper computer.
Wherein a second target field of the second data packet stores target data of a register corresponding to the read operation.
With reference to fig. 12, another register data processing apparatus 600 is provided in the embodiment of the present invention, which can be applied to the upper computer 10. It should be noted that the basic principle and the technical effect are the same as those of the corresponding method embodiments, and for the sake of brief description, the corresponding contents in the method embodiments may be referred to for the parts not mentioned in this embodiment. The register data processing apparatus may include a control module 610 and a transmitting module 620.
The control module 610 is configured to generate a first data packet including register operation information.
The register operation information is operation information for performing read-write operation on the register.
The sending module 620 is configured to send the first data packet to the register through the service data channel.
Further, the control module 610 of the register data processing apparatus 600 is further configured to:
receiving a second data message sent by the register through a service data channel;
and analyzing a second target field of the second data message to obtain target data of the register.
The second target field of the second data packet is used for storing target data of a register corresponding to the read operation.
The above-mentioned apparatus is used for executing the method provided by the foregoing embodiment, and the implementation principle and technical effect are similar, which are not described herein again.
These above modules may be one or more integrated circuits configured to implement the above methods, such as: one or more Application Specific Integrated Circuits (ASICs), or one or more microprocessors (DSPs), or one or more Field Programmable Gate Arrays (FPGAs), among others. For another example, when one of the above modules is implemented in the form of a Processing element scheduler code, the Processing element may be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. For another example, these modules may be integrated together and implemented in the form of a System-on-a-Chip (SoC).
Further, based on the above register data processing method, in the embodiment of the present application, a memory is further provided, on which a computer program is stored, and the computer program is executed when being executed by a processor, so as to implement the above method embodiment.
Optionally, when the memory is disposed in the FPGA device in the above embodiment, it may be used to store the program corresponding to the corresponding method flow in fig. 3 to fig. 6, so as to achieve the corresponding effect. When the memory is disposed in the upper computer in the above embodiment, it can be used to store the program corresponding to the corresponding method flow of fig. 7 to 9, so as to achieve the corresponding effect.
In summary, the register data processing method, apparatus and memory provided in the embodiments of the present invention can perform read-write control on register data through an upper computer, and the method includes: after receiving a first data message sent by an upper computer through a service data channel, the FPGA equipment analyzes the first data message to obtain register operation information contained in the first data message. And further, reading and writing the register according to the register operation information, so that the reading and writing operation of the register data is realized. Compared with the message processed by the register data transmitted by the single channel in the prior art, the invention improves the utilization rate of channel resources by multiplexing the service data and the register operation data, thereby saving the interface resources of the FPGA and avoiding the increase of the development work of an upper computer.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (12)
1. A register data processing method, comprising:
receiving a first data message sent by an upper computer through a service data channel;
analyzing the first data message to obtain register operation information contained in the first data message;
and performing read-write operation on the register according to the register operation information.
2. The method of claim 1, wherein the parsing the first datagram to obtain register operation information included in the first datagram comprises:
and analyzing a first target field of the first data message to obtain the register operation information, wherein the first target field is used for storing the register operation information corresponding to the read-write operation.
3. The method of claim 1, wherein said step of reading from and writing to a register based on said register operation information comprises:
judging the operation type of the register operation information;
if the operation type is reading operation, reading the target data of the register and sending the target data to an upper computer;
and if the operation type is a write operation, writing write data corresponding to the write operation into the register.
4. The method of claim 3, wherein the register operation information further includes an operation address, and the step of reading the target data of the register and transmitting the target data to the upper computer comprises:
when the operation address is a target reading address, reading target data corresponding to the register according to the target reading address;
sending a second data message to the upper computer, wherein a second target field of the second data message stores the target data;
the step of writing the write data corresponding to the write operation into the register includes:
and when the operation address is a target write address, writing the write data into the register according to the target write address.
5. A register data processing method, comprising:
generating a first data message containing register operation information, wherein the register operation information is operation information for performing read-write operation on a register;
and sending the first data message to a register through a service data channel.
6. The method of claim 5, wherein generating the first data packet containing register operation information comprises:
and generating a first data message containing a first target field according to the register operation information, wherein the first target field is used for storing the register operation information corresponding to the read-write operation.
7. The method of claim 5, wherein the method further comprises:
receiving a second data message sent by the register through a service data channel, wherein a second target field of the second data message is used for storing target data of the register corresponding to the reading operation;
and analyzing a second target field of the second data message to obtain target data of the register.
8. A register data processing apparatus, comprising:
the receiving module is used for receiving a first data message sent by an upper computer through a service data channel, and the register operation information is operation information for performing read-write operation on a register;
the analysis module is used for analyzing the first data message to obtain register operation information contained in the first data message;
and the processing module is used for performing read-write operation on the register according to the register operation information.
9. The apparatus of claim 8, wherein the processing module is further to;
judging the operation type of the register operation information;
and sending a second data message to the upper computer, wherein a second target field of the second data message stores target data of the register corresponding to the reading operation.
10. A register data processing apparatus, comprising:
the control module is used for generating a first data message containing register operation information, wherein the register operation information is operation information for performing read-write operation on a register;
and the sending module is used for sending the first data message to a register through a service data channel.
11. The apparatus of claim 10, wherein the control module is further to:
receiving a second data message sent by the register through a service data channel, wherein a second target field of the second data message is used for storing target data of the register corresponding to the reading operation;
and analyzing a second target field of the second data message to obtain target data of the register.
12. A memory having stored thereon a computer program which, when executed, implements the register data processing method of any of the preceding method claims 1 to 4 or the register data processing method of any of the 5-7 claims.
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