CN113675104A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN113675104A CN113675104A CN202110949049.1A CN202110949049A CN113675104A CN 113675104 A CN113675104 A CN 113675104A CN 202110949049 A CN202110949049 A CN 202110949049A CN 113675104 A CN113675104 A CN 113675104A
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- 229910045601 alloy Inorganic materials 0.000 claims abstract description 33
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- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 44
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 33
- 229910052802 copper Inorganic materials 0.000 claims description 33
- 239000010949 copper Substances 0.000 claims description 33
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- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 claims description 8
- 238000000678 plasma activation Methods 0.000 claims description 6
- 230000003746 surface roughness Effects 0.000 claims description 4
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- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4827—Materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
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- Materials Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A method of forming a semiconductor structure, comprising: providing a first substrate, wherein the first substrate is provided with a first side and a second side which are opposite; forming a first dielectric layer on the first surface of the first substrate, wherein the first dielectric layer is internally provided with a first opening; forming a first conductive layer in the first opening, wherein the surface of the first conductive layer is lower than the top surface of the first dielectric layer; forming a second conductive layer on the surface of the first conductive layer, wherein the second conductive layer is made of a different material from the first conductive layer; providing a second substrate, wherein the second substrate is provided with a third surface and a fourth surface which are opposite, a second dielectric layer is formed on the third surface, a conductive structure is arranged in the second dielectric layer, and the surface of the second dielectric layer is exposed out of the conductive structure; and bonding the first surface of the first substrate towards the third surface of the second substrate to fix the first dielectric layer and the second dielectric layer and form an alloy layer between the first conductive layer and the conductive structure. The formed semiconductor structure has high electrical stability and good process flexibility.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof in a three-dimensional packaging technology.
Background
In recent years, the semiconductor industry has been increasingly demanding on device packing density and circuit performance. Among them, the three-dimensional packaging technology is widely used in the manufacture of various integrated circuits because of its technical requirements of high performance, low power consumption and high integration density.
In the three-dimensional packaging technology, bonding is a key technology for realizing vertical stacking of multilayer chip interconnects. The hybrid bonding technology combines metal-metal bonding and dielectric-dielectric bonding, can effectively realize chip interconnection stacking, and simultaneously ensures reliable mechanical property and electrical property of devices, and is the bonding technology with the most potential at present.
Among them, copper-copper thermocompression bonding has wide application in the manufacture of three-dimensional integrated circuits. In this bonding process, the bonding temperature is an important parameter that affects the bonding effect and device performance. However, the process temperature in the existing thermocompression bonding technology is too high, thereby damaging sensitive devices in the circuit, and simultaneously damaging adhesive glue of other processes, thereby causing poor device performance.
Disclosure of Invention
The invention solves the technical problems that the process temperature in the existing hot-press bonding technology is too high, thereby destroying sensitive devices in a circuit, and simultaneously damaging adhesive glue of other processes, thereby causing poor device performance.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a first substrate having first and second opposing faces; forming a first dielectric layer on a first surface of a first substrate, wherein the first dielectric layer is internally provided with a first opening; forming a first conductive layer in the first opening, wherein the surface of the first conductive layer is lower than the top surface of the first dielectric layer; forming a second conductive layer on the surface of the first conductive layer, wherein the second conductive layer is made of a different material from the first conductive layer; providing a second substrate, wherein the second substrate is provided with a third surface and a fourth surface which are opposite, a second dielectric layer is formed on the third surface, a conductive structure is arranged in the second dielectric layer, and the surface of the second dielectric layer is exposed out of the conductive structure; and bonding the first surface of the first substrate towards the third surface of the second substrate to fix the first dielectric layer and the second dielectric layer and form an alloy layer between the first conductive layer and the conductive structure.
Optionally, the material of the first conductive layer includes copper; the material of the conductive structure comprises copper.
Optionally, a forming process of the first conductive layer is a chemical plating process; the forming process of the conductive structure is a chemical plating process.
Optionally, in the chemical plating process for forming the first conductive layer, a plating solution including a copper sulfate solution and an additive is used; in the chemical plating process for forming the conductive structure, the used electroplating solution is a copper sulfate solution and an additive.
Optionally, the material of the second conductive layer includes nickel.
Optionally, the forming method of the second conductive layer includes: forming an initial second conductive layer on the surface of the first conductive layer; and flattening the initial second conductive layer until the surface of the first dielectric layer is exposed to form a second conductive layer.
Optionally, the forming process of the initial second conductive layer is a physical vapor deposition process.
Optionally, the thickness of the second conductive layer is 50 angstroms to 300 angstroms.
Optionally, the forming process of the initial second conductive layer is a chemical plating process.
Optionally, the thickness of the second conductive layer is 30 angstroms to 3 microns.
Optionally, the surface roughness of the second conductive layer is less than 3 nm.
Optionally, the conductive structure includes a third conductive layer and a fourth conductive layer on the third conductive layer, where a material of the third conductive layer includes copper, and a material of the fourth conductive layer includes nickel.
Optionally, performing surface treatment on the surface of the first dielectric layer, where the surface treatment process includes a plasma activation process; and carrying out surface treatment on the surface of the second dielectric layer, wherein the surface treatment process comprises a plasma activation process.
Optionally, the heating temperature range adopted in the bonding process is 130 to 150 ℃.
Optionally, the heating temperature range adopted in the bonding process is 130 to 200 ℃.
Accordingly, the present invention also provides a semiconductor structure formed by any one of the above methods, comprising: a first substrate having opposing first and second sides; the first dielectric layer is positioned on the first surface of the first substrate and is internally provided with a first opening; the first conducting layer is positioned in the first opening, and the surface of the first conducting layer is lower than the top surface of the first dielectric layer; a second substrate bonded to the first substrate, the second substrate having third and fourth opposing faces; a second dielectric layer on the third face; the conductive structure is positioned in the second dielectric layer, and the surface of the conductive structure is lower than the surface of the second dielectric layer; an alloy layer between the first conductive layer and the conductive structure.
Optionally, the material of the first conductive layer includes copper; the material of the conductive structure comprises copper.
Optionally, the material of the alloy layer includes a copper-nickel alloy.
Optionally, the conductive structure includes a third conductive layer and a fourth conductive layer on the third conductive layer, where a material of the third conductive layer includes copper, and a material of the fourth conductive layer includes nickel.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming a semiconductor structure of the present invention, a second conductive layer is formed on the surface of the first conductive layer, and the second conductive layer is formed of a different material from the first conductive layer. In the subsequent bonding process, the second conductive layer is used as a bonding interface and is attached and fixed with the surface of the conductive structure to form a bonding structure. By selecting a proper second conductive layer material, an alloy layer can be formed on the surfaces of the second conductive layer and the conductive structure in the bonding process, the bonding process temperature is reduced, and the bonding strength of a bonding interface is enhanced, so that the device performance is improved, the effectiveness of the adhesive process is ensured, and the process flexibility is enlarged.
Further, the material of the second conductive layer includes nickel, and the material of the conductive structure includes copper. Because the metal diffusion strength between the nickel and the copper is high, and the nickel and the copper can generate the copper-nickel alloy at a lower temperature, the second conducting layer and the surface of the conducting structure can be bonded at 130-150 ℃ in the bonding process, so that the process temperature is greatly reduced. Meanwhile, the bonding interface is formed by the copper-nickel alloy, so that the bonding strength of the bonding interface is enhanced.
Further, the surface roughness of the second conductive layer formed by adopting a physical vapor deposition process after planarization is less than 3 nanometers. The flatness of the second conducting layer is good, so that the attaching degree of a bonding interface is enhanced, and bonding is more sufficient.
Drawings
FIGS. 1 to 3 are schematic cross-sectional views illustrating an embodiment of a process for forming a semiconductor bonding structure;
fig. 4 to 11 are schematic cross-sectional views illustrating a process of forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As described in the background art, the process temperature in the existing thermocompression bonding technology is too high, thereby destroying the sensitive devices in the circuit, and simultaneously damaging the adhesive glue of other processes, resulting in poor device performance.
Fig. 1 to 3 are schematic cross-sectional views illustrating an embodiment of a process for forming a semiconductor bonding structure.
Referring to fig. 1, a first substrate 100 is provided, the first substrate 100 having a first side and a second side opposite to each other; forming a first dielectric layer 101 on a first side of the first substrate 100; a first conductive structure 102 is formed in the first dielectric layer 101, and the material of the first conductive structure 102 includes copper.
Referring to fig. 2, a second substrate 200 is provided, the second substrate 200 having a third surface and a fourth surface opposite to each other; forming a second dielectric layer 201 on a third surface of the second substrate 200; and forming a second conductive structure 202 in the second dielectric layer 201, wherein the material of the second conductive structure 202 comprises copper.
Referring to fig. 3, the first conductive structure 102 is planarized, and the second conductive structure 202 is planarized; and bonding the first surface of the first substrate 100 after planarization towards the third surface of the second substrate 200 after planarization, so that the first dielectric layer 101 and the second dielectric layer 201 are fixed, and the surface of the first conductive structure 102 and the surface of the second conductive structure 202 are fixed.
Wherein the material of the first and second conductive structures 102 and 202 comprises copper; the formation process of the first conductive structure 102 and the second conductive structure 202 is an electroless plating process, and the plating solution used is a copper sulfate solution with an additive. Due to the limited diffusion strength between copper and copper, the bonding process of the first conductive structure 102 and the second conductive structure 202 needs to be performed at a high temperature of 350-400 ℃, which seriously damages sensitive devices and damages adhesive of other processes, resulting in poor device performance.
In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, including:
and sequentially forming a first conductive layer and a second conductive layer in the first dielectric layer to fill the opening, wherein the second conductive layer is made of a different material from the first conductive layer. Related technicians can select a proper second conductive layer material, so that the process of bonding the second conductive layer and the surface of the conductive structure can be carried out at a lower temperature, and meanwhile, the bonding strength of a bonding interface is enhanced, thereby improving the performance of the device and expanding the process flexibility.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 11 are schematic cross-sectional views illustrating a process of forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 4, a first substrate 300 is provided, the first substrate 300 having a first side 3001 and a second side 3002 opposite to each other.
The first side 3001 of the first substrate 300 provides a platform for subsequent processing. The constituent material of the first substrate 300 includes silicon, silicon germanium, silicon carbide, silicon-on-insulator (SOI), germanium-on-insulator (GOI), and the like.
In this embodiment, a first dielectric layer formed subsequently is located on the surface of the first surface 3001, and a first conductive layer formed subsequently is electrically connected to the first substrate 300.
In another embodiment, the first substrate further includes a device layer on the first side, and a subsequently formed first dielectric layer is on the device layer, the device layer including: an active device or a passive device; a dielectric layer located on the active device or the passive device; a conductive structure located within the dielectric layer; the subsequently formed first conductive layer is electrically connected to the active device or the passive device.
Referring to fig. 5, a first dielectric layer 310 is formed on a first side 3001 of a first substrate 300, wherein the first dielectric layer 310 has a first opening 301 therein.
The surface of the first dielectric layer 310 serves as a bonding interface in subsequent bonding, and the surface of the first dielectric layer 310 is fixed with the surface of a subsequently formed second dielectric layer, so that dielectric bonding is formed. The first opening 301 is used for subsequent deposition of a first conductive layer and a second conductive layer.
In this embodiment, the first opening 301 includes: the structure comprises a first groove 302 and a second groove 303 positioned at the bottom of the first groove 302, wherein the projection pattern of the second groove 303 on the top surface of a first dielectric layer 310 is positioned inside the projection pattern of the first groove 302 on the top surface of the first dielectric layer 310, and the first groove 302 is communicated with the second groove 303.
The forming step of the first dielectric layer 301 comprises: forming a first dielectric film (not shown) on a first surface of the first substrate 300; and forming a first opening 301 in the first dielectric film to form the first dielectric layer 310.
The forming step of the first opening 301 includes: forming a first photoresist pattern layer (not shown) on the surface of the first dielectric film; etching the first dielectric film by taking the first photoresist pattern layer as a mask to form a first groove 302; forming a second photoresist pattern layer (not shown) on the surface of the first dielectric film and in the first trench 302, wherein the second photoresist pattern layer exposes a part of the bottom of the first trench 302; and etching the first dielectric film by using the second photoresist pattern layer as a mask, and forming a second groove 303 at the bottom of the first groove 302, wherein the second groove 303 exposes the surface of the first substrate 300.
The material of the first dielectric film comprises silicon oxide, silicon nitride or other insulating materials; the first dielectric film is formed by chemical vapor deposition or physical vapor deposition.
The forming step of the first photoresist pattern layer includes: and forming a photoresist film on the surface of the first dielectric film by adopting a coating process, and exposing and developing to form a first photoresist pattern layer with a first groove 302 pattern. The forming step of the second photoresist pattern layer includes: and forming photoresist films on the surface of the first dielectric film and the bottom surface of the first groove 302 by adopting a coating process, and exposing and developing to form a second photoresist pattern layer with a second groove 303 pattern.
In this embodiment, the process of etching the first dielectric film is an anisotropic dry etching process, and the etching direction is perpendicular to the surface of the first substrate 300 until the first trench 302 and the second trench 303 are formed, so as to form the first opening 301.
In this embodiment, after the first opening 301 is formed, the first photoresist pattern layer and the second photoresist pattern layer are removed by an ashing process.
In other embodiments, the projected pattern of the second trench 303 on the top surface of the first dielectric layer 310 coincides with the projected pattern of the first trench 302 on the top surface of the first dielectric layer 310.
With reference to fig. 5, a first dielectric barrier layer 311 is formed on the surface of the first opening 301.
The first dielectric barrier layer 311 is used to prevent the metal in the subsequently formed first conductive layer from diffusing into the first dielectric layer 310.
In this embodiment, the first dielectric barrier layer 311 is made of Nitride Doped Silicon Carbide (NDC); the thickness of the first dielectric barrier layer 311 is 50 angstroms to 250 angstroms; the forming process of the first dielectric barrier layer 311 includes chemical vapor deposition or atomic layer deposition.
Referring to fig. 6, a first seed layer 312 is formed on the first dielectric barrier layer 311.
The material of the first seed layer 312 is copper; the first seed layer 312 is formed by chemical vapor deposition or atomic layer deposition. Because the process has excellent consistency, the formed first seed layer 312 has good continuity and no structural defects such as pinholes, voids, etc., and is an important basis for the subsequent formation of a uniform and continuous first conductive layer 320.
With reference to fig. 6, a first conductive layer 320 is formed in the first opening 301, the first conductive layer 320 is located on the first seed layer 312, and the surface of the first conductive layer 320 is lower than the top surface of the first dielectric layer 310.
In this embodiment, the material of the first conductive layer 320 includes copper. The formation process of the first conductive layer 320 is an electroless plating process in which a plating solution including a copper sulfate solution and an additive is used. During filling of the first opening 301, additives in the plating solution may help maintain a uniform deposition rate at the top and bottom of the first opening 301, thereby forming a uniform and continuous first conductive layer 320 within the first opening 301.
The top of the first conductive layer 320 is lower than the top of the first dielectric layer 310, and the gap distance W from the top surface of the first conductive layer 320 to the top surface of the first dielectric layer 310 ranges from 30 angstroms to 3 microns, and provides a space for a subsequently formed second conductive layer.
Specifically, the gap distance W is related to a formation process of a second conductive layer to be formed later. In this embodiment, the subsequent process of forming the second conductive layer is a physical vapor deposition process, and the gap distance W ranges from 50 angstroms to 300 angstroms. In another embodiment, the subsequent process for forming the second conductive layer is an electroless plating process, and the gap distance W is in a range of 30 angstroms to 3 microns. By controlling the electroless plating time of the first conductive layer 320, the gap distance W of the top surface of the first conductive layer 320 from the top surface of the first dielectric layer 310 can be controlled.
In this embodiment, a second conductive layer is formed on the surface of the first conductive layer 320, and the second conductive layer is made of a different material from the first conductive layer 320. The second conductive layer is located in the space between the top of the first conductive layer 320 and the top of the first dielectric layer 310 to fill the first opening 301 (as shown in fig. 5). Please refer to fig. 7 to 8 for a process of forming the second conductive layer.
Referring to fig. 7, an initial second conductive layer 3301 is formed on the surface of the first conductive layer 320.
In this embodiment, the forming process of the initial second conductive layer 3301 is a physical vapor deposition process. The physical vapor deposition process has excellent uniformity, and the crystal grain arrangement of the deposition product can be well controlled, so that the crystal phase arrangement of the surface of the subsequently formed second conductive layer is uniform, the surface smoothness of the second conductive layer is optimized, the interface joint degree in the subsequent bonding process is further improved, and the bonding is more sufficient.
In another embodiment, the forming process of the initial second conductive layer is an electroless plating process, and an electroplating solution used in the electroless plating process includes nickel sulfate, nickel chloride, boric acid, and an additive. Because the forming process of the initial second conducting layer and the forming process of the first conducting layer are both chemical plating processes, process equipment does not need to be replaced, and the process cost and the operation difficulty are reduced.
Referring to fig. 8, the initial second conductive layer 3301 is planarized until the surface of the first dielectric layer 310 is exposed, forming a second conductive layer 330.
In this embodiment, the planarizing includes: and removing the redundant first dielectric barrier layer 311, the first seed layer 312, the first conductive layer 320 and the initial second conductive layer 3301 on the surface of the first dielectric layer 310 until the surface of the first dielectric layer 310 is exposed.
In this embodiment, the planarization process is a chemical mechanical polishing process.
In this embodiment, the forming process of the initial second conductive layer 3301 is a physical vapor deposition process, the thickness of the second conductive layer 330 formed after planarization is 50 angstroms to 300 angstroms, and the surface roughness of the second conductive layer 330 formed after planarization is less than 3 nanometers.
In another embodiment, the forming process of the initial second conductive layer is an electroless plating process, and the thickness of the second conductive layer formed after planarization is 30 angstroms to 3 microns.
In this embodiment, the material of the second conductive layer 330 includes nickel. In the subsequent bonding process, the surface of the second conductive layer 330 and the surface of the subsequently formed conductive structure are fixed to each other as a bonding interface. Since the nickel diffusion strength of the surface of the second conductive layer 330 is high, the bonding strength between the surface of the second conductive layer 330 and the surface of the conductive structure formed later in the bonding process is high. In addition, the surface of the second conductive layer 330 is in contact with the surface of the first conductive layer 320 and the surface of the conductive structure to be formed subsequently, and the second conductive layer 330 provides a raw material for forming an alloy layer between the first conductive layer 320 and the conductive structure subsequently.
Referring to fig. 9, a second substrate 400 is provided, where the second substrate 400 has a third surface and a fourth surface opposite to each other, a second dielectric layer 410 is formed on the third surface, a conductive structure 440 is disposed in the second dielectric layer 410, and the conductive structure 440 is exposed on a surface of the second dielectric layer 410.
The third side of the second substrate 400 provides a platform for subsequent processes.
In this embodiment, the method further includes: forming a second opening (not shown) in the second dielectric layer 410; forming a second dielectric barrier layer 411 on the sidewall surface and the bottom surface of the second opening; a second seed layer 412 is formed on the surface of the second dielectric barrier layer 411, and the second seed layer 412 is used as a base for the deposition of the subsequent conductive structure 440.
The constituent material of the second substrate 400 includes silicon, silicon germanium, silicon carbide, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like; the material of the second dielectric layer 410 includes silicon oxide, silicon nitride or other insulating materials; the material of the second dielectric barrier layer 411 includes nitrogen-Doped Silicon Carbide (NDC); the material of the second seed layer 412 includes copper.
In this embodiment, the material of the conductive structure 440 includes copper; the forming process of the conductive structure 440 comprises an electroless plating process; in the chemical plating process, the plating solution used comprises a copper sulfate solution and an additive. After the conductive structure 440 is formed, the conductive structure 440 is planarized until the top surface of the second dielectric layer 410 is exposed.
During subsequent bonding, the surface of the second conductive layer 330 (shown in fig. 8) and the surface of the conductive structure 440 act as a bonding interface. The nickel on the surface of the second conductive layer 330 and the copper on the surface of the conductive structure 440 have strong metal diffusion with each other, and at the same time, a copper-nickel alloy layer is subsequently formed between the first conductive layer 320 (as shown in fig. 8) and the conductive structure 440, so that the bonding strength is higher, and the process temperature required for bonding is reduced.
In another embodiment, the conductive structure includes a third conductive layer and a fourth conductive layer on the third conductive layer.
The forming of the third conductive layer and the fourth conductive layer includes: forming the third conducting layer in the second dielectric layer, wherein the third conducting layer is lower than the top surface of the second dielectric layer; forming a fourth conductive layer on the surface of the third conductive layer; and flattening the fourth conducting layer until the top surface of the second dielectric layer is exposed.
The material of the third conductive layer comprises copper; the forming process of the third conducting layer is a chemical plating process; in the electroless plating process for forming the third conductive layer, a plating solution including a copper sulfate solution and an additive is used. The material of the fourth conductive layer comprises nickel; the forming process of the fourth conducting layer comprises a physical vapor deposition process, a chemical plating process and the like; when the process of forming the fourth conductive layer is an electroless plating process, a plating solution including nickel sulfate, nickel chloride, boric acid, and an additive is used.
In the subsequent bonding process, the surface of the second conductive layer 330 and the surface of the fourth conductive layer are used as bonding interfaces and fixed to each other. The nickel on the surface of the second conductive layer 330 and the nickel on the surface of the fourth conductive layer have strong metal diffusion, and a copper-nickel alloy layer is formed between the first conductive layer 320 and the third conductive layer, so that the bonding strength is higher, and the process temperature required by bonding is reduced.
In this embodiment, the first surface of the first substrate 300 is bonded to the third surface of the second substrate 400, so that the first dielectric layer 310 and the second dielectric layer 410 are fixed, the surface of the second conductive layer 330 and the surface of the conductive structure 440 are fixed, and an alloy layer is formed between the first conductive layer 320 and the conductive structure 440. Please refer to fig. 10 to fig. 11 for the bonding process.
Referring to fig. 10, a surface treatment is performed on the surface of the first dielectric layer 310; performing surface treatment on the surface of the second dielectric layer 410; and attaching the first surface of the first substrate 300 to the third surface of the second substrate 400, and pressing, so that the surface of the first dielectric layer 310 on the first substrate 300 and the surface of the second dielectric layer 410 on the second substrate 400 are combined through van der waals force, and dielectric bonding is formed.
In this embodiment, the process of performing the surface treatment on the surface of the first dielectric layer includes a plasma activation process, and the gas used in the process includes nitrogen; the process for performing surface treatment on the surface of the second dielectric layer comprises a plasma activation process, wherein the gas adopted in the process comprises nitrogen.
Referring to fig. 11, an alloy layer 340 is formed between the first conductive layer 320 in the first dielectric layer 310 and the conductive structure 440 in the second dielectric layer 410 by a heating process, thereby completing the bonding.
In this embodiment, the forming step of the alloy layer 340 includes: in the heating process, a first initial alloy layer (not shown) is formed at the interface of the second conductive layer 330 and the conductive structure 440, while a second initial alloy layer (not shown) is formed at the interface of the first conductive layer 320 and the second conductive layer 330; an alloy layer 340 is formed between the first conductive layer 320 and the conductive structure 440 by metal diffusion between the first preliminary alloy layer and the second preliminary alloy layer.
In this embodiment, the alloy layer 340 is made of a copper-nickel alloy. During the bonding process, there are strong metal diffusion effects between the nickel on the surface of the second conductive layer 330 and the copper on the surface of the conductive structure 440, and between the copper on the surface of the first conductive layer 320 and the nickel on the surface of the second conductive layer 330. Meanwhile, since copper and nickel can form a copper-nickel alloy at a lower temperature, the temperature required for forming the alloy layer 340 between the first conductive layer 320 and the conductive structure 440 is lower, thereby reducing the process temperature required for bonding, protecting the adhesive of other processes from being damaged, and expanding the process flexibility. In addition, the copper-nickel alloy has compact structure, high strength and good chemical stability, so that the bonding strength of a bonding interface is further improved, the bonding effect is optimized, and the electrical performance of the device is improved.
In this embodiment, the forming process of the second conductive layer 330 is a physical vapor deposition process, and the heating temperature range adopted in the bonding process is 130-150 ℃.
In another embodiment, the forming process of the second conductive layer is an electroless plating process, and the heating temperature range adopted in the bonding process is also between 130 ℃ and 150 ℃.
In other embodiments, the conductive structure includes a third conductive layer and a fourth conductive layer on the third conductive layer; the material of the third conductive layer comprises copper, and the material of the fourth conductive layer comprises nickel. The bonding step is the same as in the above embodiment and will not be repeated here. The heating temperature adopted in the bonding process is lower than 400 ℃. Because the nickel on the surface of the second conductive layer has a strong diffusion effect with the nickel on the surface of the fourth conductive layer, and a copper-nickel alloy layer is formed between the first conductive layer 320 and the third conductive layer, the process temperature required by bonding is reduced, the bonding strength of a bonding interface is improved, and the electrical performance of the device is optimized.
Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, with reference to fig. 11, including:
a first substrate 300, the first substrate 300 having opposing first and second faces;
a first dielectric layer 310 on a first side of the first substrate 300, the first dielectric layer 310 having a first opening 301 therein (shown in fig. 5);
a first conductive layer 320 located in the first opening 301, wherein the surface of the first conductive layer 320 is lower than the top surface of the first dielectric layer 310;
a second substrate 400 bonded to the first substrate 300, the second substrate 400 having third and fourth opposing faces; a second dielectric layer 410 on the third face; a conductive structure 440 located in the second dielectric layer 410, wherein the surface of the conductive structure 440 is lower than the surface of the second dielectric layer 410;
an alloy layer 340 between the first conductive layer 320 and the conductive structure 440.
The following detailed description will be made in conjunction with the accompanying drawings.
In this embodiment, the material of the first conductive layer 320 includes copper; the material of the conductive structure 440 includes copper; the material of the alloy layer 340 between the first conductive layer 320 and the conductive structure 440 includes a copper-nickel alloy. The copper-nickel alloy has compact structure, high strength and good chemical stability, so that the bonding strength of a bonding interface is further improved, the bonding effect is optimized, and the electrical property of the device is improved.
In other embodiments, the conductive structure includes a third conductive layer and a fourth conductive layer on the third conductive layer, the material of the third conductive layer includes copper, and the material of the fourth conductive layer includes nickel.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (19)
1. A method of forming a semiconductor structure, comprising:
providing a first substrate having first and second opposing faces;
forming a first dielectric layer on a first surface of a first substrate, wherein the first dielectric layer is internally provided with a first opening;
forming a first conductive layer in the first opening, wherein the surface of the first conductive layer is lower than the top surface of the first dielectric layer;
forming a second conductive layer on the surface of the first conductive layer, wherein the second conductive layer is made of a different material from the first conductive layer;
providing a second substrate, wherein the second substrate is provided with a third surface and a fourth surface which are opposite, a second dielectric layer is formed on the third surface, a conductive structure is arranged in the second dielectric layer, and the surface of the second dielectric layer is exposed out of the conductive structure;
and bonding the first surface of the first substrate towards the third surface of the second substrate to fix the first dielectric layer and the second dielectric layer and form an alloy layer between the first conductive layer and the conductive structure.
2. The method of forming a semiconductor structure according to claim 1, wherein a material of the first conductive layer comprises copper; the material of the conductive structure comprises copper.
3. The method for forming a semiconductor structure according to claim 1, wherein a process for forming the first conductive layer is an electroless plating process; the forming process of the conductive structure is a chemical plating process.
4. The method according to claim 3, wherein in an electroless plating process for forming the first conductive layer, a plating solution comprising a copper sulfate solution and an additive is used; in the chemical plating process for forming the conductive structure, the used electroplating solution is a copper sulfate solution and an additive.
5. The method of forming a semiconductor structure of claim 1, wherein a material of the second conductive layer comprises nickel.
6. The method for forming a semiconductor structure according to claim 1, wherein the method for forming the second conductive layer comprises: forming an initial second conductive layer on the surface of the first conductive layer; and flattening the initial second conductive layer until the surface of the first dielectric layer is exposed to form a second conductive layer.
7. The method of claim 6, wherein the initial second conductive layer is formed by a physical vapor deposition process.
8. The method of forming a semiconductor structure according to claim 7, wherein a thickness of the second conductive layer is 50 to 300 angstroms.
9. The method of claim 6, wherein the initial second conductive layer is formed by an electroless plating process.
10. The method of forming a semiconductor structure according to claim 9, wherein a thickness of the second conductive layer is 30 angstroms to 3 micrometers.
11. The method of forming a semiconductor structure of claim 7, wherein a surface roughness of the second conductive layer is less than 3 nanometers.
12. The method of claim 1, wherein the conductive structure comprises a third conductive layer and a fourth conductive layer over the third conductive layer, wherein the material of the third conductive layer comprises copper, and the material of the fourth conductive layer comprises nickel.
13. The method of forming a semiconductor structure of claim 1, further comprising: performing surface treatment on the surface of the first dielectric layer, wherein the surface treatment process comprises a plasma activation process; and carrying out surface treatment on the surface of the second dielectric layer, wherein the surface treatment process comprises a plasma activation process.
14. The method of claim 7, wherein the heating temperature used during the bonding process is in a range of 130 degrees Celsius to 150 degrees Celsius.
15. The method of claim 9, wherein the heating temperature used during the bonding process is in a range of 130 degrees celsius to 150 degrees celsius.
16. A semiconductor structure, comprising:
a first substrate having opposing first and second sides;
the first dielectric layer is positioned on the first surface of the first substrate and is internally provided with a first opening;
the first conducting layer is positioned in the first opening, and the surface of the first conducting layer is lower than the top surface of the first dielectric layer;
a second substrate bonded to the first substrate, the second substrate having third and fourth opposing faces; a second dielectric layer on the third face; the conductive structure is positioned in the second dielectric layer, and the surface of the conductive structure is lower than the surface of the second dielectric layer;
an alloy layer between the first conductive layer and the conductive structure.
17. The semiconductor structure of claim 16, wherein a material of the first conductive layer comprises copper; the material of the conductive structure comprises copper.
18. The semiconductor structure of claim 16, wherein a material of the alloy layer comprises a copper nickel alloy.
19. The semiconductor structure of claim 16, wherein the conductive structure comprises a third conductive layer and a fourth conductive layer over the third conductive layer, wherein a material of the third conductive layer comprises copper and a material of the fourth conductive layer comprises nickel.
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