CN113612447A

CN113612447A - Oscillating circuit

Info

Publication number: CN113612447A
Application number: CN202111173416.XA
Authority: CN
Inventors: 邱文才; 林满院; 田学红
Original assignee: Shenzhen Yingterui Semiconductor Technology Co ltd
Current assignee: Shenzhen Yingterui Semiconductor Technology Co ltd
Priority date: 2021-10-09
Filing date: 2021-10-09
Publication date: 2021-11-05
Anticipated expiration: 2041-10-09
Also published as: CN113612447B

Abstract

The embodiment of the invention discloses an oscillating circuit. The oscillation circuit includes: the circuit comprises a resonant circuit, a feedback amplification circuit, a current on-off control circuit and a pulse current output circuit; the current on-off control circuit is used for enabling the first end of the resonant circuit and the first end of the feedback amplifying circuit to be in a through-current state and a flow-blocking state periodically after the resonant circuit reaches a first preset oscillation state; the pulse current output circuit is used for outputting current to the resonant circuit when the first end of the resonant circuit and the first end of the feedback amplifying circuit are in a choked flow state through the current on-off control circuit after the resonant circuit reaches a first preset oscillation state. According to the technical scheme provided by the embodiment of the invention, when the pulse current output circuit provides current for the resonant circuit within shorter pulse time, one end of the resonant circuit is disconnected with the feedback amplifying circuit providing equivalent negative resistance, so that the power consumption of the oscillating circuit is reduced.

Description

Oscillating circuit

Technical Field

The invention relates to the technical field of oscillating circuits, in particular to an oscillating circuit.

Background

The quartz crystal oscillator is a resonance device manufactured by utilizing the piezoelectric effect of the quartz crystal, and because the quartz crystal has a very high quality factor, the quartz crystal oscillator can generate an oscillation waveform with accurate and stable frequency, and is widely applied to the fields of clocks, military industry, communication and the like with higher requirements on the oscillation frequency.

With the rapid development of portable devices in the field of communications in recent years, the demand for designing integrated circuits with low power consumption and low cost has been increasingly highlighted.

Disclosure of Invention

The embodiment of the invention provides an oscillating circuit, so that when a pulse current output circuit provides current for a resonant circuit in a short pulse time, one end of the resonant circuit is disconnected with a feedback amplifying circuit providing an equivalent negative resistance, and the situation that the pulse current output circuit provides driving current for the resonant circuit because the two ends of the resonant circuit are always connected with the feedback amplifying circuit providing the equivalent negative resistance and is directly guided by the feedback amplifying circuit providing a negative resistance function to cause great power loss is avoided, and the power consumption of the oscillating circuit is greatly reduced.

An embodiment of the present invention provides an oscillation circuit, including: the circuit comprises a resonant circuit, a feedback amplification circuit, a current on-off control circuit and a pulse current output circuit;

the first end of the resonant circuit is electrically connected with the first end of the feedback amplifying circuit through the current on-off control circuit; the pulse current output circuit is electrically connected with the resonance circuit; the current on-off control circuit is used for enabling the first end of the resonant circuit and the first end of the feedback amplifying circuit to be in a through-current state and a flow-blocking state periodically after the resonant circuit reaches a first preset oscillation state; the pulse current output circuit is used for outputting current to the resonant circuit when the first end of the resonant circuit and the first end of the feedback amplifying circuit are in a choked flow state through the current on-off control circuit after the resonant circuit reaches a first preset oscillation state.

Furthermore, the pulse current output circuit is used for not outputting current to the resonant circuit after the resonant circuit reaches the first preset oscillation state and when the current on-off control circuit enables the first end of the resonant circuit and the first end of the feedback amplification circuit to be in a through-current state, and before the resonant circuit reaches the first preset oscillation state;

the current on-off control circuit is used for enabling the first end of the resonant circuit and the first end of the feedback amplifying circuit to be in a through-flow state before the resonant circuit reaches a first preset oscillation state.

Further, the pulse current output circuit comprises a first direct current source, a first transistor and a first control circuit, wherein the first direct current source is electrically connected with a first pole of the first transistor; the second pole of the first transistor is electrically connected with the resonant circuit; the first control circuit is electrically connected with the control electrode of the first transistor; the first control circuit is used for controlling the conduction of the first transistor when the resonant circuit reaches a first preset oscillation state and a current on-off control circuit enables a current blocking state to be formed between the first end of the resonant circuit and the first end of the feedback amplifying circuit.

Further, the first control circuit comprises a clock signal generating circuit and a follow current pulse generating circuit, wherein the input end of the clock signal generating circuit is electrically connected with the resonance circuit; the output end of the clock signal generating circuit is electrically connected with the input end of the follow current pulse generating circuit; the output terminal of the freewheel pulse generating circuit is electrically connected to the control electrode of the first transistor.

Further, the freewheel pulse generating circuit includes a signal delay circuit, a nor gate circuit, and a first inverter; the input end of the signal delay circuit and the first input end of the NOR gate circuit are electrically connected with the output end of the clock signal generating circuit; the output end of the NOR gate circuit is electrically connected with the output end of the follow current pulse generating circuit through a first inverter; the signal delay circuit includes a plurality of second inverters connected in series.

Further, the current on-off control circuit comprises a first switch; the first end of the first switch is electrically connected with the first end of the resonant circuit; the second end of the first switch is electrically connected with the first end of the feedback amplifying circuit; the control end of the first switch is electrically connected with the first control circuit; the first control circuit is used for controlling the first switch to be periodically switched on or switched off after the resonant circuit reaches a first preset oscillation state.

Further, the feedback amplification circuit includes: the feedback resistor, the second current source and the amplifying circuit; the first end of the feedback resistor is electrically connected with the first end of the feedback amplifying circuit; the second end of the feedback resistor is electrically connected with the second end of the resonant circuit; the first end of the amplifying circuit is electrically connected with the second end of the feedback resistor; the second end of the amplifying circuit is electrically connected with the first end of the feedback amplifying circuit; the second current source is electrically connected with the second end of the amplifying circuit.

Further, the amplifying circuit is a transconductance adjustable amplifying circuit, wherein the transconductance of the amplifying circuit before the resonant circuit reaches the second preset oscillation state is larger than the transconductance of the amplifying circuit after the resonant circuit reaches the second preset oscillation state;

and/or the second current source is an adjustable current source, wherein the current output by the second current source before the resonant circuit reaches the second preset oscillation state is larger than the current output by the second current source after the resonant circuit reaches the second preset oscillation state.

Further, the amplifying circuit includes a second transistor, a third transistor, a fourth transistor, and a second control circuit; the control electrode of the second transistor and the control electrode of the third transistor are electrically connected with the first end of the amplifying circuit; the first pole of the second transistor and the first pole of the third transistor are electrically connected with the second end of the amplifying circuit; the second pole of the second transistor is grounded; a second pole of the third transistor is electrically connected with the first pole of the fourth transistor; the second pole of the fourth transistor is grounded; the control electrode of the fourth transistor is electrically connected with the second control circuit; the size of the third transistor is larger than that of the second transistor; the second control circuit is used for controlling the fourth transistor to be conducted before the resonant circuit reaches a second preset oscillation state; after the resonant circuit reaches a second preset oscillation state, controlling the fourth transistor to be switched off;

the second current source comprises a first direct current source unit, a second direct current source unit and a fifth transistor; the first direct current source unit is electrically connected with the second end of the amplifying circuit; the second direct current source unit is electrically connected with the first pole of the fifth transistor; a second pole of the fifth transistor is electrically connected with a second end of the amplifying circuit; a control electrode of the fifth transistor is electrically connected with the second control circuit; the second control circuit is used for controlling the fifth transistor to be conducted before the resonant circuit reaches a second preset oscillation state; and after the resonant circuit reaches the second preset oscillation state, controlling the fifth transistor to be turned off.

Further, the second control circuit comprises an oscillation state identification circuit and a selection signal generation circuit, wherein the output end of the oscillation state identification circuit is electrically connected with the input end of the selection signal generation circuit; the first output end of the selection signal generating circuit is electrically connected with the control electrode of the fourth transistor; the second output terminal of the selection signal generation circuit is electrically connected to the control electrode of the fifth transistor.

Further, the resonant circuit comprises a crystal, a first capacitor and a second capacitor, wherein the first end of the crystal is grounded through the first capacitor; the second end of the crystal is grounded through a second capacitor; a first end of the crystal is electrically connected with a first end of the resonant circuit; the second end of the crystal is electrically connected with the second end of the resonant circuit;

the pulse current output circuit is electrically connected with the first end of the resonance circuit; alternatively, the pulse current output circuit is electrically connected to the second terminal of the resonance circuit.

The oscillation circuit in the technical scheme of the embodiment of the invention comprises a resonance circuit, a feedback amplification circuit, a current on-off control circuit and a pulse current output circuit; the first end of the resonant circuit is electrically connected with the first end of the feedback amplifying circuit through the current on-off control circuit; the pulse current output circuit is electrically connected with the resonance circuit; the current on-off control circuit is used for enabling the first end of the resonant circuit and the first end of the feedback amplifying circuit to be in a through-current state and a flow-blocking state periodically after the resonant circuit reaches a first preset oscillation state; the pulse current output circuit is used for outputting current to the resonant circuit when the amplitude of the resonant circuit is larger than or equal to the preset amplitude and the current on-off control circuit enables the first end of the resonant circuit and the first end of the feedback amplification circuit to be in a choked flow state. When the pulse current output circuit provides current for the resonant circuit within a short pulse time, one end of the resonant circuit is disconnected with the feedback amplifying circuit providing the equivalent negative resistance, so that the situation that the pulse current output circuit provides driving current for the resonant circuit due to the fact that two ends of the resonant circuit are always connected with the feedback amplifying circuit providing the equivalent negative resistance is avoided, the pulse current output circuit is directly guided to the ground by the feedback amplifying circuit providing the negative resistance function, and great power loss is caused, and therefore power consumption of the oscillating circuit is greatly reduced.

Drawings

Fig. 1 is a schematic structural diagram of an oscillation circuit according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a pulse current output circuit according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a pulse current output circuit according to an embodiment of the present invention when the pulse current output circuit does not output current;

FIG. 4 is a waveform diagram provided by an embodiment of the present invention;

fig. 5 is a schematic structural diagram of another oscillation circuit according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of a first control circuit according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of a second control circuit according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of the switching states of transistors with smaller amplitudes according to an embodiment of the present invention;

fig. 9 is a schematic diagram of the switching states of the transistors in a time period t1 when the oscillation state is stable according to the embodiment of the present invention;

fig. 10 is a schematic diagram of the switching states of the transistors in a time period t2 when the oscillation state is stable according to the embodiment of the present invention;

FIG. 11 is a diagram of another waveform provided by an embodiment of the present invention;

fig. 12 is a schematic structural diagram of another oscillation circuit according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

The embodiment of the invention provides an oscillating circuit. Fig. 1 is a schematic structural diagram of an oscillation circuit according to an embodiment of the present invention. The oscillating circuit may be provided in a clock circuit. The oscillation circuit includes: the circuit comprises a resonant circuit 10, a feedback amplifying circuit 20, a current on-off control circuit 30 and a pulse current output circuit 40.

The first end XT2 of the resonant circuit 10 is electrically connected with the first end Q1 of the feedback amplifying circuit 20 through the current on-off control circuit 30; the pulse current output circuit 40 is electrically connected to the resonance circuit 10; the current on-off control circuit 30 is configured to periodically enable a current flowing state and a current blocking state between the first end XT2 of the resonant circuit 10 and the first end Q1 of the feedback amplification circuit 20 after the resonant circuit 10 reaches a first preset oscillation state; the pulse current output circuit 40 is configured to output a current to the resonant circuit 10 when a current flowing between the first terminal XT2 of the resonant circuit 10 and the first terminal Q1 of the feedback amplifier circuit 20 is blocked by the current on-off control circuit 30 after the resonant circuit 10 reaches the first preset oscillation state.

The oscillation circuit may be a pierce oscillation circuit or the like. The resonant circuit 10 may comprise a crystal, a capacitor, etc. The resonant circuit 10 may generate a sine wave signal. The feedback amplifier circuit 20 can be used to make the resonant circuit 10 start up normally and operate stably. The period of the pulse current output from the pulse current output circuit 40 may be equal to the period of the resonance circuit 10. The pulse current output circuit 40 is configured to not output current to the resonant circuit 10 after the resonant circuit 10 reaches the first predetermined oscillation state and when a current flows between the first terminal XT2 of the resonant circuit 10 and the first terminal Q1 of the feedback amplifier circuit 20 through the current on-off control circuit 30. The pulse current output circuit 40 may pulse current to the resonant circuit 10 to supplement the energy required by the resonant circuit 10 to maintain oscillation. The frequency and the width of the pulse current output by the pulse current output circuit 40 may be set as required, which is not limited in the embodiment of the present invention. The frequency of the pulse current output by the pulse current output circuit 40 may be greater than or equal to the frequency of the resonance circuit 10, and for example, the frequency of the pulse current output by the pulse current output circuit 40 may be equal to an integer multiple of the frequency of the resonance circuit 10. The current on-off control circuit 30 may include a first switch.

After the oscillating circuit is powered on, the resonant circuit 10 starts to oscillate, and after oscillating for a period of time, the amplitude gradually increases until reaching the set amplitude, namely reaching a stable oscillation state. The first preset oscillation state may be a stable oscillation state after the amplitude of the resonance circuit 10 reaches a set amplitude. Fig. 2 is a schematic diagram of a pulse current output circuit according to an embodiment of the present invention. Fig. 3 is a schematic diagram of a pulse current output circuit according to an embodiment of the present invention when the pulse current output circuit does not output current. Fig. 4 is a waveform diagram according to an embodiment of the present invention. Wherein Sig1 may be the waveform of the sine wave signal generated by the resonant circuit 10, and I1 is the waveform of the current output by the pulse current output circuit 40. After the resonant circuit 10 reaches the first preset oscillation state, within a time period T1 of any period T, the pulse current output circuit 40 outputs a current to the resonant circuit 10, and the current on-off control circuit 30 is in a current blocking state, as shown in fig. 2, the first switch S1 is turned off, so that the first end XT2 of the resonant circuit is turned off from the feedback amplification circuit 20 providing the equivalent negative resistance, and a situation that the two ends of the resonant circuit are always connected to the feedback amplification circuit providing the equivalent negative resistance, so that a driving current provided by the pulse current output circuit to the resonant circuit is directly guided to the ground by the feedback amplification circuit providing the negative resistance function, which causes a great power loss occurs, thereby greatly reducing the power consumption of the resonant circuit, and enabling the resonant circuit to operate in a low power consumption mode. After the resonant circuit 10 reaches the first preset oscillation state, in a time period T2 of any period T, the pulse current output circuit 40 may not output current to the resonant circuit 10, and the current on-off control circuit 30 may be in a current flowing state, as shown in fig. 3, so that the first switch S1 is turned on.

The oscillation circuit in the technical scheme of the embodiment comprises a resonance circuit, a feedback amplification circuit, a current on-off control circuit and a pulse current output circuit; the first end of the resonant circuit is electrically connected with the first end of the feedback amplifying circuit through the current on-off control circuit; the pulse current output circuit is electrically connected with the resonance circuit; the current on-off control circuit is used for enabling the first end of the resonant circuit and the first end of the feedback amplifying circuit to be in a through-current state and a flow-blocking state periodically after the resonant circuit reaches a first preset oscillation state; the pulse current output circuit is used for outputting current to the resonant circuit when the amplitude of the resonant circuit is larger than or equal to the preset amplitude and the current on-off control circuit enables the first end of the resonant circuit and the first end of the feedback amplification circuit to be in a choked flow state. When the pulse current output circuit provides current for the resonant circuit within a short pulse time, one end of the resonant circuit is disconnected with the feedback amplifying circuit providing the equivalent negative resistance, so that the situation that the pulse current output circuit provides driving current for the resonant circuit due to the fact that two ends of the resonant circuit are always connected with the feedback amplifying circuit providing the equivalent negative resistance is avoided, the pulse current output circuit is directly guided to the ground by the feedback amplifying circuit providing the negative resistance function, and great power loss is caused, and therefore power consumption of the oscillating circuit is greatly reduced.

Optionally, the pulse current output circuit 40 is configured to not output current to the resonant circuit 10 until the resonant circuit 10 reaches the first preset oscillation state.

However, before the amplitude of the resonant circuit 10 does not reach the set amplitude, which corresponds to before the resonant circuit 10 does not reach the stable oscillation state, the pulse current output circuit 40 does not output a current to the resonant circuit 10.

Optionally, the current on-off control circuit 30 is configured to enable a current to flow between the first terminal XT2 of the resonant circuit 10 and the first terminal Q1 of the feedback amplifier circuit 20 before the resonant circuit 10 reaches the first preset oscillation state.

However, before the amplitude of the resonant circuit 10 does not reach the set amplitude, which corresponds to before the resonant circuit 10 does not reach the stable oscillation state, the current on-off control circuit 30 can make the first terminal XT2 of the resonant circuit 10 and the first terminal Q1 of the feedback amplification circuit 20 be in the through-flow state.

Optionally, on the basis of the foregoing embodiment, fig. 5 is a schematic structural diagram of another oscillation circuit provided in the embodiment of the present invention, where the pulse current output circuit 40 includes: a first direct current source 41, a first transistor P4 and a first control circuit 42.

The first direct current source 41 is electrically connected to a first pole of the first transistor P4, the second pole of the first transistor P4 is electrically connected to the resonant circuit 10, and the first control circuit 42 is electrically connected to a control pole of the first transistor P4.

The first control circuit 42 is configured to control the first transistor P4 to be turned on after the resonant circuit 10 reaches the first preset oscillation state and when the current on-off control circuit 30 makes a current between the first end XT2 of the resonant circuit 10 and the first end Q1 of the feedback amplifying circuit 20 be in a current blocking state, so that the first dc power supply 41 outputs a current to the resonant circuit 10.

The first control circuit 42 is configured to control the first transistor P4 to turn off after the resonant circuit 10 reaches the first predetermined oscillation state and when the current flowing between the first terminal XT2 of the resonant circuit 10 and the first terminal Q1 of the feedback amplifier circuit 20 is enabled to flow through the current on-off control circuit 30, so that the first dc current source 41 does not output current to the resonant circuit 10. The first control circuit 42 may output a high level or a low level to the control electrode of the first transistor P4 to control the first transistor P4 to be turned on or off. The first transistor P4 may include a PMOS transistor, the first electrode of the first transistor P4 may be a source, the second electrode of the first transistor P4 may be a drain, and the control electrode of the first transistor P4 may be a gate.

Alternatively, on the basis of the above embodiment, with continued reference to fig. 5, the first direct current source 41 may comprise a sixth transistor P3. Wherein a first pole of the sixth transistor P3 is electrically connected to the second voltage source 60; a second pole of the sixth transistor P3 is electrically connected to the first pole of the first transistor P4; the control electrode of the sixth transistor P3 may be electrically connected to the first voltage source 50.

Wherein the first direct current source 41 can output a constant current. The sixth transistor P3 may include a PMOS transistor, the first pole of the sixth transistor P3 may be a source, the second pole of the sixth transistor P3 may be a drain, and the control pole of the sixth transistor P3 may be a gate. By adjusting the voltage of the control electrode of the sixth transistor P3, the current flowing through the sixth transistor P3 may be adjusted. The output voltage of the first voltage source 50 can be set as required so that the current output by the first direct current source 41 can meet the requirement. The first voltage source 50 may output a constant voltage. The second voltage source 60 may output a constant voltage.

Optionally, on the basis of the above embodiment, fig. 6 is a schematic structural diagram of a first control circuit according to an embodiment of the present invention, and as shown in fig. 5 and fig. 6, the first control circuit 42 includes a clock signal generating circuit 421 and a free-wheeling pulse generating circuit 422.

Wherein, the input terminal In1 of the clock signal generating circuit 421 is electrically connected to the resonant circuit 10; the output terminal Out1 of the clock signal generation circuit 421 is electrically connected to the input terminal of the freewheel pulse generation circuit 422; the output terminal of the freewheel pulse generating circuit 422 is electrically connected to the control electrode of the first transistor P4.

Wherein, the input terminal In1 of the clock signal generating circuit 421 can be electrically connected with the second terminal XT1 of the resonant circuit 10. The clock signal generation circuit 421 may convert the sine wave signal generated by the resonance circuit 10 into a clock signal. The freewheel pulse generating circuit 422 may perform inverse delay or nor logic operation on the clock signal to generate a freewheel pulse signal with a smaller pulse width to control the first transistor P4 to be turned on or off periodically. The width of the freewheel pulse signal is equal to the delay time of the delayed clock signal. The width of the freewheel pulse signal may determine the width of the pulse signal output by the pulse current output circuit 40.

Alternatively, on the basis of the above embodiment, with continued reference to fig. 6, the clock signal generation circuit 421 includes a low pass filter 4214, a first comparator 4211, a first counter 4212, and a nand gate circuit 4213.

An input end of the low-pass filter 4214 and a first input end of the first comparator 4211 are electrically connected to the input end In1 of the clock signal generating circuit 421; an output terminal of the low-pass filter 4214 is electrically connected to a second input terminal of the first comparator 4211; the output end of the first comparator 4211 is electrically connected with a first input end of the nand gate circuit 4213; an output end of the first comparator 4211 is electrically connected to a second input end of the nand gate circuit 4213 through a first counter 4212; an output terminal of the nand gate circuit 4213 is electrically connected to the output terminal Out1 of the clock signal generating circuit 421.

Optionally, the first input terminal of the first comparator 4211 may be a non-inverting input terminal, and the second input terminal of the first comparator 4211 may be an inverting input terminal. Alternatively, the first input terminal of the first comparator 4211 may be an inverting input terminal, and the second input terminal of the first comparator 4211 may be a non-inverting input terminal. The low pass filter 4214 may comprise: the input end of the low-pass filter 4214 is electrically connected with the output end of the low-pass filter 4214 through a second resistor R3; the output of the low pass filter 4214 is connected to ground via a third capacitor C3.

The sine wave input by the input terminal In1 of the clock signal generating circuit 421 is input as the negative terminal of the first comparator 4211, the dc signal output by the low pass filter 4214 is input as the positive terminal of the first comparator 4211, the output terminal of the first comparator 4211 outputs a square wave, the first counter 4212 counts the number of edges of the square wave, and when the number reaches a first set value, the output signal of the output terminal of the first counter 4212 is inverted, for example, from a low level to a high level, the enable gate circuit 4213 is enabled, and the output terminal Out1 of the clock signal generating circuit 421 outputs a clock signal. The first setting value determines a first predetermined oscillation state. The larger the first set value is, the longer the time required to reach the first preset oscillation state is. The first setting value may be set according to needs, which is not limited in the embodiment of the present invention.

Alternatively, on the basis of the above-described embodiment, with continued reference to fig. 6, the freewheel pulse generating circuit 422 includes a signal delay circuit 4221, a nor gate circuit 4222, and a first inverter 4223. An input end of the signal delay circuit 4221 and a first input end of the nor gate circuit 4222 are electrically connected to the output end Out1 of the clock signal generating circuit 421; an output terminal of the nor gate circuit 4222 is electrically connected to an output terminal of the freewheel pulse generating circuit 422 via a first inverter 4223.

The signal delay circuit 4221 may be an inverting delay circuit. Optionally, the signal delay circuit 4221 includes a plurality of second inverters 42211 connected in series. Fig. 6 exemplarily shows a case where the signal delay circuit 4221 includes three second inverters 42211 connected in series. The clock signal generated by the clock signal generation circuit 421 is delayed by the three second inverters 42211, and the delayed signal passes through the nor gate circuit 4222 together with the original clock signal, and then a pulse signal having a short time is generated, and the pulse width of the pulse signal is equal to the delay time of the delayed clock signal.

Alternatively, on the basis of the above embodiment, with continued reference to fig. 5, the current on-off control circuit 30 may include the first switch S1.

Wherein, the first terminal of the first switch S1 is electrically connected with the first terminal XT2 of the resonant circuit 10; a second terminal of the first switch S1 is electrically connected to the first terminal Q1 of the feedback amplifying circuit 20; the control terminal of the first switch S1 is electrically connected to the first control circuit 42; the first control circuit 42 is used for controlling the first switch S1 to be turned on or off periodically after the resonant circuit 10 reaches the first preset oscillation state.

The first control circuit 42 is configured to control the first switch S1 to turn off when the pulse current output circuit 40 outputs a current to the resonant circuit 10 after the resonant circuit 10 reaches the first preset oscillation state, so that a current blocking state is formed between the first terminal XT2 of the resonant circuit 10 and the first terminal Q1 of the feedback amplifying circuit 20. The first control circuit 42 is configured to control the first switch S1 to be turned on when the pulse current output circuit 40 does not output a current to the resonant circuit 10 after the resonant circuit 10 reaches the first preset oscillation state, so that a current flows between the first terminal XT2 of the resonant circuit 10 and the first terminal Q1 of the feedback amplifying circuit 20. The first control circuit 42 is configured to control the first switch S1 to be turned on before the resonant circuit 10 reaches the first predetermined oscillation state, so that a current flows between the first terminal XT2 of the resonant circuit 10 and the first terminal Q1 of the feedback amplifying circuit 20. The first switch S1 may include a metal-oxide-semiconductor (MOS) Transistor, a Bipolar Junction Transistor (BJT) Transistor, a relay, or the like. The first control circuit 42 may output a high level or a low level to the control terminal of the first switch S1 to control the first switch S1 to be turned on or off periodically. A control terminal of the first switch S1 may be electrically connected with an output terminal of the first inverter 4223.

Alternatively, on the basis of the above-described embodiment, with continued reference to fig. 5, the feedback amplification circuit 20 includes the feedback resistor R0, the second current source 21, and the amplification circuit 22.

Wherein, the first end of the feedback resistor R0 is electrically connected with the first end Q1 of the feedback amplifying circuit 20; a second end of the feedback resistor R0 is electrically connected to a second end XT1 of the resonant circuit 10; a first end of the amplifying circuit 22 is electrically connected to a second end of the feedback resistor R0; the second terminal of the amplifying circuit 22 is electrically connected to the first terminal Q1 of the feedback amplifying circuit 20; the second current source 21 is electrically connected to a second terminal of the amplifier circuit 22.

The feedback resistor R0 can make the transistor in the amplifying circuit 22 operate in the linear region or the sub-threshold region, and not operate in the fully on or fully off state. When the amplifying circuit 22 is in normal operation, it is equivalent to a negative resistance, which can counteract the power consumption loss of the equivalent internal resistance of the crystal in the resonant circuit 10, so that the whole oscillating circuit can maintain stable oscillation.

Optionally, the amplifying circuit 22 is a transconductance adjustable amplifying circuit, wherein a transconductance of the amplifying circuit 22 before the resonant circuit 10 reaches the second preset oscillation state is larger than a transconductance of the amplifying circuit after the resonant circuit 10 reaches the second preset oscillation state.

The second preset oscillation state may be a stable oscillation state after the amplitude of the resonant circuit 10 reaches the set amplitude. The second preset oscillation state may be before or after the first preset oscillation state.

When the circuit is powered on, the oscillation circuit does not start oscillation or has a small oscillation amplitude, and does not reach a stable oscillation state with a set amplitude, which is equivalent to that the resonance circuit 10 does not reach a second preset oscillation state, so that the transconductance of the amplifying circuit 22 is larger, the absolute value of the equivalent negative resistance is larger, the starting oscillation of the oscillation circuit is facilitated, and the oscillation circuit is enabled to oscillate rapidly. After the start-up and the stable oscillation of the oscillator circuit, which is equivalent to after the resonant circuit 10 reaches the second predetermined oscillation state, the transconductance of the amplifier circuit 22 is reduced to save power consumption, and the oscillator circuit is switched from the start-up stage to the low power consumption mode.

Optionally, the second current source 21 is an adjustable current source, wherein the current output by the second current source 21 before the resonant circuit 10 reaches the second preset oscillation state is greater than the current output by the second current source 21 after the resonant circuit 10 reaches the second preset oscillation state.

When the circuit is powered on, the oscillation circuit does not start oscillation or has a small oscillation amplitude, and does not reach a stable oscillation state with a set amplitude, which is equivalent to that the resonance circuit 10 does not reach a second preset oscillation state, so that the current output by the second current source 21 is large, the working current of the amplifying circuit 22 is large, the oscillation circuit starts oscillation, and the oscillation circuit oscillates rapidly. After the start-up and the stable oscillation of the oscillating circuit, which is equivalent to the resonant circuit 10 reaching the second preset oscillation state, in order to save power consumption, the current output by the second current source 21 is reduced, so that the working current of the amplifying circuit 22 is reduced, and the oscillating circuit is switched from the start-up stage to the low power consumption mode.

Alternatively, on the basis of the above embodiment, with continued reference to fig. 5, the amplifying circuit 22 includes the second transistor N2, the third transistor N0, the fourth transistor N1, and the second control circuit 23.

A control electrode of the second transistor N2 and a control electrode of the third transistor N0 are electrically connected to the first end of the amplifying circuit 22; a first pole of the second transistor N2 and a first pole of the third transistor N0 are electrically connected to the second terminal of the amplifying circuit 22; the second pole of the second transistor N2 is grounded; a second pole of the third transistor N0 is electrically connected to a first pole of the fourth transistor N1; a second pole of the fourth transistor N1 is grounded; a control electrode of the fourth transistor N1 is electrically connected to the second control circuit 23; the size of the third transistor N0 is larger than that of the second transistor N2; the second control circuit 23 is configured to control the fourth transistor N1 to be turned on before the resonant circuit 10 reaches the second preset oscillation state; after the resonant circuit 10 reaches the second preset oscillation state, the fourth transistor N1 is controlled to be turned off.

The second control circuit 23 may output a high level or a low level to the gate of the fourth transistor N1 to control the fourth transistor N1 to be turned on or off. The second transistor N2 may include an NMOS transistor, the first pole of the second transistor N2 may be a drain, the second pole of the second transistor N2 may be a source, and the control pole of the second transistor N2 may be a gate. The third transistor N0 may include an NMOS transistor, the first pole of the third transistor N0 may be a drain, the second pole of the third transistor N0 may be a source, and the control pole of the third transistor N0 may be a gate. The fourth transistor N1 may include an NMOS transistor, the first electrode of the fourth transistor N1 may be a drain, the second electrode of the fourth transistor N1 may be a source, and the control electrode of the fourth transistor N1 may be a gate. The larger the size of the transistor, the larger the transconductance.

When the circuit is powered on, the oscillation circuit does not start oscillation or the oscillation amplitude is small, the stable oscillation state of the set amplitude is not achieved, namely the resonance circuit 10 does not reach the second preset oscillation state, the second control circuit 23 controls the fourth transistor N1 to be switched on, and the third transistor N0 functions, so that the transconductance of the amplifying circuit 22 is large, the absolute value of the equivalent negative resistance is also large, the starting oscillation of the oscillation circuit is facilitated, and the oscillation circuit can oscillate rapidly. After the oscillator circuit is started and stable oscillation, which is equivalent to after the resonant circuit 10 reaches the second preset oscillation state, in order to save power consumption, the second control circuit 23 controls the fourth transistor N1 to turn off, the third transistor N0 does not function, so that the transconductance of the amplifying circuit 22 is reduced, and the oscillator circuit is switched to the low power consumption mode from the start-up stage.

Alternatively, on the basis of the above-described embodiment, with continued reference to fig. 5, the second current source 21 includes the first direct current source unit 211, the second direct current source unit 212, and the fifth transistor P2.

The first direct current source unit 211 is electrically connected to the second end of the amplifying circuit 22; the second dc current source unit 212 is electrically connected to a first pole of the fifth transistor P2; a second pole of the fifth transistor P2 is electrically connected to the second terminal of the amplifying circuit 22; a control electrode of the fifth transistor P2 is electrically connected to the second control circuit 23; the second control circuit 23 is configured to control the fifth transistor P2 to be turned on before the resonant circuit 10 reaches the second preset oscillation state; after the resonant circuit 10 reaches the second preset oscillation state, the fifth transistor P2 is controlled to be turned off.

The second control circuit 23 may output a high level or a low level to the control electrode of the fifth transistor P2 to control the fifth transistor P2 to be turned on or off. The fifth transistor P2 may include a PMOS transistor, the first electrode of the fifth transistor P2 may be a source, the second electrode of the fifth transistor P2 may be a drain, and the control electrode of the fifth transistor P2 may be a gate.

When the circuit is powered on, the oscillation circuit does not start oscillation or the oscillation amplitude is small, the stable oscillation state of the set amplitude is not achieved, that is, the resonance circuit 10 does not reach the second preset oscillation state, the second control circuit 23 controls the fifth transistor P2 to be switched on, and the first direct current power supply unit 211 functions to enable the working current of the amplifying circuit 22 to be large, the absolute value of the equivalent negative resistance to be large, so that the oscillation circuit starts oscillation, and the oscillation circuit oscillates rapidly. After the oscillator circuit is started and oscillates stably, which is equivalent to that after the resonant circuit 10 reaches the second preset oscillation state, in order to save power consumption, the second control circuit 23 controls the fifth transistor P2 to be turned off, the first direct current power supply unit 211 does not function, so that the operating current of the amplifier circuit 22 is reduced, and the oscillator circuit is switched to the low power consumption mode from the start-up stage.

Alternatively, on the basis of the above embodiment, with continued reference to fig. 5, the first direct current supply unit 211 may include a seventh transistor P0. Wherein a first pole of the seventh transistor P0 is electrically connected to the second voltage source 60; a second pole of the seventh transistor P0 is electrically connected to the second terminal of the amplifying circuit 22; the control electrode of the seventh transistor P0 is electrically connected to the first voltage source 50.

Wherein the first direct current source unit 211 may output a constant current. The seventh transistor P0 may include a PMOS transistor, the first pole of the seventh transistor P0 may be a source, the second pole of the seventh transistor P0 may be a drain, and the control pole of the seventh transistor P0 may be a gate. By adjusting the voltage of the gate of the seventh transistor P0, the current flowing through the seventh transistor P0 can be adjusted. The output voltage of the first voltage source 50 can be set as required, so that the current output by the first dc current source unit 211 can meet the requirement.

Alternatively, on the basis of the above embodiment, with continued reference to fig. 5, the second direct current source unit 212 may include an eighth transistor P1. Wherein a first pole of the eighth transistor P1 is electrically connected to the second voltage source 60; a second pole of the eighth transistor P1 is electrically connected to the first pole of the fifth transistor P2; the control electrode of the eighth transistor P1 is electrically connected to the first voltage source 50.

Wherein, the second dc current source unit 212 may output a constant current. The eighth transistor P1 may include a PMOS transistor, the first electrode of the eighth transistor P1 may be a source, the second electrode of the eighth transistor P1 may be a drain, and the control electrode of the eighth transistor P1 may be a gate. By adjusting the voltage of the gate of the eighth transistor P1, the current flowing through the eighth transistor P1 can be adjusted. The output voltage of the first voltage source 50 can be set as required, so that the current output by the second dc current source unit 212 can meet the requirement.

Optionally, on the basis of the above embodiment, fig. 7 is a schematic structural diagram of a second control circuit according to an embodiment of the present invention, and as shown in fig. 5 and fig. 7, the second control circuit 23 includes an oscillation state identification circuit 231 and a selection signal generation circuit 232.

Wherein, the output terminal of the oscillation state recognition circuit 231 is electrically connected with the input terminal of the selection signal generation circuit 232; a first output terminal of the selection signal generation circuit 232 is electrically connected to a control electrode of the fourth transistor N1; a second output terminal of the selection signal generation circuit 232 is electrically connected to a control electrode of the fifth transistor P2.

Wherein the oscillation state recognition circuit 231 may be electrically connected with the resonance circuit 10. The oscillation state identification circuit 231 may be used to identify the oscillation state of the resonance circuit 10. When the resonant circuit 10 reaches the second preset oscillation state, the output signal of the oscillation state identification circuit 231 is inverted, and further the output signal of the first output terminal of the selection signal generation circuit 232 is inverted, for example, from low level to high level, and the output signal of the second output terminal of the selection signal generation circuit 232 is inverted, for example, from high level to low level, so that the fourth transistor N1 is turned from on to off, the fifth transistor P2 is turned from on to off, so that the transconductance of the amplifying circuit 22 is reduced, and the output current of the second current source 21 is reduced, so that the oscillation circuit will be switched from the start-up stage to the low power consumption mode.

Alternatively, on the basis of the above embodiment, with continued reference to fig. 7, the oscillation state recognition circuit 231 may include a second comparator 2311 and a second counter 2312. A first input terminal of the second comparator 2311 may be electrically connected to the resonant circuit 10; a second input terminal of the second comparator 2311 is electrically connected to the reference voltage source 70; an output terminal of the second comparator 2311 is electrically connected to an input terminal of the selection signal generating circuit 232 via the second counter 2312.

Optionally, the first input terminal of the second comparator 2311 may be a non-inverting input terminal, and the second input terminal of the second comparator 2311 may be an inverting input terminal. Alternatively, the first input terminal of the second comparator 2311 may be an inverting input terminal, and the second input terminal of the second comparator 2311 may be a non-inverting input terminal.

Illustratively, when the amplitude of the sinusoidal signal generated by the resonant circuit 10 is small, the output signal of the second comparator 2311 is at a low level, after oscillating for a period of time, the amplitude of the sinusoidal signal generated by the resonant circuit 10 is large, the output signal of the second comparator 2311 is a square wave signal, and when the number of pulses counted by the second counter 2312 reaches a second preset value, the output signal of the second counter 2312 is inverted, for example, from the low level to the high level.

Alternatively, on the basis of the above embodiment, with continuing reference to fig. 7, the selection signal generation circuit 232 may include a D flip-flop 2321 and a third inverter 2322. The signal input end D of the D flip-flop 2321 may be electrically connected to the input end of the selection signal generating circuit 232; a signal output end Q of the D flip-flop 2321 is electrically connected to the first output end of the selection signal generating circuit 232 through the third inverter 2322; the signal output terminal Q of the D flip-flop 2321 is electrically connected to the second output terminal of the selection signal generating circuit 232.

Illustratively, when the output signal of the oscillation state recognition circuit 231 is inverted and a signal with a rising edge arrives at the pulse signal input terminal CLK of the D flip-flop 2321, the output signal of the D flip-flop 2321 is inverted, and the high-level signal is locked until a clear signal is input to the clear terminal CLR, so that the state is cleared. The clock input terminal CLK of the D flip-flop may be electrically connected to a clock signal source. When the output signal of the D flip-flop 2321 is inverted, the output signal of the third inverter 2322 is inverted, so that the fourth transistor N1 is turned from on to off, and the fifth transistor P2 is turned from on to off.

Optionally, on the basis of the above embodiment, with continued reference to fig. 5, the resonant circuit 10 includes a crystal Y1, a first capacitor C0, and a second capacitor C1.

The first end of the crystal Y1 is grounded through a first capacitor C0, and the first end of the crystal Y1 is electrically connected with the first end XT2 of the resonant circuit 10; the second end of the crystal Y1 is grounded through a second capacitor C1; a second terminal of the crystal Y1 is electrically connected to a second terminal XT1 of the resonant circuit 10.

Wherein the crystal Y1 can be a quartz crystal. In the oscillation circuit, a periodic sine wave signal is generated mainly by oscillation of the crystal Y1. The quartz crystal Y1, the first capacitor C0 and the second capacitor C1 constitute a band pass filter in the form of a pi-network providing a 180 degree phase shift and the required voltage gain at the resonance frequency of the quartz crystal Y1.

As shown in fig. 5, 6 and 7, the electrical nodes with the same labels are electrically connected, such as drvSTB, drvST1, drvB and XTout.

Fig. 8 is a schematic diagram of the switching states of the transistors with smaller amplitudes according to the embodiment of the present invention. Where the transistors marked x are off. Referring to fig. 6, 7 and 8, when the circuit is powered on, because the oscillation circuit does not start oscillation or the oscillation amplitude is small and does not reach the stable oscillation state of the set amplitude value, the sine wave signal with small oscillation amplitude is input to the second comparator 2311 in the oscillation state identification circuit 231 and then output to a low level after passing through the D flip-flop 2321 (i.e. the node drvSTB is at a low level), and output to a high level after passing through the third inverter 2322 (i.e. the node drvST1 is at a high level), so that the fifth transistor P2 and the fourth transistor N1 are turned on, so that a large bias current can be supplied to the second transistor N2 and the third transistor N0 in the amplification circuit 22, and the size of the third transistor N0 is much larger than that of the second transistor N2, so that the transconductance of the oscillating circuit is larger when the oscillating circuit is started, and the absolute value of the equivalent negative resistance is larger, which is beneficial to starting oscillation of the oscillating circuit. At this time, the output end of the first comparator 4211 outputs a square wave, the first counter 4212 counts the number of pulse edges of the square wave, and the number of pulse edges of the square wave does not reach a first set value, the output end of the first counter 4212 outputs a low level, the nand gate 4213 outputs a high level, the nor gate 4222 outputs a low level, and the first inverter 4223 outputs a high level (i.e., the node drvB is a high level), so that the first transistor P4 is turned off, and the first switch S1 is turned on.

Fig. 9 is a schematic diagram of the switching states of the transistors in a time period t1 when the oscillation state is stable according to an embodiment of the present invention. Fig. 10 is a schematic diagram of the switching states of the transistors in a time period t2 when the oscillation state is stable according to the embodiment of the present invention. FIG. 11 is a waveform diagram of another embodiment of the present invention. Wherein Sig1 may be a waveform of a voltage at the second end XT1 of the resonant circuit 10, Sig2 may be a waveform of a voltage at the first end XT2 of the resonant circuit 10, Ck may be a waveform of a clock signal output from the output terminal Out1 of the clock signal generating circuit 421, and I1 may be a waveform of a current output from the pulse current output circuit 40. Referring to fig. 6, 7, 9 and 11, after the oscillation circuit oscillates for a period of time, the second terminal (i.e., the node XTout) of the amplifying circuit 22 reaches a stable oscillation state with a set amplitude value, the input sine wave signal has a large amplitude, the second comparator 2311 outputs a square wave signal, when the count of the second counter 2312 reaches a second preset value, the output signal of the second counter 2312 is inverted, for example, from a low level to a high level, and is output as a high level after passing through the D flip-flop 2321, and is output as a low level after passing through the third inverter 2322, so that the fifth transistor P2 and the fourth transistor N1 are controlled to be turned off, and the oscillation circuit is switched from a start-up stage to a low power consumption mode. The output end of the first comparator 4211 outputs a square wave, the first counter 4212 counts the number of pulse edges of the square wave, and when the number reaches a first set value, the output end of the first counter 4212 inverts, for example, changes from a low level to a high level, so that the nand gate circuit 4213 is enabled, and the output end Out1 of the clock signal generating circuit 421 outputs a clock signal. After the clock signal generated by the clock signal generation circuit 421 is delayed by the signal delay circuit 4221, the delayed signal passes through the nor gate circuit 4222 together with the original clock signal, and then a short-time pulse signal is generated to control the periodic on/off of the first transistor P4 and the first switch S1. As shown in fig. 9, 10 and 11, the square wave signal output from the first control circuit 42 drives the first transistor P4 to be periodically turned on, so as to maintain the oscillation of the oscillation circuit, and enter the low power consumption operation mode. In the low power consumption operation mode, at the stage t1, the first switch S1 is turned off, the first transistor P4 is turned on, and the current provided by the first transistor P4 to the crystal Y1 is fully absorbed by the crystal Y1, so that the situation that the driving current provided to the crystal Y1 is directly guided to the ground by the second transistor N2 providing a negative resistance function, which causes a great power loss, is avoided.

Alternatively, on the basis of the above-described embodiment, with continued reference to fig. 5, the pulse current output circuit 40 is electrically connected to the first terminal XT2 of the resonance circuit 10.

Alternatively, on the basis of the above embodiment, fig. 12 is a schematic structural diagram of another oscillation circuit provided in the embodiment of the present invention, and the pulse current output circuit 40 is electrically connected to the second end XT1 of the resonance circuit 10.

Optionally, on the basis of the above embodiment, with continuing reference to fig. 12, the oscillation circuit further includes an isolation resistor R1. The first end Q1 of the feedback amplifying circuit 20 is electrically connected to the first end XT2 of the resonant circuit 10 through the isolation resistor R1 and the current on-off control circuit 30 in sequence. The first end Q1 of the feedback amplifying circuit 20 is electrically connected to the first end of the feedback resistor R0 through the isolation resistor R1.

The isolation resistor R1 can isolate the output of the feedback amplifier circuit 20 from the pi-type network formed by the quartz crystal Y1, the first capacitor C0 and the second capacitor C1. The isolation resistor R1 can suppress high-frequency spurious oscillation to obtain a clean output signal; the drive power of the quartz crystal is reduced to prevent the allowable drive power of the quartz crystal from being exceeded.

Optionally, on the basis of the above embodiment, with continued reference to fig. 12, the current on-off control circuit 30 includes a second switch S2 and a first resistor R2. A first end of the second switch S2 and a first end of the first resistor R2 are electrically connected to the first end XT2 of the resonant circuit 10; the second terminal of the second switch S2 and the second terminal of the first resistor R2 are electrically connected to the first terminal Q1 of the feedback amplifier circuit 20 through the isolation resistor R1; the control terminal of the second switch S2 is electrically connected to the first control circuit 42; the first control circuit 42 is used for controlling the second switch S2 to be turned on or off periodically after the resonant circuit 10 reaches the first preset oscillation state.

The resistance of the first resistor R2 is relatively large. The first control circuit 42 is configured to control the second switch S2 to turn off when the pulse current output circuit 40 outputs a current to the resonant circuit 10 after the resonant circuit 10 reaches the first preset oscillation state, and the first resistor R2 will act to enable a current blocking state between the first terminal XT2 of the resonant circuit 10 and the first terminal Q1 of the feedback amplifying circuit 20. The first control circuit 42 is configured to control the second switch S2 to be turned on and the first resistor R2 to be short-circuited to be inactive when the pulse current output circuit 40 does not output current to the resonant circuit 10 after the resonant circuit 10 reaches the first preset oscillation state, so that a current flows between the first terminal XT2 of the resonant circuit 10 and the first terminal Q1 of the feedback amplifying circuit 20. The first control circuit 42 is operable to control the second switch S2 to be turned on and the first resistor R2 to be short circuited before the resonant circuit 10 reaches the first predetermined oscillation state, so that no current will flow between the first terminal XT2 of the resonant circuit 10 and the first terminal Q1 of the feedback amplifier circuit 20. The second switch S2 may include a metal-oxide-semiconductor (MOS) Transistor, a Bipolar Junction Transistor (BJT) Transistor, a relay, or the like.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. An oscillating circuit, comprising: the circuit comprises a resonant circuit, a feedback amplification circuit, a current on-off control circuit and a pulse current output circuit;

the first end of the resonant circuit is electrically connected with the first end of the feedback amplifying circuit through the current on-off control circuit; the pulse current output circuit is electrically connected with the resonance circuit; the current on-off control circuit is used for enabling the first end of the resonant circuit and the first end of the feedback amplifying circuit to be in a through-current state and a current-blocking state periodically after the resonant circuit reaches a first preset oscillation state; the pulse current output circuit is used for outputting current to the resonant circuit when the resonant circuit reaches a first preset oscillation state and a current on-off control circuit enables a current blocking state to be formed between the first end of the resonant circuit and the first end of the feedback amplification circuit.

2. The oscillating circuit according to claim 1, wherein the pulse current output circuit is configured to not output a current to the resonant circuit after the resonant circuit reaches the first preset oscillating state and when a current is passed between the first terminal of the resonant circuit and the first terminal of the feedback amplifying circuit through the current on-off control circuit, and before the resonant circuit reaches the first preset oscillating state;

3. The oscillating circuit of claim 1, wherein the pulsed current output circuit comprises a first direct current source, a first transistor, and a first control circuit, wherein the first direct current source is electrically connected to a first pole of the first transistor; a second pole of the first transistor is electrically connected to the resonant circuit; the first control circuit is electrically connected with a control electrode of the first transistor; the first control circuit is used for controlling the first transistor to be conducted when the resonant circuit reaches a first preset oscillation state and a current on-off control circuit enables a current blocking state to be formed between the first end of the resonant circuit and the first end of the feedback amplification circuit.

4. The oscillating circuit of claim 3, wherein the first control circuit comprises a clock signal generating circuit and a free-wheeling pulse generating circuit, wherein an input of the clock signal generating circuit is electrically connected to the resonant circuit; the output end of the clock signal generating circuit is electrically connected with the input end of the follow current pulse generating circuit; the output end of the free-wheeling pulse generation circuit is electrically connected with the control electrode of the first transistor.

5. The oscillation circuit according to claim 4, wherein the freewheel pulse generating circuit includes a signal delay circuit, an nor gate circuit, and a first inverter; the input end of the signal delay circuit and the first input end of the NOR gate circuit are both electrically connected with the output end of the clock signal generating circuit; the output end of the NOR gate circuit is electrically connected with the output end of the follow current pulse generating circuit through the first inverter;

the signal delay circuit includes a plurality of second inverters connected in series.

6. The oscillating circuit according to claim 3, wherein the current on-off control circuit comprises a first switch; wherein a first end of the first switch is electrically connected with a first end of the resonant circuit; the second end of the first switch is electrically connected with the first end of the feedback amplifying circuit; the control end of the first switch is electrically connected with the first control circuit; the first control circuit is used for controlling the first switch to be periodically switched on or switched off after the resonant circuit reaches a first preset oscillation state.

7. The oscillation circuit of claim 1, wherein the feedback amplification circuit comprises: the feedback resistor, the second current source and the amplifying circuit; the first end of the feedback resistor is electrically connected with the first end of the feedback amplifying circuit; the second end of the feedback resistor is electrically connected with the second end of the resonant circuit; the first end of the amplifying circuit is electrically connected with the second end of the feedback resistor; the second end of the amplifying circuit is electrically connected with the first end of the feedback amplifying circuit; the second current source is electrically connected to a second terminal of the amplification circuit.

8. The oscillating circuit of claim 7, wherein the amplifying circuit is a transconductance tunable amplifying circuit, wherein a transconductance of the amplifying circuit before the resonant circuit reaches a second predetermined oscillation state is greater than a transconductance of the amplifying circuit after the resonant circuit reaches the second predetermined oscillation state;

and/or the second current source is an adjustable current source, wherein the current output by the second current source is greater than the current output by the second current source after the resonant circuit reaches the second preset oscillation state before the resonant circuit reaches the second preset oscillation state.

9. The oscillation circuit according to claim 8, wherein the amplification circuit includes a second transistor, a third transistor, a fourth transistor, and a second control circuit;

a control electrode of the second transistor and a control electrode of the third transistor are electrically connected with a first end of the amplifying circuit; a first pole of the second transistor and a first pole of the third transistor are electrically connected with the second end of the amplifying circuit; a second pole of the second transistor is grounded; a second pole of the third transistor is electrically connected to the first pole of the fourth transistor; a second pole of the fourth transistor is grounded; a control electrode of the fourth transistor is electrically connected with the second control circuit; the size of the third transistor is larger than that of the second transistor; the second control circuit is used for controlling the fourth transistor to be conducted before the resonant circuit reaches a second preset oscillation state; after the resonant circuit reaches a second preset oscillation state, controlling the fourth transistor to be switched off;

the second current source includes a first direct current source unit, a second direct current source unit, and a fifth transistor;

the first direct current source unit is electrically connected with the second end of the amplifying circuit; the second direct current source unit is electrically connected to a first pole of the fifth transistor; a second pole of the fifth transistor is electrically connected to a second terminal of the amplifying circuit; a control electrode of the fifth transistor is electrically connected with the second control circuit; the second control circuit is used for controlling the fifth transistor to be conducted before the resonant circuit reaches a second preset oscillation state; and after the resonant circuit reaches a second preset oscillation state, controlling the fifth transistor to be switched off.

10. The oscillating circuit according to claim 9, wherein the second control circuit comprises an oscillation state identifying circuit and a selection signal generating circuit, wherein an output terminal of the oscillation state identifying circuit is electrically connected to an input terminal of the selection signal generating circuit; a first output terminal of the selection signal generation circuit is electrically connected to a control electrode of the fourth transistor; a second output terminal of the selection signal generation circuit is electrically connected to a control electrode of the fifth transistor.

11. The oscillating circuit according to claim 1, wherein the resonant circuit comprises a crystal, a first capacitor and a second capacitor, wherein a first terminal of the crystal is connected to ground via the first capacitor; the second end of the crystal is grounded through the second capacitor; a first end of the crystal is electrically connected with a first end of the resonant circuit; a second end of the crystal is electrically connected to a second end of the resonant circuit;

the pulse current output circuit is electrically connected with the first end of the resonance circuit; or, the pulse current output circuit is electrically connected with the second end of the resonance circuit.