GB2136651A - Improvements in or relating to oscillators - Google Patents

Abstract

A crystal oscillator (10) including a basic oscillator stage (16), a comparator stage (18), and a TTL output stage (20) has the amplifying transistor gate (26) of the comparator stage (18) connected to the input node (21) of the basic oscillator stage (16) to improve the duty cycle. A load transistor (M7) for the amplifying transistor (M6) of the comparator (18) is connected as a stably biased source-follower to permit symmetrical square-wave output over a wide range of supply voltages. The gate of the load transistor (M7) may be connected to the output node 22 of the inverter (M1, M2) of the basic oscillator stage (16), and is an active load. <IMAGE>

Description

SPECIFICATION Improvements in or relating to oscillators This invention relates to oscillators, and finds application, for example, in MOS (Metal-Oxide Semiconductor) or other field effect transistor technology oscillators suitable for integration with other circuit sections of a larger integrated MOS digital circuit.

There are a variety of circuits for processing digital electrical signals, such as communication signals, which require clock pulses for their operation. Such clock pulses are typically generated by an oscillator circuit which includes an amplifying device and a fundamental resonance frequency generator, such as a quartz crystal, connected as a series or shunt element within a feedback network which is connected across the amplifying device.

Circuits which operate in a charge redistribution, or switched capacitor mode are generally MOS circuits and need fortheirfunctioning a train of clock pulses provided by an oscillator. It is desirable that this oscillator be integrated as a subcircuit on the same substrate.

Recent developments in the design of MOS circuits have lead to smalier design rules--that is, smaller dimensions for the devices and their interconnecting elements. This permits more devices to be integrated on a single chip. The increased device density on a chip brings with it the problem of markedly increased power dissipation. As a result, the dissipated power of a circuit frequently is a limitation on the packing density of the devices on th chip. The need to reduce the power dissipation has led to a preference for lower supply voltages for the circuits. There exists a need for a crystal oscillator capable of operating at these lower supply voltages.

According to this invention an oscillator includes an oscillator stage having a network for generating a bias voltage, and a resonating element coupled to an input node of an amplifier, a comparator stage having an input node coupled to the input node of the amplifier, and an output stage coupled to the comparator stage.

This arrangement results in more accurate tracking of the threshold voltage of the comparator stage with the d.c. (direct current) component of its driving voltage and thereby improves the duty cycle of the complete oscilator.

The comparator stage may include a load device which is source-follower connected. This further improves the tracking of the comparator threshold with the oscillator stage bias conditions and shortens the slewing time of the comparator stage output voltage to the threshold voltage of the output stage.

Both of these benefits contribute to improved control over the duty cycle of the square wave output.

The source-follower device can share a biasing circuit with the oscillator stage if the amplifying device in this stage is connected so that it inverts the signal in transmitting it. Alternatively, it can be driven as an active load by connecting it to the output node of the oscillator stage if the amplifying device in this stage is connected so that it inverts the signal in transmitting it.

The invention will now be described by way of example with reference to the accompanying drawings, in which: Figure l is a schematic circuit diagram of an oscillator embodying the invention; and Figure 2 a schematic circuit diagram of the oscillator of Figure 1 modified so that the comparator stage includes an active load transistor.

Referring now to Figure 1, an oscillator 10 includes positive and grounded voltage supply rails 12, 14, respectively. Between the supply rails 12, there are connected as stages, in order, a basic oscillator 16 such as a Pierce-type or Colpitts-type oscillator, a comparator 18, and a TTL output circuit 20. All the transistors M1 - M11 of the oscillator 10 are N conductivity-type conduction channel MOS devices.

The transistors M1, M3, M6, M8 and M11 are enhancement mode devices. The remaining ones are depletion mode devices. The positive supply rail 12 is at a voltage VDD. The bulk material of all the transistors is integral with the substrate bulk and is at the voltage Vss, which is of a less positive value than VDD and would generally be of the same magnitude as VDD, but opposite in sign.

The basic oscillator stage 16 includes an inverter amplifier formed by the transistors M1 and M2. The transistor M1 a transconductance transistor which has its source connected to the grounded supply rail 14 and its drain connected to the source and gate of the depletion mode transistor M2. The depletion mode transistor M2 has its drain connected to the positive supply rail 12.

A biasing network biases the inverter within the basic oscillator stage 16 to an initial state of greaterthan-unity gain. There is enough on-chip and stray capacitance to provide the additional phase shift around the feedback loop needed to make oscillation occur. The biasing network includes the depletion mode transistor M4, which has its drain connected to the positive supply rail 12 and its gate and source connected to the gate and drain of the enhancement mode transistor M3, which in turn has its source tied to the grounded supply rail 14. The transistors M4, M3 function to set the d.c. voltage at the gate of the transconductance transistor M1.A depletion mode transistor M5, which is connected into the circuit as a two-terminal resistance element of the biasing network, has its drain tied to the source of transistor M4 and its gate and source coupled to the gate of the transconductance transistor M1. The node 21 at the gate of the transistor Ml is considered the signal input node for the inverter and for the basic oscillator stage 16 itself, whereas the node 22 at drain of the transistor M1 and the source of the transistor M2 is considered a signal output node of that stage 16.

Connected between the node 21 and the grounded supply rail 14 there is a loop-gain shaping capacitor 24. A quartz crystal resonance element 25 is coupled between the node 21 and the node 22 to produce a narrow-band feedback loop to provide the fundamental frequency-setting resonance for the basic oscillator stage 16 and to thereby result in the generation of an approximately sinusoidal waveform at the node 21. The preferred crystal for the element 25 in one application is a colorburst type which has a fundamental resonance frequency of 3.5 mHz (mega-Hertz).

The transistor M5, which acts as a large resistor, forms a high frequency blocking element to increase the gain margin of the oscillating feedback loop by preventing the biasing network from loading down the signal node 21 This feature permits the use of moderate conduction channel width/length ratios in the transistors M3 and M4. This saves bias current and yet still produces close tracking of the M1 quiescent, bias current with the transistor M3 current and tracking of the transistor M2 drain-to-source voltage with the transistor M4 drain-to-source voltage. In this regard, it is important that the channel lengths of transistors M1 and M2 equal those of transistors M3 and M4, respectively in order to provide a sufficiently stable start-up bias voltage at the node 22.

The node 21 of the basic oscillator stage 16 is coupled to the gate 26 of the enhancement mode amplifying transistor M6, which is the input terminal of the comparator stage 18. The drain of the amplifying transistor M6 is connected through an optional voltage swing-limiting resistance element 27 to the source of the load transistor M7, which in turn has its drain tied to the positive supply rail 12.

The gate of the load transistor M7 is tied to either the common node 29 of the transistors M4 and M5 or the basic oscillator stage output terminal 22. At some disadvantage in terms of the final output duty cycle, but some advantage in terms of manufacturing yield, it may alternatively be tied to the positive supply rail 12.

The TTL output stage 20 includes the four transistors M8, M9, M10, Ml 1. The gates of transistors M8 and M11 are connected to the node 28, which is the output of the comparator stage 18. Their drains are connected to the respective sources of the load transistors M10, M9, and their sources are tied to the grounded supply rail 14. The load transistors M9, M10, with their drains connected to the positive supply rail 12, both have their gates connected to the source of the load transistor M10. The source of the load transistor M9 and the drain of the transconductance transistor M11 lead to an output terminal 30 for the oscillator 10. The TTL output stage 20 is typical of subcircuits presently used in MOS integrated cir cuit.

It would be consistent with the designs of previous oscillators to connect the principal input node 26 of the comparator stage 18 to the output node 22 of the basic oscillator stage 16. In Pierce-type oscillators this output node 22 can provide a higher signal voltage amplitude than the input node 21 of the basic oscillator stage 16. However, in the design of the oscillator 10 it is recognized that for improving the duty cycle of the oscillator 10 it is desirable to have the threshold voltage of the comparator stage 18 match the d.c. (direct current) voltage in the steady state condition of that node of the basic oscillator stage 16 to which the comparator input node is connected. Since the transistors M1 and M6 have similar diffusions and channel lengths, their currents track very precisely in the neighborhood of the bias states.Therefore, a substantially 50% duty cycle of the TTL output, which means essentially an output voltage that spends equal times above and below a central level, can be well determined by appropriate design parameters for the various load transistors M4, M3, M2, and M7. This is in contrast to previous designs for oscillators of this general type, in which it was necessary either to match the threshold voltage of the comparator amplifying device (corresponding to the inverter stage transistors M6 and M7 in the oscillator 10) with the steady stage state d.c. at the output node of the basic oscillator stage (corresponding to the node 22 in the oscillator 10) or else to introduce a d.c. coupling capacitor and additional biasing elements.Such a matching is difficult and imprecise, since it is dependent on the amplitude of the basic oscillator output and therefore is affected by non-linearities in that output. The signal waveform at node 21 is more purely sinusoidal than the waveform at node 22. In the design of the oscillator 10, the connection of the input node 26 of the comparator stage 18 to the input node 21 of the basic oscillator stage 16 affords tighter control of the duty cycle. This results in improved reliability of the TTL output duty cycle and permits simplification of the circuit.

It would also be consistent with the design of previous oscillators to connectthe gate of the load transistor M7 of the comparator stage 18 to its own source. The connection of this gate to the common node of the bias network transistors M3 and M4 in the oscillator 10 converts the load transistor M7 to a source-follower connected load device. The term "source-follower connected" as applied to an MOS transistor means herein that the drain is connected to a supply voltage, the gate is an input node connected to a constant or varying input voltage, and the source is an output node. The mismatch between the comparator threshold and the bias voltage at node 21 that is produced by variation of the power supply voltages is thereby reduced.This improves power supply noise rejection as well as permitting operation of a fixed design over a wide range of supply voltages. The oscillator 10 can operate at a relatively low total supply voltage, as little as 2 volts. While the load transistor M7 is advantageously a depletion mode device, it could also be in the form of an enhancement mode device adapted in known ways.

It is a feature of the oscillator 10 that the basic oscillator stage 16 is coupled to the TTL output stage 20 through the special comparator stage 18 to provide the desired characteristic 50% output duty cycle to within a few percentage points. This makes feasible in the circuit 10 the use of the Pierce network topology with its inherent high tolerance to parasitics and permits the entire oscillator circuit 10 to be realized with NMOS technology and without significant start-up problems. The oscillating frequency of the oscillator circuit 10 is not limited to that of the particular crystal element 25, which in this particular circuit is external to the integrated circuit itself, but can indeed be made another desired frequency by supplying an appropriate alternate resonator, such as a passive resonator network, between the input node 21 and output node 22 of the inverter.

In Figure 2 there is shown an oscillator 32 which has elements denoted by the same reference symbols as those of the oscillator 10 of Figure 1 and which is identical in all respects, except that in the oscillator 32 the gate of the load transistor M7 of the comparator 18 is tied to the drain ofthe transcon- ductance transistor M1 of the basic oscillator stage 16, that being the output node 22 of the inverter of the basic oscillator stage 16. With this arrangement, the load transistor M7 is an active load, with the effect that the duty cycle of the oscillator is further increased. However, the use of this arrangement is feasible only where the positive supply voltage VDD at the positive supply voltage rail 12 is low enough to permit the gate voltage of the load transistor M7 to drop to a level which leaves the transconductance transistor M8 and M11 in their OFF state. If the VDD is too high, the load transistor M7 will pull the gates of these transconductance transistors up too far to permit the transistor M6 to turn transistors M8 and M11 OFF during the next half cycle of operation. It therefore becomes advantageous to connect the transistor M7 gate as in Figure 1 to establish a stable predetermined maximum gate voltage for M7 via the biasing network.

Claims (5)

1. An oscillator including an oscillator stage having a network for generating a bias voltage, and a resonating element coupled to an input node of an amplifier, a comparator stage having an input node coupled to the input node of the amplifier, and an output stage coupled to the comparator stage.

2. An oscillator as claimed in claim 1 wherein the amplifier is an inverter including a transconductance transistor having its source coupled to a voltage supply rail and its drain coupled to bias means, the amplifier input node including a control electrode of the transconductance transistor.

3. An oscillator as claimed in claim 1 or 2 wherein the comparator stage includes a sourcefollower-connected load transistor coupled between a voltage supply rail and the drain of an amplifying transistor of the comparator stage, the load transistor having its gate coupled to a node of the bias voltage generating network.

4. An oscillator as claimed in claim 2 wherein the comparator stage includes an active load transistor coupled between a voltage supply rail and the drain of an amplifying transistor of the comparator stage, the load transistor having its gate coupled to the drain of the transconductance transistor.

5. An oscillator substantially as herein described with reference to Figure 1 or 2 of the accompanying drawings.