CN100581056C - Stable oscillator without influence of temperature variation and power supply voltage variation - Google Patents
Stable oscillator without influence of temperature variation and power supply voltage variation Download PDFInfo
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- CN100581056C CN100581056C CN200610143515A CN200610143515A CN100581056C CN 100581056 C CN100581056 C CN 100581056C CN 200610143515 A CN200610143515 A CN 200610143515A CN 200610143515 A CN200610143515 A CN 200610143515A CN 100581056 C CN100581056 C CN 100581056C
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Abstract
The invention provides a comparator for a oscillator circuit with a self bias reference voltage. The comparator includes: a depleted metal oxide semiconductor transistor network which forms constant current equivalent connection, wherein a gate electrode and a source electrode which belong to the depleted metal oxide semiconductor transistor are connected; a enhanced metal oxide semiconductor transistor network, wherein a drain electrode or a source electrode of the enhanced metal oxide semiconductor transistor is connected with the depleted metal oxide semiconductor transistor in series, and a gate electrode terminal can receive a input voltage. The comparator outputs a high level signal when the input voltage is lower than the reference voltage and a low level signal when the input voltage is higher than the reference voltage. Moreover, the oscillator circuit with the comparator ensures that the reference voltage is independent from changes of external voltage source and temperature.
Description
Technical field
The present invention relates to a pierce circuit, relate in particular to the pierce circuit that a kind of stability is not subjected to external power source and influence of temperature change.
Background technology
Oscillator (oscillator), generally be applied to producing (frequency generator) circuit etc. such as phase-locked loop (phase-locked loop), frequency synthesizer (frequency synthesizer) and frequency, along with popularizing and needs of communication and consumption electronic products, more widely scholar's research and industrial quarters are used, and its operating characteristic is to utilize the variation of input signal and the output wave mode that produces different frequency.
In other words, produce the electric oscillation phenomenon of repetitive vibrations electric signal (for example string ripple or square-wave signal), be vibration (oscillation), ask for an interview Fig. 1, be a loop circuit (closeloop) oscillating circuit 100 block schematic diagrams, this loop circuit oscillating circuit 100 satisfies Barkhausen condition (BarkhausenCriteria), and just: loop gain is 1 (A (j ω
0) β (j ω
0)=1), phase deviation is 0 (∠ A (j ω
0) β (j ω
0)=0 °), then described loop circuit oscillating circuit will vibrate at ω
0On the frequency.
Realize that described loop circuit oscillating circuit 100 has multiple variation and possibility, mainly can be divided into following a few class: harmonic oscillator (harmonic oscillator), relaxation oscillator (relaxation oscillator) and crystal (crystal) oscillator etc., but also not as limit.
At first, harmonic wave (sine wave) oscillator is under the situation that does not add input signal, relies on circuit self-oscillation and produces the circuit of sinewave output voltage.Its basic principle is that an amplifier is received in the output of a filter, the output of described amplifier is taken back the input of described filter again.When the moment that the power supply of this amplifier begins to supply, has only noise (noise) in the output of amplifier.Described noise passes to this filter, makes in the noise that the specific part frequency is filtered comes out, and appears at the output of this filter.The output of this filter is received this amplifier input terminal again, and therefore filtered signal amplifies by this amplifier, enters this filter circuit filtering again.Above-mentioned steps constantly repeats, till output signal is desired signal.
Harmonic oscillator can utilize different amplifications and filtering mode to be implemented, therefore many different implementation methods are arranged, such as Hartley oscillator, Colpitts oscillator, Clapp oscillator, Pierce crystal oscillator, phaseshift oscillator, RC oscillator and Wien-Bridge oscillator and LC oscillator etc., but also not as limit.
In addition, relaxation oscillator is mainly used to produce the non-sinusoidal waveform output signal, as square wave or triangular wave.Relaxation oscillator has the non-linear element of transistor etc., can periodically the energy that is stored in electric capacity or the inductance be discharged, and makes signal output waveform moment change.
The relaxation oscillator that produces square wave can be used in the clock signal of preface to logical circuit (for example timer, counter etc.).It is to produce the horizontal reflection signal in benchmark, the cathode ray tube in oscilloscope or TV that the oscillator of output triangular wave (or claiming sawtooth waveforms) was generally used for time.In frequency generator, triangular wave also is commonly used to integer to export near sinusoidal wave signal.Relaxation oscillator also is a kind of flip-flop (multivibrator).
One crystal oscillator can be used for and filter coupler, and with the stable oscillation stationary vibration frequency, crystal oscillator has good frequency stability and temperature factor, and frequency accuracy is very high, but its output tuning range is narrow, has also therefore limited its purposes.
In order to increase the ability of oscillator modulation, the research of carrying out oscillator control with voltage modulation also becomes focus gradually, one voltage-controlled oscillator (Voltage-controlled oscillator, VCO) be a kind of oscillator that utilizes an input voltage to carry out frequency of oscillation control, the switch of its through a DC potential source and modulating signal (modulating signals) control one diode changes the direct capacitance value, thereby produces frequency modulating (frequency modulation) and phase modulation (phase modulation).
It should be noted that, no matter how evolution of oscillator, so long as utilize the oscillator that effect produces output wave mode signal that discharges and recharges of electronic component network (for example a capacitance network and equivalent network thereof), all can't avoid importing error and the noise effect that power supply causes, the change that its frequency characteristic also may Yin Wendu and changing.Ask for an interview Fig. 2, be a known pierce circuit schematic diagram, this pierce circuit 200 comprises comparator 210 on, once comparator 220, a flip-flop 230, a discharge transistor 240, one anti-phase out drive stage 250, one first divider resistance 260a, one second divider resistance 260b, one the 3rd divider resistance 260c, one first build-out resistor 270, one second build-out resistor 280 and an electric capacity 290.The resistance of wherein said divider resistance is identical, and Vdd represents the dc voltage value imported, and the evoked potential that therefore should go up comparator 210 is 2/3Vdd, and the evoked potential of this time comparator 220 then is 1/3Vdd.When power supply begins to put on described pierce circuit 200, described electric capacity 290 charges by described build-out resistor 270 and 280, this moment, described comparator 220 down ordered about described anti-phase out drive stage 250 outputs one high level signal by described flip-flop 230, and close described discharge transistor 240, make described electric capacity 290 continue to charge.When the cross-pressure on this electric capacity 290 reaches 2/3Vdd, the described comparator 210 output high level signals of going up, make described flip-flop 230 order about described anti-phase out drive stage 250 outputs one low level signal, and the described discharge transistor 240 of conducting, with this, described electric capacity 290 is by 280 discharges of described second build-out resistor.When the cross-pressure on this electric capacity 290 is reduced to 1/3Vdd once again, restart above-mentioned charge step.
Fig. 2 A is the Vc charging and discharging curve and the Vo curve of output of loop circuit oscillating circuit.Because the charging and discharging currents of described pierce circuit 200 and comparative voltage (1/3Vdd and 2/3Vdd) can change with Vdd, so the frequency of described pierce circuit 200 can change with Vdd.
Summary of the invention
One of the object of the invention is to provide a comparator that can be used for oscillator (comparator), comprise a depletion most (depletion MOS) network and an emos (enhanced MOSFET) network, wherein said voltage comparator has a comparative voltage of the self-bias voltage (Self Bias) that is independent of the external voltage variation.
Another object of the present invention is to provide a Voltagre regulator, described Voltagre regulator makes described reference voltage be independent of external voltage source variation and variations in temperature.
Another object of the present invention is to provide a comparator that can be used for oscillator, comprise a depletion most, described comparator utilizes temperature characterisitic relative between element to make a comparative voltage have independent (temperature independent) characteristic of temperature.
Another object of the present invention is to provide a oscillator, utilize described comparator element to be independent of the comparative voltage that external voltage changes, make the frequency of oscillation of described oscillator not be subjected to the external voltage variable effect with a comparator element.
Another object of the present invention is to provide a oscillator, utilize described comparator element to be independent of the reference voltage of variations in temperature, make the frequency of oscillation of described oscillator not be subjected to influence of temperature change with a comparator element.
Another object of the present invention is to provide a oscillator, can control the characteristic of described oscillator by the technological design of described comparator element with a comparator element.
To achieve these goals, the invention provides a comparator, this comparator comprises: a depletion most network, and form the constant current source equivalence and connect, connect between a grid of wherein said depletion most and one source pole; An and enhancement most network, one drain electrode of wherein said enhancement most or one source pole are connected with described depletion most, the one gate terminal can receive an input voltage, when described input voltage is lower than described reference voltage, described comparator is exported a high level signal, when described input voltage was higher than described reference voltage, described comparator was exported a low level signal.
In addition, the present invention also provides a pierce circuit, and this pierce circuit comprises:
One current source provides described pierce circuit a required charging current;
One capacitance network is connected in a reference node with described current source, utilizes described current source to charge;
One switch is connected in described reference node with described capacitance network, controls the switching of charge/discharge pattern in the described oscillator;
One comparator, be connected in described reference node with described switch, reference voltage with only self-bias voltage, described comparator comprises: a depletion most network, form the constant current source equivalence and connect, connect between a grid of wherein said depletion most and one source pole; An and enhancement most network, one drain electrode of wherein said enhancement most or one source pole are connected with described depletion most, the one gate terminal can receive the voltage of described capacitance network, when the voltage of described capacitance network is lower than described reference voltage, described comparator is exported a high level signal, when the voltage of described capacitance network was higher than described reference voltage, described comparator was exported a low level signal;
One anti-phase network is connected with described switch and described comparator respectively, receives the signal of described comparator output and exports an inversion signal to control described switch.
In described pierce circuit, comprising:
Described current source output is independent of an electric current of voltage source variation so that described electric capacity is charged.
The signal of described comparator output has two class carry-out bit rank at least.
Described charging current has the characteristic that is independent of the voltage source variation.
Described current source comprises a depletion most network and two enhancement most networks.
And described depletion most network comprises at least one depletion most.
Described enhancement most network comprises at least one enhancement most.
Described anti-phase network has a delay-time characteristic of the signal variation of the described comparator output of enough reactions.
Described anti-phase network comprises the odd number inverter.
Described reference voltage can be the summation of the terminal voltage value of described depletion most network and described enhancement most network.
Described reference voltage level can be adjusted by transistor length and the width of adjusting described depletion most network and described enhancement most network.
In sum,, make described oscillator have stable properties, and have the advantage that reference voltage is independent of external voltage source variation and variations in temperature because described pierce circuit uses described comparator.
Description of drawings
Fig. 1 is a loop circuit oscillating circuit block schematic diagram;
Fig. 2 is a known pierce circuit schematic diagram;
Fig. 2 A concerns schematic diagram between output signal and electric capacity cross-pressure in the oscillator;
Fig. 3 is for being used for a comparator of a pierce circuit among the disclosed embodiment of the present invention;
Fig. 3 A is for being used for a Voltagre regulator of a pierce circuit among the disclosed embodiment of the present invention;
Fig. 3 B is the equivalent schematic of Fig. 3;
Fig. 4 one has the schematic diagram of the comparator of two enhancement mosts and two depletion mosts;
Fig. 5 is an embodiment of the disclosed pierce circuit of the present invention;
Fig. 6 is on the oscillator, the schematic diagram of capacitance voltage Vc and output voltage;
Fig. 7 is the oscillator shown in the alternate embodiment of the present invention.
The main element symbol description:
100: loop circuit oscillating circuit 200: pierce circuit
210: go up comparator 220: following comparator
230: flip-flop 240: discharge transistor
250: anti-phase out drive stage 260a: first divider resistance
260b: the second divider resistance 260c: the 3rd divider resistance
280: the second build-out resistors of 270: the first build-out resistors
290: electric capacity 30: comparator
31,31 ': the depletion most network
32,32 ': the enhancement most network
33: input 34: output
40: comparator 50: pierce circuit
51: constant current source 52: electric capacity
53: inverter 54: switch
511: enhancement most 512: enhancement most
513: depletion most 514: voltage stabilizing circuit
520: 601: the first constant current sources of node
603: the first switches of 602: the second constant current sources
604: 605: the first comparators of second switch
609: the second capacitance networks of 608: the first capacitance networks
Vdd: external power source anode Gnd: external power source negative terminal
Vo: output voltage V ref: reference voltage
Self Bias Vref: the reference comparison voltages of self-bias voltage
Self Bias Vref1: the reference comparison voltages 1 of self-bias voltage
Self Bias Vref2: the reference comparison voltages 2 of self-bias voltage
Embodiment
The present invention is described in detail below in conjunction with accompanying drawing.
Ask for an interview shown in Figure 3, for being used for a comparator (comparator) 30 of a pierce circuit among the disclosed embodiment of the present invention.This comparator 30 comprises a depletion most network 31 (depletion MOS), an enhancement most network 32 (enhanced MOSFET), an input 33 and an output 34.This depletion most network 31 and 32 on this enhancement most network be connected in series (in series), be connected to each other between the grid of this depletion most network 31 and source electrode, under this connected mode, this depletion most network 31 can be equivalent to a current source (current source).Described input 33 is connected with the grid of this enhancement most network 32, and described output 34 is connected with the grid and the source electrode of this depletion most network 31.The other end of this depletion most network 31 connects a voltage source V dd.
As Fig. 3 A, when this input 33 is connected with this output 34, disclosed circuit can be considered one and has and be independent of that external voltage source changes and the voltage stabilizing circuit of variations in temperature among Fig. 3 A, under this annexation, these output 34 output voltages equal a reference voltage Vref, this reference voltage level Vref has the characteristic that is independent of this voltage source V dd variation and variations in temperature, this reference voltage level Vref promptly equals a comparing voltage value of this comparator 30, as Fig. 3 B is the equivalent schematic of this comparator 30, can be independent of about this reference voltage Vref that external voltage source changes and the reason of variations in temperature, will be in explanation down:
At first, according to shown in Fig. 3 A as can be known, the electric current I d of this depletion most network 31 of flowing through equates with the electric current I n of this enhancement most network 32 of flowing through.Because of depletion most network 31 has an entity raceway groove (channel), and its grid is connected (Vgsd=0) with source electrode, according to its Semiconductor Physics characteristic as can be known, after this depletion most arrives saturation conditions, Id will not be subjected to the influence of external voltage source.
Therefore can get:
Id=In can know by inference again
Wherein Kd and K
nSemiconductor constant for this depletion most network 31 and this enhancement most network 32, Wd and Ld are the width and the length of this depletion most network 31, Wn and Ln are the width and the length of this enhancement most network 32, V
TdAnd V
TnVoltage threshold (threshold voltage) for this depletion most network 31 and this enhancement most network 32, Vgsn be in this enhancement most network 32 source electrode with and grid between voltage difference, this reference voltage level Vref of these output 34 outputs just, and this comparing voltage value of this comparator 30
According to above-mentioned, then:
Thus, have the knack of this operator and can find that the value of this comparative voltage is independent of voltage source V dd, and this comparative voltage can by on the technology to the adjustment of transistor length and width, obtain required comparative voltage.
This comparing voltage value of disclosed this comparator 30 of the present invention also has the characteristic that is independent of variations in temperature, generally speaking, reason is that this comparator 30 has the relative element of temperature effect simultaneously, by on the technology to the setting of parameter, the temperature effect that can make two elements produce is offseted relatively, makes the comparative voltage of this comparator 30 have the characteristic that is independent of variations in temperature.
Below narrate the circuit function mode of this comparator 30, this input 33 connects the grid of this enhancement most network 32, therefore the electric current I n to this enhancement most network 32 of flowing through has influence, when the input voltage of this input 33 during less than this comparative voltage, the current value I n that flows through this enhancement most network 32 will diminish and the feasible high value (hi) of voltage that is output as, in case the input voltage of this input 33 is during greater than this comparative voltage, the current value I n that flows through this enhancement most network 32 will increase and make output voltage be dragged down rapidly, though output voltage is reduced to a voltage low value (low) by the high value of voltage (hi) and still must be passed through the certain reaction time, right its reaction time is less relatively, make that this comparator 30 can comparative voltage be a comparative level, it is (for example high that output has two rank, low or open, pass etc.) output signal, and because this comparator 30 has the characteristic that is independent of temperature and power source change, thereby very be suitable in the enforcement of pierce circuit.
It should be noted that, though the combination that this comparator 30 is an enhancement most and a depletion most among Fig. 3, but use transistorized quantity and type (for example P type or n type) should not be considered as restriction of the present invention, haveing the knack of this operator can understand, and this comparator that the present invention discloses also can make up the enhancement most and the depletion most of relative populations.As shown in Figure 4, be one to have the schematic diagram of two enhancement mosts 32,32 ' and two depletion mosts 31,31 ' comparator 40, this comparator 40 also can be realized the function of aforementioned this comparator 30, difference wherein is, one group of enhancement most that increases in this comparator 40 and depletion most will can be this comparator 40 provides higher impedance, makes this comparator 40 more difficult power supply and influence of temperature variation of being subjected to.
Ask for an interview Fig. 5, be an embodiment of the disclosed pierce circuit of the present invention, this pierce circuit 50 comprises a constant current source 51, a comparator 40, an electric capacity 52, an inverter 53 and a switch 54.Wherein this constant current source 51 comprises an enhancement most 511,512 and a depletion most 513.This enhancement most 511 and this depletion most 513 are also formed one and are had a voltage stabilizing circuit 514 that is independent of temperature and power source change characteristic, the origin cause of formation of its characteristic is consistent with aforementioned this comparator 30, repeats no more in this.The grid of the grid of this enhancement most 511 and this enhancement most 512 is connected to each other and forms the current mirror framework, make this two enhancement most 511,512 and a depletion most 513 form this constant current source 51, these constant current source 51 outputs one electric current I m.One end of the drain electrode of this enhancement most 512 and this switch 54 is connected on the node 520, this electric capacity 52 also by this node 520 with this constant current source 51 and this switch 54 and connect.The input 33 of this comparator 40 also is connected with this electric capacity 52, this constant current source 51 and this switch 54 by this node 520.The output 34 of this comparator 40 is connected with the input of this inverter 53, and the output of this inverter 53 is connected with the other end of this switch 54.
Its mode of operation can be divided into charge mode and discharge mode, is described below now:
When the charging stage, this switch 54 turn-offs (turn off), make the electric current I m on this constant current source 51 flow to this electric capacity 52, cross-pressure Vc thereby rising on this electric capacity 52, because this input 33 of this comparator 40 is connected with this electric capacity 52 by this node 520, therefore the magnitude of voltage of this input 33 equates with Vc, also constantly raises with Vc.
When Vc is slightly larger than this comparative voltage approximately, this oscillator 50 enters discharge mode, according to previous narration to this comparator operation principle, the output of this comparator 40 switches to output one low level (low) signal, this inverter 53 receives this low level signal and exports a high level signal (high) and give this switch 54, this switch 54 thereby conducting (turn on) make these electric capacity 52 ground connection.After ground connection, the electric weight of accumulation reduces rapidly by earth terminal on this electric capacity 52, makes Vc also drop to the earth terminal magnitude of voltage fast.Thereby make the magnitude of voltage of these comparator 40 inputs be lower than this comparative voltage.Therefore, the output of this comparator 40 switches to high level (hi), and output one low level signal after the output of these inverter 53 these comparators of reception turn-offs after this switch 54 receives these low level signals.Begin another charge cycle subsequently.
In the present embodiment, this switch 54 is implemented with a reinforced electric metal-oxide semiconductor (MOS) crystal, but also not as limit, any switch of these oscillator 50 required reaction speeds that cooperated all can be used for substituting enforcement, for example electronic switch of electromagnetic type, mechanical type or other type.
In the present embodiment, for carrying out circuit integration, with one source pole and the interconnected depletion most that drains as an equivalent electric capacity, but also not as limit.
In the present embodiment, this constant current source 51 is as providing a constant charge electric current, but also not as limit, for example with constant current source 51 as a stable discharging electric current is provided.
In addition, can't react this comparator 40 variation of output signals for fear of this switch 54, this inverter 53 need have enough lag characteristics.In the present embodiment, this inverter 53 forms with the standard inverter serial connection that odd number is easy to the technology making, must understand yet have the knack of this operator, and this inverter 53 also can have the single inverter of enough time of delay to be realized.
Moreover present embodiment can be controlled the frequency of this oscillator 50 by the numerical value of control comparing voltage value, this electric current I m and this electric capacity 52.In other words, when this comparing voltage value is more little, then the cycle that discharges and recharges of this oscillator 50 is more little.Perhaps this electric current I m is big more, and then the cycle that discharges and recharges of this oscillator 50 is also more little.And when the capacitance of this electric capacity 52 more hour, then the cycle that discharges and recharges of this oscillator 50 is also more little.Otherwise when this comparing voltage value is big more, then the cycle that discharges and recharges of this oscillator 50 is big more.Perhaps this electric current I m is more little, and then the cycle that discharges and recharges of this oscillator 50 is also big more.And when the capacitance of this electric capacity 52 was big more, then the cycle that discharges and recharges of this oscillator 50 was also big more.By said method, this oscillator 50 is satisfied the needs of various systems and frequency of oscillation.
Figure 6 shows that on this oscillator 50 schematic diagram of capacitance voltage Vc and output voltage.Can find use, make the characteristic curve convergence ideal of this oscillator 50 by this comparator 40 and this constant current source 51.At first, by deciding the use of current element, make charging not be subjected to resistance to change the nonlinear state that forms because of pressure reduction.Moreover, utilize this constant current source 51 not to be subjected to the characteristic of voltage source and influence of temperature change, it is stable to make charging current be maintained.In addition, utilize this comparator 40 not to be subjected to the characteristic of voltage source and externally temperature influence, make the frequency of this oscillator 50 be maintained fixing.By above-mentioned summation influence, a charging and discharging state keeps linearity and frequency is not achieved by the oscillator of voltage source and influence of temperature change.
Figure 7 shows that the disclosed oscillator 60 of another embodiment of the present invention, this oscillator 60 comprises one first constant current source 601, one second constant current source 602, one first switch 603, a second switch 604, one first comparator 605, one second comparator 606, one first capacitance network 608, one second capacitance network 609 and an inverter 607.In the present embodiment, this first constant current source 601 is implemented with the framework of this constant current source 51, this second constant current source 602 is existing arbitrary current mirror framework, so the output current of this second constant current source 602 is able to the output current of this first constant current source 601 proportional.In addition, this first constant current source 601 in the present embodiment, this first switch 603, the annexation that this first comparator 605 and this first capacitance network are 608 is identical with the annexation of each element in this oscillator 50, and this second constant current source 602, this second switch 604, the annexation that this second comparator 606 and this second capacitance network are 609 is also identical with the annexation of each element in this oscillator 50, one end of the output of this first comparator 605 and this inverter 607, the gate terminal of this second switch 604 is connected with the other end of this inverter 607, and the output of this second comparator 606 is connected with the gate terminal of this first switch 603.Under this framework, the operation principle of this oscillator 60 is similar to this oscillator 50, but utilize the existence of this first constant current source 601, this first comparator 605, this second constant current source 602 and this second comparator 606, this oscillator 60 is controlled the high level period and the low-level period of output signal respectively, to export frequency of oscillation more accurate and that suit the requirements.It should be noted that in the present embodiment that though this inverter 607 is connected between this first comparator 605 and this second switch 604, this inverter 607 also can be connected between this second comparator 606 and this first switch 603.In addition, haveing the knack of this operator must understand, this first constant current source 601 and this second constant current source 602 can use the framework of disclosed constant current source 51 among Fig. 5 respectively, or provided the framework of these oscillator 60 constant current source to realize with any other, and do not exceed with the disclosed framework of present embodiment.
Above embodiment only is used to illustrate the present invention, but not is used to limit the present invention.
Claims (21)
1. a comparator is characterized in that, is used for pierce circuit and has the reference voltage of a self-bias voltage, comprises:
One depletion most network forms the constant current source equivalence and connects, and connects between a grid of wherein said depletion most and one source pole; And
One enhancement most network, one drain electrode of wherein said enhancement most or one source pole are connected with described depletion most, the one gate terminal can receive an input voltage, when described input voltage is lower than reference voltage, described comparator is exported a high level signal, when described input voltage was higher than described reference voltage, described comparator was exported a low level signal.
2. comparator according to claim 1 is characterized in that, when described input voltage equaled described reference voltage, described comparator was exported described reference voltage.
3. comparator according to claim 1 is characterized in that, described depletion most network comprises at least one depletion most.
4. comparator according to claim 1 is characterized in that, described enhancement most network comprises at least one enhancement most.
5. comparator according to claim 1 is characterized in that, constant current source equivalence connects between the grid that is meant described depletion most and source electrode and is connected to each other.
6. comparator according to claim 3 is characterized in that, constant current source equivalence connects between the grid that is meant described depletion most and source electrode and is connected to each other.
7. comparator according to claim 3 is characterized in that, described reference voltage can be the summation of the terminal voltage value of described depletion most network and described enhancement most network.
8. comparator according to claim 4 is characterized in that, described reference voltage can be the summation of the terminal voltage value of described depletion most network and described enhancement most network.
9. comparator according to claim 3, it is characterized in that described reference voltage level can be adjusted by transistor length and the width of adjusting described depletion most network and described enhancement most network.
10. comparator according to claim 4, it is characterized in that described reference voltage level can be adjusted by transistor length and the width of adjusting described depletion most network and described enhancement most network.
11. a pierce circuit is characterized in that, comprises:
One current source provides described pierce circuit a required charging current;
One capacitance network is connected in a reference node with described current source, utilizes described electric current to carry out charge or discharge;
One switch is connected in described reference node with described capacitance network, controls the switching of charge or discharge pattern in the described oscillator;
One comparator is connected in described reference node with described switch, has a reference voltage of a self-bias voltage, and described comparator comprises:
One depletion most network forms the constant current source equivalence and connects, and connects between a grid of wherein said depletion most and one source pole; And
One enhancement most network, one drain electrode of wherein said enhancement most or one source pole are connected with described depletion most, the one gate terminal can receive the voltage of described capacitance network, when the voltage of described capacitance network is lower than described reference voltage, described comparator is exported a high level signal, when the voltage of described capacitance network was higher than described reference voltage, described comparator was exported a low level signal; And
One anti-phase network is connected with described switch and described comparator respectively, receives the signal of described comparator output and exports an inversion signal to control described switch.
12. pierce circuit according to claim 11 is characterized in that, described current source output is independent of an electric current of voltage source variation so that described electric capacity is charged.
13. pierce circuit according to claim 11 is characterized in that, the signal of described comparator output has two class carry-out bit rank at least.
14. pierce circuit according to claim 11 is characterized in that, described charging current has the characteristic that is independent of the voltage source variation.
15. pierce circuit according to claim 11 is characterized in that, described current source comprises a depletion most network and two enhancement most networks.
16. pierce circuit according to claim 11 is characterized in that, described depletion most network comprises at least one depletion most.
17. pierce circuit according to claim 11 is characterized in that, described enhancement most network comprises at least one enhancement most.
18. pierce circuit according to claim 11 is characterized in that, described anti-phase network has a delay-time characteristic of the signal variation of the described comparator output of enough reactions.
19. pierce circuit according to claim 11 is characterized in that, described anti-phase network comprises the odd number inverter.
20. pierce circuit according to claim 11 is characterized in that, described reference voltage can be the summation of the terminal voltage value of described depletion most network and described enhancement most network.
21. pierce circuit according to claim 11, it is characterized in that described reference voltage level can be adjusted by transistor length and the width of adjusting described depletion most network and described enhancement most network.
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| CN102158203A (en) * | 2011-04-26 | 2011-08-17 | 杭州芯赛微电子有限公司 | High-accuracy resistance-capacitance (RC) oscillator |
| CN103187924A (en) * | 2011-12-30 | 2013-07-03 | 无锡华润矽科微电子有限公司 | Oscillator circuit structure |
| CN103580655B (en) * | 2012-07-24 | 2017-05-17 | 飞思卡尔半导体公司 | Comparator and relaxation oscillator with comparator |
| CN102957421A (en) * | 2012-11-22 | 2013-03-06 | 江苏格立特电子有限公司 | Frequency generator circuit without changes along with voltage |
| US20140232480A1 (en) * | 2013-02-19 | 2014-08-21 | Issc Technologies Corp. | Clock apparatus |
| CN104253587B (en) * | 2013-06-27 | 2017-10-20 | 上海东软载波微电子有限公司 | Crystal oscillator |
| EP2854293B1 (en) * | 2013-09-30 | 2016-03-30 | Micro Crystal AG | Temperature compensated timing signal generator |
| CN105515550B (en) * | 2016-01-22 | 2017-12-29 | 英麦科（厦门）微电子科技有限公司 | A kind of super low-power consumption clock circuit with high stability |
| CN106506002B (en) * | 2016-12-23 | 2023-04-28 | 江苏信息职业技术学院 | VCO circuit for realizing full amplitude of input signal based on constant current charge and discharge |
| CN108880504B (en) * | 2017-05-16 | 2021-10-08 | 博通集成电路（上海）股份有限公司 | Method for exciting crystal oscillation circuit and circuit |
| CN113794613A (en) * | 2021-09-13 | 2021-12-14 | 中车大连机车研究所有限公司 | Direct-current carrier communication module of locomotive fire-fighting controller |
| CN115395890B (en) * | 2022-09-15 | 2023-07-28 | 广东工业大学 | Temperature compensation RC oscillator circuit and application chip thereof |
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2006
- 2006-11-10 CN CN200610143515A patent/CN100581056C/en not_active Expired - Fee Related
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| CN101179266A (en) | 2008-05-14 |
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