CN113597661A - 半导体装置以及半导体装置的制造方法 - Google Patents

半导体装置以及半导体装置的制造方法 Download PDF

Info

Publication number
CN113597661A
CN113597661A CN202080022318.3A CN202080022318A CN113597661A CN 113597661 A CN113597661 A CN 113597661A CN 202080022318 A CN202080022318 A CN 202080022318A CN 113597661 A CN113597661 A CN 113597661A
Authority
CN
China
Prior art keywords
trench
region
semiconductor layer
semiconductor device
insulator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202080022318.3A
Other languages
English (en)
Inventor
泽田达郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Publication of CN113597661A publication Critical patent/CN113597661A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • H01L21/0465—Making n or p doped regions or layers, e.g. using diffusion using ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30608—Anisotropic liquid etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/38—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions
    • H01L21/383—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions using diffusion into or out of a solid from or into a gaseous phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/42—Bombardment with radiation
    • H01L21/423—Bombardment with radiation with high-energy radiation
    • H01L21/425—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/426—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
    • H01L29/66204—Diodes
    • H01L29/66212—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

半导体装置(100)，具备：半导体基板(101)；层叠于半导体基板的表面的第1导电型的半导体层(102)；形成于半导体层的表面的沟槽(104)；将沟槽的底面以及侧面覆膜的绝缘膜(107a)；将被绝缘膜覆膜的沟槽的内部填埋的导电体(108)；形成于半导体层内的第2导电型区域(102P)；和与导电体电连接且与半导体层的表面(102a)形成肖特基势垒的金属膜(109a)。第2导电型区域配置于沟槽下，在俯视观察半导体基板时收在沟槽的区域内。

Description

半导体装置以及半导体装置的制造方法
技术领域
本公开涉及具有沟槽结构的二极管、晶体管等半导体装置以及半导体装置的制造方法。
背景技术
过去，如特表2016-502270号公报中也记载的那样，已知具有沟槽结构的半导体装置，关于该沟槽结构，在位于从形成肖特基势垒的第1导电型的半导体层的表面形成的沟槽的底部的该半导体层内区域形成有第2导电型低浓度区域。
发明内容
发明要解决的课题
在上述现有的半导体装置中，在俯视观察半导体基板时，沟槽底部的第2导电型低浓度区域伸出到沟槽外。
在这样的第2导电型低浓度区域从沟槽底部伸出到外方的结构中，该第2导电型低浓度区域伸出到正向电流的导通区域，会招致导通电阻的上升，因此有时正向特性劣化。
若要提升耐压而形成上述第2导电型低浓度区域，进而将该区域形成得大，则虽然能得到耐压的提升，但会伴随导通电阻的上升。为此，难以抑制导通电阻的上升且提升耐压。
用于解决课题的手段
本公开的1个方式的半导体装置具备：半导体基板；层叠于所述半导体基板的表面的第1导电型的半导体层；形成于所述半导体层的表面的沟槽；将所述沟槽的底面以及侧面覆膜的绝缘膜；将被所述绝缘膜覆膜的所述沟槽的内部填埋的导电体；形成于所述半导体层内的第2导电型区域；和与所述导电体电连接且与所述半导体层的表面形成肖特基势垒的金属膜，所述第2导电型区域配置于所述沟槽下，在俯视观察所述半导体基板时收在所述沟槽的区域内。
本公开的1个方式的半导体装置的制造方法中，制造半导体装置，所述半导体装置具备：半导体基板；层叠于所述半导体基板的表面的第1导电型的半导体层；形成于所述半导体层的表面的沟槽；将所述沟槽的底面以及侧面覆膜的绝缘膜；将被所述绝缘膜覆膜的所述沟槽的内部填埋的导电体；形成于所述半导体层内的第2导电型区域；和与所述导电体电连接且与所述半导体层的表面形成肖特基势垒的金属膜，所述第2导电型区域配置于所述沟槽下，所述半导体装置的制造方法具备：掺杂掩模形成工序，设置覆盖所述沟槽的周围的所述半导体层的表面、和所述沟槽的底面的外缘部以及侧面且使该底面的中央部露出的绝缘体掩模图案；和掺杂工序，将所述绝缘体掩模图案作为掩模，从所述底面的中央部对所述半导体层内导入第2导电型的杂质。
附图说明
图1是用于说明本公开的第1实施方式的截面示意图。
图2是用于说明本公开的第1实施方式的截面示意图。
图3是用于说明本公开的第1实施方式的截面示意图。
图4是用于说明本公开的第1实施方式的截面示意图。
图5是用于说明本公开的第1实施方式的截面示意图。
图6是用于说明本公开的第1实施方式的截面示意图。
图7是用于说明本公开的第1实施方式的截面示意图。
图8是用于说明本公开的第2实施方式的截面示意图。
图9是用于说明本公开的第2实施方式的截面示意图。
图10是用于说明本公开的第2实施方式的截面示意图。
图11是用于说明本公开的第2实施方式的截面示意图。
图12是用于说明本公开的第2实施方式的截面示意图。
图13是用于说明本公开的第2实施方式的截面示意图。
图14是用于说明本公开的第2实施方式的截面示意图。
图15是关于正向电压以及耐压而比较本发明例和比较例的图表。
具体实施方式
以下参考附图来说明本公开的一个实施方式。
〔第1实施方式〕
首先说明第1实施方式的半导体装置的制造方法以及半导体装置。
(制造方法)
如下那样制造半导体装置。
如图1所示那样实施沟槽形成工序。即，对半导体基板101上的半导体层102形成沟槽形成用的绝缘体掩模图案103，将绝缘体掩模图案103作为掩模进行蚀刻，由此形成沟槽104。
半导体基板101是N型高浓度硅基板。半导体层102是通过外延生长法层叠于半导体基板101的表面的N型低浓度的半导体层。
绝缘体掩模图案103是用于在半导体层102的表面在沟槽的形成预定的区域进行开口的蚀刻的掩模图案。作为构成绝缘体掩模图案103的绝缘材料，能举出氧化硅、氮化硅、TEOS(四乙氧基硅烷)等。作为绝缘体掩模图案103的层叠方法，例如运用化学蒸镀(CVD)。
另外，沟槽104的数量是任意的。
半导体基板101以及半导体层102可以是SiC(碳化硅)、GaN(氮化镓)、Ga2O3(氧化镓)的任一者的半导体材料。
接下来，实施用于对沟槽104下导入P型杂质的掺杂掩模形成工序，接着实施掺杂工序。
作为掺杂掩模形成工序，首先如图2所示那样形成绝缘体层105。将绝缘体层105层叠于上述的沟槽形成工序中的绝缘体掩模图案103上。与此同时，用绝缘体层105覆盖沟槽104的底面以及侧面。作为构成绝缘体层105的绝缘材料，能举出氧化硅、氮化硅、TEOS(四乙氧基硅烷)等。作为绝缘体层105的层叠方法，例如运用化学蒸镀(CVD)。
接下来，如图3所示那样蚀刻表面整体。作为蚀刻，运用各向异性蚀刻。作为各向异性蚀刻，运用与表面垂直的纵向的蚀刻速度比与表面平行的横向的蚀刻速度快的反应性的各向异性蚀刻。
因此，如图3所示那样，能留下绝缘体层105的一部分当中附着在沟槽104的底面的外缘部104a以及侧面104b的部分的侧壁绝缘体105S，并使沟槽104的底面的中央部104c露出。这是因为，在将沟槽104的底面的中央部104c上的绝缘体通过纵向蚀刻除去时，侧壁绝缘体105S残存。
侧壁绝缘体105S由于是越靠近沟槽104的开口的部位，蚀刻越进展，因此随着从沟槽104的开口靠近底面而变厚。
另外，在沟槽104的周围的半导体层102的表面，绝缘体掩模图案103在图2所示的蚀刻前的阶段被绝缘体层105覆盖。为此，在将沟槽104的底面的中央部104c上的绝缘体通过纵向蚀刻除去时，绝缘体掩模图案103也残存。
将通过以上的各向异性蚀刻而残存的绝缘体掩模图案103和侧壁绝缘体105S合起来作为绝缘体掩模图案106。
绝缘体掩模图案106如图3所示那样成为覆盖沟槽104的周围的半导体层102的表面、和沟槽104的底面的外缘部104a以及侧面104b并使该底面的中央部104c露出的图案。将该绝缘体掩模图案106作为用于接下来的掺杂的掩模。
接下来实施掺杂工序。
如图4所示那样，将绝缘体掩模图案106作为掩模，从沟槽104的底面的中央部104c对半导体层102内导入第2导电型(本实施方式中是P型)的杂质，由此进行掺杂工序。作为杂质导入方法，运用离子注入法。由于在沟槽104内有侧壁绝缘体105S，因此，对半导体层102的离子注入被侧壁绝缘体105S限定在内侧的中央部104c。
在杂质导入后，进行退火，使P型杂质激活，形成P型区域102P。虽然通过本退火，在半导体层102内，P型杂质比离子注入时更扩散，但关于横向，收在沟槽104的宽度内，P型区域102P不会伸出到比沟槽104更外方。
接下来如图5所示那样，除去绝缘体掩模图案106，如图6所示那样，将绝缘膜(热氧化膜)107a、107b形成在包括沟槽104内在内的半导体层102的表面，之后，在沟槽104内埋设导电体108。导电体108的材料可以是多晶硅或金属材料。
进而，在除去沟槽104的周围的绝缘膜107b后，如图7所示那样，使肖特基金属膜109a与半导体层102的表面102a接合来形成肖特基势垒，进而形成表面电极金属膜109b来将肖特基金属膜109a和导电体108连接。进而形成背面电极金属膜110。
(半导体装置)
能通过例如以上的制造方法制造的半导体装置100，如图7所示那样具备：第1导电型且比较高浓度的半导体基板101；层叠于半导体基板101的表面的第1导电型且比较低浓度的半导体层102；形成于半导体层102的表面的沟槽104；将沟槽104的底面以及侧面覆膜的绝缘膜107a；将通过绝缘膜107a覆膜的沟槽104的内部填埋的导电体108；形成于半导体层102内的第2导电型区域102P；和与导电体108电连接且与半导体层102的表面102a形成肖特基势垒的肖特基金属膜109a。
第2导电型区域102P配置于沟槽104下，在俯视观察半导体基板101时收在沟槽104的区域内。
进一步来说，在俯视观察半导体基板101时，第2导电型区域102P不与沟槽104的区域的外缘相接，从该外缘隔开距离，收在沟槽104的区域内。
第2导电型区域102P收在沟槽104的底部中的宽度内，沟槽104的底部的边角未被第2导电型区域102P覆盖。沟槽104的底部的边角可以是圆型。在反向电压施加时有缓和局部的电场的集中的作用。
半导体层102内的区域、即俯视观察半导体基板101时为沟槽104的区域外的区域，被第1导电型(N型)的区域占据。因此，能在肖特基结下较大地确保正向电流的导通区域。
第2导电型区域102P是通过离子注入形成的区域。出现在沟槽104的底面的离子注入面相当于图4中的中央部104c。在俯视观察半导体基板101时，中央部104c不与沟槽104的区域的外缘相接，收在沟槽104的区域内。出现在沟槽104的底面的离子注入面102b比图7中的第2导电型区域102P的最终的扩散宽度窄。将图4中的侧壁绝缘体105S的轮廓线在图7中也用虚线示出。其内侧相当于离子注入面102b。
第2导电型区域102P的第2导电型(P型)的杂质浓度分布，在从沟槽104的底面远离的深度(图7的点102M)取最高值。这虽然是缘于离子注入，但通过在深的位置形成峰值，电解缓和效果变得良好。
虽然P型杂质也从离子注入面102b向横向扩散，但比离子注入面102b更为低浓度化地分布。
半导体装置100除了能应用在SBD(Schottky diode，肖特基二极管)中以外，还能应用在MOSFET(metal-oxide-semiconductor field-effect transistor，金属氧化物半导体场效应晶体管)、IGBT(Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管)等中。
在构成MOSFET的情况下，Pbody(P体)、栅极等形成于中心部，表面电极金属膜109b成为源极电极，背面电极金属膜110成为漏极电极。在IGBT的情况下，进一步运用P型高浓度基板作为半导体基板101，表面电极金属膜109b成为发射极电极，背面电极金属膜110成为集电极电极。
〔第2实施方式〕
接下来说明第2实施方式的半导体装置的制造方法以及半导体装置。
(制造方法)
如下那样制造半导体装置。
如图8所示那样形成沟槽形成工序。即，对半导体装置201上的半导体层202形成沟槽形成用的绝缘体掩模图案203，将绝缘体掩模图案203作为掩模进行蚀刻，由此形成沟槽204。
半导体基板201是N型高浓度硅基板。半导体层202是通过外延生长法层叠于半导体基板201的表面的N型低浓度的半导体层。
绝缘体掩模图案203是用于在半导体层202的表面在沟槽的形成预定的区域进行开口的蚀刻的掩模图案。作为构成绝缘体掩模图案203的绝缘材料，能举出氧化硅、氮化硅、TEOS(四乙氧基硅烷)等。作为绝缘体掩模图案203的层叠方法，例如运用化学蒸镀(CVD)。
另外，沟槽204的数量是任意的。
接下来，实施用于在沟槽204下导入P型杂质的掺杂掩模形成工序，接着实施掺杂工序。
作为掺杂掩模形成工序，首先如图9所示那样形成绝缘体层205。将绝缘体层205层叠于上述的沟槽形成工序中的绝缘体掩模图案203上。与此同时用绝缘体层205覆盖沟槽204的底面以及侧面。作为构成绝缘体层205的绝缘材料，能举出氧化硅、氮化硅、TEOS(四乙氧基硅烷)等。作为绝缘体层205的层叠方法，例如运用化学蒸镀(CVD)。
接下来，如图10所示那样蚀刻表面整体。作为蚀刻，运用各向异性蚀刻。作为各向异性蚀刻，运用与表面垂直的纵向的蚀刻速度比与表面平行的横向的蚀刻速度快的反应性的各向异性蚀刻。
因此，如图10所示那样，能将绝缘体层205的一部分当中附着在沟槽204的底面的外缘部204a以及侧面204b的部分的侧壁绝缘体205S留下，并使沟槽204的底面的中央部204c露出。这是因为，在将沟槽204的底面的中央部204c上的绝缘体通过纵向蚀刻除去时，侧壁绝缘体205S残存。
侧壁绝缘体205S由于是越靠近沟槽204的开口的部位，蚀刻越进展，因此随着从沟槽204的开口靠近底面而变厚。
另外，在沟槽204的周围的半导体层202的表面，绝缘体掩模图案103在图9所示的蚀刻前的阶段被绝缘体层205覆盖。为此，在将沟槽204的底面的中央部204c上的绝缘体通过纵向蚀刻除去时，绝缘体掩模图案203也残存。
将通过以上的各向异性蚀刻残存的绝缘体掩模图案203和侧壁绝缘体205S合起来作为绝缘体掩模图案206。
绝缘体掩模图案206如图10所示那样成为覆盖沟槽204的周围的半导体层202的表面、和沟槽204的底面的外缘部204a以及侧面204b、且使该底面的中央部204c露出的图案。将该绝缘体掩模图案206作为用于接下来的掺杂的掩模。
接下来实施掺杂工序。
如图11所示那样，将绝缘体掩模图案206作为掩模，从沟槽204的底面的中央部204c对半导体层202内导入第2导电型(本实施方式中是P型)的杂质P，由此进行掺杂工序。作为杂质导入方法，运用气相扩散法。由于在沟槽204内有侧壁绝缘体205S，因此，对半导体层202的杂质P的导入面被侧壁绝缘体205S限定在内侧的中央部204c。
在杂质导入后，进行退火使P型杂质激活，形成P型区域202P。通过本退火，虽然在半导体层202内P型杂质比导入时更扩散，但关于横向，收在沟槽204的宽度内，P型区域202P不会伸出到比沟槽204更外方。
接下来，如图12所示那样，除去绝缘体掩模图案206，如图13所示那样，将绝缘膜(热氧化膜)207a、207b形成在包括沟槽204内在内的半导体层202的表面，之后在沟槽204内埋设导电体208。导电体208可以是多晶硅或金属材料。
进而，在除去沟槽204的周围的绝缘膜207b后，如图14所示那样使肖特基金属膜209a与半导体层202的表面202a接合来形成肖特基势垒，进而形成表面电极金属膜209b来将肖特基金属膜209a和导电体208连接。进而形成背面电极金属膜210。
(半导体装置)
能通过例如以上的制造方法制造的半导体装置200，如图14所示那样具备：第1导电型且比较高浓度的半导体基板201；层叠于半导体基板201的表面的第1导电型且比较低浓度的半导体层202；形成于半导体层202的表面的沟槽204；将沟槽204的底面以及侧面覆膜的绝缘膜207a；将通过绝缘膜207覆膜的沟槽204的内部填埋的导电体208；形成于半导体层202内的第2导电型区域202P；与导电体208电连接且与半导体层202的表面202a形成肖特基势垒的肖特基金属膜209a。
第2导电型区域202P配置于沟槽204下，在俯视观察半导体基板201时，收在沟槽204的区域内。
进一步来说，在俯视观察半导体基板201时，第2导电型区域202P不与沟槽204的区域的外缘相接，与该外缘隔开距离地收在该区域204内。
第2导电型区域202P收在沟槽204的底部的宽度内，沟槽204的底部的边角不被第2导电型区域202P覆盖。沟槽204的底部的边角可以是圆型。在反向电压施加时有缓和局部的电场的集中的作用。
半导体层202内的区域、即俯视观察半导体基板201时沟槽204的区域外的区域，被第1导电型(N型)的区域占据。因此，能在肖特基结下将正向电流的导通区域确保得大。
第2导电型区域202P是通过气相扩散形成的区域，出现在沟槽204的底面的杂质导入面相当于图11中的中央部204c。在俯视观察半导体基板201时，不与沟槽204的区域的外缘相接地收在沟槽204的区域内。出现在沟槽204的底面的杂质导入面202b比图14中的第2导电型区域202P的最终的扩散宽度窄。将图11中的侧壁绝缘体205S的轮廓线在图14中也通过虚线示出。其内侧相当于杂质导入面202b。
第2导电型区域202P的第2导电型(P型)的杂质浓度分布，在杂质导入面202b取最高值。这是缘于来自表面的扩散法。
虽然P型杂质从杂质导入面202b也向横向扩散，但比杂质导入面202b更为低浓度化地分布。
半导体装置200除了能应用于SBD(Schottky diode，肖特基二极管)以外，还能应用于MOSFET(metal-oxide-semiconductor field-effect transistor，金属氧化物半导体场效应晶体管)、IGBT(Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管)等。
在构成MOSFET的情况下，将Pbody、栅极等形成于中心部，表面电极金属膜209b成为源极电极，背面电极金属膜210成为漏极电极。在IGBT的情况下，进一步运用P型高浓度基板作为半导体基板201，表面电极金属膜209b成为发射极电极，背面电极金属膜210成为集电极电极。
〔作用效果〕
根据以上说明的实施方式，通过配置于沟槽下的第2导电型区域缓和反向电压施加时的电场并提升耐压。另外，能确保肖特基结下的正向电流的导通区域，并能抑制导通电阻的上升。
〔特性比较〕
在图15示出关于比较例和本发明例的VF-VRM特性。VF是正向电流IF＝10〔A〕时的正向电压。VRM表示耐压，是反向漏电流IRM＝0.1〔mA〕时的反向电压。
在图15的图表中，出现了表示遵循上述第1实施方式的本发明例的SBD的特性的点13。在图15的图表中，点14表示P型区域102P伸出到沟槽104的外方的比较例的SBD的特性。其他条件与本发明例的SBD(点13)共通。
在图15的图表中，直线16表示没有P型区域102P的比较例的SBD的特性。其他条件与本发明例的SBD(点13)共通。直线16表示越使半导体层102的N型杂质浓度降低、VF以及VRM越是直线上升的倾向。
在P型区域102P伸出到沟槽104的外方的比较例的SBD当中点14的SBD中，相对于没有P型区域102P的比较例的SBD，能提升耐压VRM。但代价是正向电压VF上升。
在P型区域102P伸出到沟槽104的外方的比较例的SBD中，耐压VRM提升，并且正向电压VF上升。这是因为，虽然能得到耐压的提升，但会伴随导通电阻的上升。
与此相对，在本发明例的SBD(点13)，能抑制导通电阻的上升并提升耐压，能达成与比较例比较更低的VF和更高的耐压VRM。
以上说明了本公开的实施方式，但本实施方式在作为示例而示出的，能以其他种种形态实施，能在不脱离发明的要旨的范围内，进行构成要素的省略、置换、变更。
产业上的可利用性
本公开能利用在半导体装置以及半导体装置的制造方法中。
附图标记的说明
100 半导体装置
101 半导体基板
102 半导体层(N型)
102P 第2导电型区域(P型)
104 沟槽
107a 绝缘膜(热氧化膜)
108 导电体
109a 肖特基金属膜
109b 表面电极金属膜
110 背面电极金属膜

Claims (10)

1.一种半导体装置，其特征在于，具备：
半导体基板；
层叠于所述半导体基板的表面的第1导电型的半导体层；
形成于所述半导体层的表面的沟槽；
将所述沟槽的底面以及侧面覆膜的绝缘膜；
将被所述绝缘膜覆膜的所述沟槽的内部填埋的导电体；
形成于所述半导体层内的第2导电型区域；和
与所述导电体电连接且与所述半导体层的表面形成肖特基势垒的金属膜，
所述第2导电型区域配置于所述沟槽下，在俯视观察所述半导体基板时收在所述沟槽的区域内。
2.根据权利要求1所述的半导体装置，其特征在于，
在俯视观察所述半导体基板时，所述第2导电型区域不与所述沟槽的区域的外缘相接，收在该区域内。
3.根据权利要求1或2所述的半导体装置，其特征在于，
所述半导体层内的区域、即俯视观察所述半导体基板时所述沟槽的区域外的区域，被第1导电型的区域占据。
4.根据权利要求1～3中任一项所述的半导体装置，其特征在于，
通过离子注入形成所述第2导电型区域。
5.根据权利要求4所述的半导体装置，其特征在于，
出现在所述沟槽的底面的离子注入面，在俯视观察所述半导体基板时，不与所述导电体的区域的外缘相接，收在该区域内。
6.根据权利要求1～5中任一项所述的半导体装置，其特征在于，
所述第2导电型区域的第2导电型的杂质浓度分布，在从所述沟槽的底面远离的深度取最高值。
7.根据权利要求1～3中任一项所述的半导体装置，其特征在于，
通过基于气相生长法的第2导电型的杂质的导入来形成所述第2导电型区域。
8.根据权利要求1～7中任一项所述的半导体装置，其特征在于，
所述绝缘膜是热氧化膜。
9.一种半导体装置的制造方法，其特征在于，所述半导体装置具备：
半导体基板；
层叠于所述半导体基板的表面的第1导电型的半导体层；
形成于所述半导体层的表面的沟槽；
将所述沟槽的底面以及侧面覆膜的绝缘膜；
将被所述绝缘膜覆膜的所述沟槽的内部填埋的导电体；
形成于所述半导体层内的第2导电型区域；和
与所述导电体电连接且与所述半导体层的表面形成肖特基势垒的金属膜，
所述第2导电型区域配置于所述沟槽下，
所述半导体装置的制造方法具备：
掺杂掩模形成工序，设置覆盖所述沟槽的周围的所述半导体层的表面、和所述沟槽的底面的外缘部以及侧面且使该底面的中央部露出的绝缘体掩模图案；和
掺杂工序，将所述绝缘体掩模图案作为掩模，从所述底面的中央部对所述半导体层内导入第2导电型的杂质。
10.根据权利要求9所述的半导体装置的制造方法，其特征在于，
在所述掺杂掩模形成工序之前具备：沟槽形成工序，在所述半导体层的表面形成在所述沟槽的形成预定的区域开口的绝缘体掩模图案，将该绝缘体掩模图案作为掩模来蚀刻所述半导体层，由此形成所述沟槽，
在所述掺杂掩模形成工序中，形成层叠于所述沟槽形成工序中的所述绝缘体掩模图案上且覆盖所述沟槽的底面以及侧面的绝缘体层，将该绝缘体层各向异性蚀刻，来留下该绝缘体层的一部分即附着在所述沟槽的底面的外缘部以及侧面的部分的绝缘体，并使所述沟槽的底面的中央部露出。
CN202080022318.3A 2019-03-29 2020-03-26 半导体装置以及半导体装置的制造方法 Pending CN113597661A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2019065351 2019-03-29
JP2019-065351 2019-03-29
PCT/JP2020/013680 WO2020203650A1 (ja) 2019-03-29 2020-03-26 半導体装置及び半導体装置の製造方法

Publications (1)

Publication Number Publication Date
CN113597661A true CN113597661A (zh) 2021-11-02

Family

ID=72668859

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202080022318.3A Pending CN113597661A (zh) 2019-03-29 2020-03-26 半导体装置以及半导体装置的制造方法

Country Status (4)

Country Link
US (1) US20220149174A1 (zh)
JP (1) JPWO2020203650A1 (zh)
CN (1) CN113597661A (zh)
WO (1) WO2020203650A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2024047430A (ja) * 2022-09-26 2024-04-05 株式会社タムラ製作所 ショットキーバリアダイオード

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002009082A (ja) * 2000-06-21 2002-01-11 Fuji Electric Co Ltd 半導体装置および半導体装置の製造方法
JP2004006723A (ja) * 2002-03-25 2004-01-08 Toshiba Corp 高耐圧半導体装置及びその製造方法
JP2010147399A (ja) * 2008-12-22 2010-07-01 Shindengen Electric Mfg Co Ltd トレンチショットキバリアダイオード
JP2012243985A (ja) * 2011-05-20 2012-12-10 Shindengen Electric Mfg Co Ltd 半導体装置及びその製造方法
JP2014236171A (ja) * 2013-06-05 2014-12-15 ローム株式会社 半導体装置およびその製造方法
CN106206755A (zh) * 2015-05-27 2016-12-07 丰田自动车株式会社 肖特基势垒二极管

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004053760A1 (de) * 2004-11-08 2006-05-11 Robert Bosch Gmbh Halbleitereinrichtung und Verfahren für deren Herstellung
JP4935160B2 (ja) * 2006-04-11 2012-05-23 株式会社デンソー 炭化珪素半導体装置およびその製造方法
JP5482701B2 (ja) * 2011-03-17 2014-05-07 富士電機株式会社 半導体素子
JP5881322B2 (ja) * 2011-04-06 2016-03-09 ローム株式会社 半導体装置
US9018698B2 (en) * 2012-11-16 2015-04-28 Vishay General Semiconductor Llc Trench-based device with improved trench protection
JP6152861B2 (ja) * 2015-02-09 2017-06-28 トヨタ自動車株式会社 ダイオードの製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002009082A (ja) * 2000-06-21 2002-01-11 Fuji Electric Co Ltd 半導体装置および半導体装置の製造方法
JP2004006723A (ja) * 2002-03-25 2004-01-08 Toshiba Corp 高耐圧半導体装置及びその製造方法
JP2010147399A (ja) * 2008-12-22 2010-07-01 Shindengen Electric Mfg Co Ltd トレンチショットキバリアダイオード
JP2012243985A (ja) * 2011-05-20 2012-12-10 Shindengen Electric Mfg Co Ltd 半導体装置及びその製造方法
JP2014236171A (ja) * 2013-06-05 2014-12-15 ローム株式会社 半導体装置およびその製造方法
CN106206755A (zh) * 2015-05-27 2016-12-07 丰田自动车株式会社 肖特基势垒二极管

Also Published As

Publication number Publication date
WO2020203650A1 (ja) 2020-10-08
JPWO2020203650A1 (zh) 2020-10-08
US20220149174A1 (en) 2022-05-12

Similar Documents

Publication Publication Date Title
US10121892B2 (en) Semiconductor device
US10861966B2 (en) Vertical trench power devices with oxygen inserted Si-layers
CN108604602B (zh) 半导体装置及半导体装置的制造方法
US9059284B2 (en) Semiconductor device
US8269272B2 (en) Semiconductor device and method for manufacturing the same
US9917184B2 (en) Semiconductor component that includes a clamping structure and method of manufacturing the semiconductor component
US9064952B2 (en) Semiconductor device
JP2013125827A (ja) 半導体装置およびその製造方法
CN103972287A (zh) 半导体装置
CN110875310B (zh) 高压cmos器件与共享隔离区的集成
JP2007207784A (ja) 半導体装置
US8017494B2 (en) Termination trench structure for mosgated device and process for its manufacture
KR20160150349A (ko) 전력 반도체 소자
WO2017145548A1 (ja) 化合物半導体装置およびその製造方法
EP3608969A1 (en) Oxygen inserted si-layers for reduced substrate dopant outdiffusion in power devices
JP2013214551A (ja) 半導体装置及びその製造方法
US20170200822A1 (en) Double gate trench power transistor and manufacturing method thereof
US10396196B1 (en) Semiconductor devices
US9825125B2 (en) Silicon carbide semiconductor device and manufacturing method of silicon carbide semiconductor device
TWI702722B (zh) 半導體裝置及半導體裝置之製造方法
JP5037103B2 (ja) 炭化珪素半導体装置
CN109888015A (zh) Ldmos器件及其制备方法
CN113597661A (zh) 半导体装置以及半导体装置的制造方法
US20220181504A1 (en) Semiconductor device and production method for semiconductor device
JP2006086549A (ja) 電界効果トランジスタ及びその製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination