CN113594119A - Semiconductor package and method of manufacturing the same - Google Patents

Semiconductor package and method of manufacturing the same Download PDF

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Publication number
CN113594119A
CN113594119A CN202110714998.1A CN202110714998A CN113594119A CN 113594119 A CN113594119 A CN 113594119A CN 202110714998 A CN202110714998 A CN 202110714998A CN 113594119 A CN113594119 A CN 113594119A
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Prior art keywords
chip
pillars
substrate
semiconductor package
pads
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CN202110714998.1A
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CN113594119B (en
Inventor
郜振豪
杨清华
唐兆云
赖志国
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Suzhou Huntersun Electronics Co Ltd
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Suzhou Huntersun Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

The invention provides a semiconductor package and a method of manufacturing the same, comprising: a substrate having a plurality of substrate pads on a top surface; a chip having a plurality of chip pads on a bottom surface; a plurality of stacked structures, each stacked structure including a bump and a solder ball, respectively electrically connecting one of the plurality of substrate pads with a corresponding one of the plurality of chip pads; a plurality of first pillars at edges of the bottom surface of the chip, aligned in a vertical direction with the plurality of alignment marks or the plurality of second pillars on the top surface of the substrate; and an encapsulant encapsulating the chip, the plurality of stacked structures, the plurality of first pillars, and/or the plurality of second pillars. According to the semiconductor package and the manufacturing method thereof, the positioning column is arranged at the bottom of the chip and is combined with the positioning column on the substrate for use, so that the excessive melting of soldering tin is effectively prevented in the reflow soldering process, and the soldering reliability and the alignment precision are improved.

Description

Semiconductor package and method of manufacturing the same
Technical Field
The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a semiconductor package and a method of manufacturing the same capable of effectively improving soldering reliability and alignment accuracy.
Background
The semiconductor Integrated Circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have resulted in generations of ICs, each of which has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (e.g., the number of interconnected devices per chip area) has generally increased, while geometry (e.g., the smallest component or line that can be produced using a fabrication process) has decreased. Such a scaling down process generally provides benefits by increasing production efficiency and reducing associated costs.
Flip chip packaging technology is an interconnect based on small chip size, high I/O density, and excellent electrical and thermal performance. The chip is attached to the circuit board by preparing solder balls or bumps on the chip bonding pads. In this technique, metal pads are formed on the upper surface of an integrated circuit ("IC") wafer, as opposed to ICs formed on the wafer. Solder bumps or copper bumps are deposited on the metal pads. The ICs are then cut from the wafer into IC dies. The diced IC die is flipped over and placed on a carrier substrate such that the solder bumps face the connections on the carrier substrate. The solder bumps are then re-melted, for example using thermosonic bonding or optionally a reflow process, so that the IC is securely coupled to the carrier substrate. An electrical connection is formed between the melted solder bump and the connection member. The small space between the IC die and the underlying carrier substrate is underfilled with an electrically insulating glue IC.
In the production and packaging process of the device, chip welding is a key control procedure in the packaging process, and the process aims to interconnect the metal bumps (bump) on the surface of the chip downwards on the substrate so as to form good ohmic contact and a good heat dissipation path between the chip and the packaging substrate. However, during the reflow soldering process, due to the unreasonable setting of the reflow soldering temperature, a large number of soldering defects are generated, such as excessive melting of the solder balls on the metal bumps, cracking of the metal bumps, and misalignment between the bumps and the solder balls, which all affect the performance and reliability of the product.
Disclosure of Invention
Accordingly, the present invention is directed to overcoming the above technical obstacles and providing an innovative semiconductor package and method for manufacturing the same, which makes the soldering of the molten solder more uniform and reduces the solder reflow defect of the bump and the risk of solder offset between the bump and the pad of the substrate, thereby improving the signal transmission and reliability of the product.
The present invention provides a semiconductor package, comprising:
a substrate having a plurality of substrate pads on a top surface;
a chip having a plurality of chip pads on a bottom surface;
a plurality of stacked structures, each stacked structure including a bump and a solder ball, respectively electrically connecting one of the plurality of substrate pads with a corresponding one of the plurality of chip pads;
a plurality of first pillars at edges of the bottom surface of the chip, aligned in a vertical direction with the plurality of alignment marks or the plurality of second pillars on the top surface of the substrate;
and an encapsulant encapsulating the chip, the plurality of stacked structures, the plurality of first pillars, and/or the plurality of second pillars.
Wherein, the material of the first columns and/or the second columns is metal, alloy of metal, conductive nitride of metal, conductive oxide of metal and combination thereof, the metal is selected from any one of Al, Cu, Mo, W, Pt, Ni, Cr, Nd, Ti, Ta, Hf, Zr, Mg and Zn.
The cross-sectional shapes and/or sizes of the first cylinders and the second cylinders are the same.
The heights of the first columns are greater than the heights of the bumps in the stacked structures, or the heights of the first columns are smaller than the heights of the bumps in the stacked structures and the heights of the second columns are greater than the heights of the solder balls in the stacked structures.
Wherein, the side walls of the first columns and/or the second columns are vertical and have alignment patterns.
Wherein, the bottom surfaces of the first columns and the top surfaces of the second columns are respectively provided with a concave-convex structure, rough textures or magnetic components.
The first columns are symmetrically distributed about the center of the chip, and/or the second columns are symmetrically distributed about the center of the substrate.
The present invention also provides a method of manufacturing a semiconductor package, comprising the steps of:
step 1, forming a plurality of first columns at the upper edge of the bottom surface of a chip;
step 2, forming a stacking structure on each of a plurality of chip bonding pads on the bottom surface of the chip, wherein the stacking structure comprises a bump and a welding ball;
step 3, inversely installing the chip on the substrate to enable the plurality of first columns to be aligned with the plurality of alignment marks or the plurality of second columns on the top surface of the substrate in the vertical direction;
and 4, performing reflow soldering, fixing the chip on the substrate by using the solder balls, and electrically connecting one of the substrate pads with a corresponding one of the chip pads through the bumps and the solder balls in the stacked structure.
Wherein, after the step 2 and before the step 3, a step 2B is further included, and a plurality of second pillars are formed on the top surface of the substrate.
Wherein step 2 is performed before or simultaneously with step 1.
According to the semiconductor package and the manufacturing method thereof, the positioning column is arranged at the bottom of the chip and is combined with the positioning column on the substrate for use, so that the excessive melting of soldering tin is effectively prevented in the reflow soldering process, and the soldering reliability and the alignment precision are improved.
The stated objects of the invention, as well as other objects not listed here, are met within the scope of the independent claims of the present application. Embodiments of the invention are defined in the independent claims, with specific features being defined in the dependent claims.
Drawings
The technical solution of the present invention is explained in detail below with reference to the accompanying drawings, in which:
FIG. 1 shows a cross-sectional view of a semiconductor package according to one embodiment of the present invention;
FIG. 2 shows a plan view of the bottom surface of a chip in the semiconductor package of FIG. 1;
fig. 3 shows a cross-sectional view of a semiconductor package according to another embodiment of the present invention;
fig. 4 shows a plan view of the top surface of the substrate in the semiconductor package of fig. 3; and
fig. 5 shows a flow chart of a method of manufacturing a semiconductor package according to an embodiment of the invention.
Detailed Description
Features of the present invention and technical effects thereof will be described in detail below with reference to the accompanying drawings in conjunction with exemplary embodiments, disclosing a semiconductor package and a method of manufacturing the same that effectively improves reflow reliability and alignment accuracy. It is noted that like reference numerals refer to like structures and that the terms "first", "second", "upper", "lower", and the like as used herein may be used to modify various device structures. These modifications do not imply a spatial, sequential, or hierarchical relationship to the structures of the modified devices unless specifically stated.
As shown in fig. 1, a semiconductor package according to a preferred embodiment of the present invention includes a substrate 1, a chip 2, and an encapsulation resin 7. The substrate 1 is, for example, a Printed Circuit Board (PCB) including a plurality of insulating layers made of an organic or inorganic material, a metal interconnection layer or a redistribution layer (RDL) disposed between the respective insulating layers as necessary for wiring, and a plurality of pads (not shown in fig. 1, denoted by 4B in fig. 4) on a top surface of the substrate. In addition, the substrate 1 may also be a lead frame (lead frame) with metal traces encapsulated by an encapsulant and pads on the top surface of the traces. The chip 2 may be a variety of commonly used semiconductor chips such as silicon-based logic/memory circuits fabricated on a CMOS process, power devices fabricated on a bipolar or BiMOS process, Light Emitting Diodes (LEDs) based on III-V or II-VI compounds, and the like. The chip 2 has a bottom surface which includes a plurality of metal traces or pads 3, for example made of Al, Cu, Mo, W, Pt, Ni and alloys thereof, which serve as input/output of electrical signals inside the chip 2.
A plurality of first pillars 4A are formed in the peripheral region (at least two corners of the upper left corner and the lower right corner in fig. 2) of the bottom surface of the chip 2, for example, by the same manufacturing process as the metal traces or pads 3 to a greater thickness, or by bonding, pressing, or adhering on dummy pads in the peripheral region. Preferably, the first pillars 4A are made of a hard conductive material so as to provide sufficient mechanical support during subsequent reflow soldering, prevent excessive solder melting on the bumps, facilitate improved alignment accuracy during flip-chip mounting due to the hard material having aligned sidewalls, and further prevent warpage of the chip edges during reflow soldering due to good thermal conductivity, thereby further improving alignment accuracy. For example, the first pillar 4A material is a metal, a metal alloy, a conductive metal nitride, a conductive metal oxide, and combinations thereof, wherein the metal is selected from Al, Cu, Mo, W, Pt, Ni, Cr, Nd, Ti, Ta, Hf, Zr, Mg, Zn, and the like. Although the first column 4A is shown in fig. 2 as having a circular cross section, it is also possible to use a rectangular shape, a square shape, a trapezoidal shape, a triangular shape, an elliptical shape, a star shape, a diamond shape, a cross shape, other polygonal shapes such as a pentagonal shape, a hexagonal shape, an octagonal shape, an irregular shape, or the like. The posts 4A have vertical sidewalls and further preferably have a vertically distributed pattern (e.g., grooves or protrusions, such as the lateral edges of the posts) on the sidewalls to improve the accuracy of visual or optical/laser alignment during the alignment process using the vertical sidewalls and their sidewall patterns. Further, although the first pillars 4A are shown as two on the symmetrical corners in fig. 2, a larger number may be selected, and it is preferable that the plurality of first pillars 4A are distributed symmetrically (line symmetry, point symmetry, or rotational symmetry) about the geometric center of the chip 2, thereby improving the efficiency of the inversion alignment process.
Metal bumps (bump)5, preferably Cu, Sn, Al, Ag, Ni, Au, Pt, Pd and alloys thereof, are provided on the pads 3 of the chip 2 by plating, electroless plating, bonding, pressing, conductive adhesive bonding, etc., for providing sufficient mechanical support during flip-chip reflow soldering of the chip 2, avoiding solder ball displacement, and at the same time preferably also a solderable material to promote bonding strength with solder balls. The metal bump 5 has a solder ball 6 formed thereon, and the solder ball 6 is brought into contact with and soldered to a pad on the surface of the substrate 1 to realize physical and electrical connection. The metal bumps 6 are generally circular in cross-section so that the solder balls 6 are evenly distributed over the bump surface during reflow without overflowing from the sharp corners or protrusions to the sidewalls. The material of the solder balls 6 may be a lead-based solder or a lead-free solder. Preferably, the solder balls 6 and the pads on the top surface of the substrate 1 may also have flux or solder paste (not shown) therebetween, so as to improve the reliability of soldering with the substrate.
As shown in fig. 1, when the first pillar 4A is formed only on the bottom of the chip 2, the height of the first pillar 4A is preferably greater than the height of the metal bump 5, so that the gap between the pillar 4A and the substrate 1 is small enough, for example, 5 μm or less and 100nm or less, so that even if a small amount of the solder balls 6 is melted and excessively displaced during the reflow process to cause local suspension or distortion/tilting, the horizontal surface of the chip 2 is not excessively tilted due to the support of the first pillar 4A, thereby ensuring the reliability of the soldering.
Further, in order to improve the alignment accuracy in the flip chip mounting process of the chip 2, in another preferred embodiment shown in fig. 3, 4, a plurality of second pillars 4B are provided on the top surface of the substrate 1, which are the same in material, shape, size and forming process as the first pillars 4A, and which are arranged in a plane so that each first pillar 4A overlaps with a respective second pillar 4B in the thickness direction (z-axis or substrate normal direction) when the chip 2 is flip-mounted on the top surface of the substrate 1, thereby enabling the first pillar 4A and the second pillar 4B to be vertically aligned. In this embodiment, the height of the first pillar 4A may be slightly smaller than the metal bump 5 (e.g., the height difference is 200nm or less) and the height of the second pillar 4B is slightly larger than the thickness of the solder ball 6 (e.g., the height difference is 200nm or more), so that the gap existing between the pillars 4A-4B is 5 μm or less and 100nm or less, thereby achieving the same mechanical supporting strength as described in the embodiment shown in fig. 1. The side wall of the second pillar 4B is also vertical and preferably has a pattern that is the same as or corresponds to the pattern of the side wall of the first pillar 4A, thereby facilitating visual or optical/laser alignment from the side, and solving the problem of difficulty in measuring horizontal displacement from the top surface of the flip chip 2 in the conventional process. In other preferred embodiments of the present invention, the height of the second post 4B may be further reduced until it is reduced to become an alignment mark on the surface of the substrate 1 (e.g., only within 50nm of the top surface of the substrate 1), at which time the alignment mark needs to be enlarged in planar size to extend beyond the boundary of the top surface of the chip 2 to facilitate viewing the alignment from the top.
In other preferred embodiments of the present invention, the surfaces of the first pillar 4A opposite to the second pillar 4B (e.g., the bottom surface of the first pillar 4A and the top surface of the second pillar 4B) may be further provided with engaging structures, such as a combination of concave portions and convex portions, or other complementary rough textures, etc., so as to enhance the mechanical bonding strength between the pillars, and advantageously avoid warpage or tilting at the edges of the chip 2. Further, magnetic members (e.g., ferromagnetic film layers, not shown) having different polarities may be respectively provided (e.g., by welding, bonding, adhering, plating, etc.) on the bottom surface of the first pillar 4A and the top surface of the second pillar 4B, thereby improving the efficiency of the operation in the flip-chip mounting process by magnetic attraction.
As shown in fig. 5, the method for manufacturing the semiconductor package according to the above preferred embodiment of the present invention includes the steps of:
step 1, forming a plurality of first pillars 4A on the bottom surface of a chip 2;
step 2, forming a bump 5 on the pad 3 on the bottom surface of the chip 2, the top of the bump 5 preferably having solder, and step 2 may be performed simultaneously with step 1 or before step 1;
preferably, step 2B is inserted to form a plurality of second pillars 4B on the top surface of the substrate 1, and step 2B may be performed before steps 1 and 2;
step 3, inversely installing the chip 2 on the substrate 1, wherein a plurality of first cylinders 4A are overlapped and aligned with the alignment marks or a plurality of second cylinders 4B on the substrate 1 in a plan view, a device suction nozzle is adopted to core from the wafer and simultaneously paste the bumps 5 of the chip on the substrate welding area, and the image identification reference points are the first cylinders 4A on the chip and the alignment marks or the second cylinders 4B on the substrate;
step 4, performing reflow soldering, and fixing the chip 2 on the substrate 1 by using the solder balls 6.
Thereafter, the first pillar 4A on the chip 2 and the second pillar 4B on the substrate 1 need not be removed or disassembled, and are molded in a post-process following the product flow, for example, by applying the encapsulating resin 7 to the entire apparatus, completing the encapsulation and performing quality inspection.
In step 3, the flip-chip connection method may be solder bonding, thermocompression bonding, thermosonic bonding, or adhesive bonding, so long as the chip 2 can be flipped and aligned with the substrate 1.
According to the semiconductor package and the manufacturing method thereof, the first column is arranged at the bottom of the chip and is combined with the second column on the substrate for use, so that excessive melting of soldering tin is effectively prevented in the reflow soldering process, and the soldering reliability and the alignment precision are improved.
While the invention has been described with reference to one or more exemplary embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the disclosure without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the disclosed device structure and its method of manufacture will include all embodiments falling within the scope of the present invention.

Claims (10)

1. A semiconductor package, comprising:
a substrate having a plurality of substrate pads on a top surface;
a chip having a plurality of chip pads on a bottom surface;
a plurality of stacked structures, each stacked structure including a bump and a solder ball, respectively electrically connecting one of the plurality of substrate pads with a corresponding one of the plurality of chip pads;
a plurality of first pillars at edges of the bottom surface of the chip, aligned in a vertical direction with the plurality of alignment marks or the plurality of second pillars on the top surface of the substrate;
and an encapsulant encapsulating the chip, the plurality of stacked structures, the plurality of first pillars, and/or the plurality of second pillars.
2. The semiconductor package of claim 1, wherein the material of the first and/or second pillars is a metal selected from any of Al, Cu, Mo, W, Pt, Ni, Cr, Nd, Ti, Ta, Hf, Zr, Mg, Zn, an alloy of the metal, a conductive nitride of the metal, a conductive oxide of the metal, and combinations thereof.
3. The semiconductor package of claim 1, wherein the first plurality of pillars is the same as the second plurality of pillars in cross-sectional shape and/or size.
4. The semiconductor package of claim 1, wherein a height of the first plurality of pillars is greater than a height of the bumps in the plurality of stacked structures, or the height of the first plurality of pillars is less than the height of the bumps in the plurality of stacked structures and the height of the second plurality of pillars is greater than a height of the solder balls in the plurality of stacked structures.
5. The semiconductor package of claim 1, wherein sidewalls of the first plurality of pillars and/or the second plurality of pillars are vertical and have an alignment pattern.
6. The semiconductor package according to claim 1, wherein bottom surfaces of the first pillars and top surfaces of the second pillars have a concavo-convex structure, a rough texture, or a magnetic member, respectively.
7. The semiconductor package according to claim 1, wherein the plurality of first pillars are symmetrically distributed about a center of the chip, and/or the plurality of second pillars are symmetrically distributed about a center of the substrate.
8. A method of manufacturing a semiconductor package, comprising the steps of:
step 1, forming a plurality of first columns at the upper edge of the bottom surface of a chip;
step 2, forming a stacking structure on each of a plurality of chip bonding pads on the bottom surface of the chip, wherein the stacking structure comprises a bump and a welding ball;
step 3, inversely installing the chip on the substrate to enable the plurality of first columns to be aligned with the plurality of alignment marks or the plurality of second columns on the top surface of the substrate in the vertical direction;
and 4, performing reflow soldering, fixing the chip on the substrate by using the solder balls, and electrically connecting one of the substrate pads with a corresponding one of the chip pads through the bumps and the solder balls in the stacked structure.
9. The method of manufacturing a semiconductor package according to claim 8, further comprising a step 2B of forming a plurality of second pillars on the top surface of the substrate after the step 2 and before the step 3.
10. The manufacturing method of the semiconductor package according to claim 8, wherein step 2 is performed before or simultaneously with step 1.
CN202110714998.1A 2021-06-25 2021-06-25 Semiconductor package and method of manufacturing the same Active CN113594119B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117912963A (en) * 2024-03-13 2024-04-19 荣耀终端有限公司 Ball planting tool, ball planting equipment and ball planting method

Citations (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5834323A (en) * 1997-01-21 1998-11-10 Accurel Systems International Corporation Method of modification and testing flip-chips
EP0902330A1 (en) * 1997-09-16 1999-03-17 Sanei Giken Co., Ltd. Photomask and alignment method
JPH11191530A (en) * 1997-12-25 1999-07-13 Mitsutoyo Corp Alignment mark device
JPH11340277A (en) * 1998-05-22 1999-12-10 Nec Corp Semiconductor chip loading substrate, semiconductor device and method for loading semiconductor chip to semiconductor chip loading substrate
JP2001015552A (en) * 1999-07-02 2001-01-19 Shinkawa Ltd Flip-chip mounting method
US20020079577A1 (en) * 1999-12-03 2002-06-27 Ho Tony H. Advanced electronic package
US20030146518A1 (en) * 1999-02-24 2003-08-07 Junichi Hikita Semiconductor device of chip-on-chip structure, assembling process therefor, and semiconductor chip to be bonded to solid surface
US20040232537A1 (en) * 2002-12-28 2004-11-25 Kobrinsky Mauro J. Method and structure for interfacing electronic devices
KR20050023119A (en) * 2003-08-29 2005-03-09 동부아남반도체 주식회사 reticle for manufacturing semiconductor and reticle pre-alignment method using it
JP2005353857A (en) * 2004-06-11 2005-12-22 Matsushita Electric Works Ltd Semiconductor device and flip-chip mounting method
WO2005122706A2 (en) * 2004-05-31 2005-12-29 Joon-Mo Kang Method of aligning semiconductor device and semiconductor structure thereof
US20070001318A1 (en) * 2005-06-29 2007-01-04 Robert Starkston Soldering a die to a substrate
US20070216041A1 (en) * 2006-03-20 2007-09-20 Robert Patti Fiducial scheme adapted for stacked integrated circuits
JP2010003927A (en) * 2008-06-20 2010-01-07 Fujitsu Ltd Circuit substrate and method for manufacturing the same
US20100283144A1 (en) * 2007-12-26 2010-11-11 Steve Xin Liang In-situ cavity circuit package
US20110215466A1 (en) * 2010-03-04 2011-09-08 Hung-Hsin Hsu Flip chip package maintaining alignment during soldering
US20120086123A1 (en) * 2010-10-06 2012-04-12 Samsung Electronics Co., Ltd. Semiconductor assembly and semiconductor package including a solder channel
US20120153462A1 (en) * 2010-12-17 2012-06-21 Sony Corporation Semiconductor device and method of manufacturing semiconductor device
CN102593110A (en) * 2012-01-05 2012-07-18 三星半导体(中国)研究开发有限公司 Laminated inverted chip packaging structure of ultra-fine spacing welding plates and bottom filling material preparation method
US20120313236A1 (en) * 2011-06-09 2012-12-13 Sony Corporation Semiconductor device and manufacturing method for semiconductor device
US20130181339A1 (en) * 2012-01-12 2013-07-18 Mars Technology Multi-chip self-alignment assembly which can be used with flip-chip bonding
US20140217567A1 (en) * 2013-02-04 2014-08-07 Fujitsu Semiconductor Limited Semiconductor device and manufacturing method of the same
US20140252604A1 (en) * 2013-03-07 2014-09-11 Tohoku-Microtec Co., Ltd Stacked device and method of manufacturing the same
US20150228587A1 (en) * 2014-02-13 2015-08-13 Taiwan Semiconductor Manufacturing Company, Ltd. Concentric Bump Design for the Alignment in Die Stacking
US20160071897A1 (en) * 2013-06-07 2016-03-10 Olympus Corporation Semiconductor device, solid-state imaging device, and imaging device
CN106601672A (en) * 2016-11-28 2017-04-26 西安空间无线电技术研究所 Method for eliminating cutting burrs of film circuit
US20170373003A1 (en) * 2016-06-22 2017-12-28 Nanya Technology Corporation Semiconductor chip and multi-chip package using thereof
US20180342475A1 (en) * 2017-05-23 2018-11-29 Micron Technology, Inc. Semiconductor device assembly with die support structures
CN110061106A (en) * 2019-04-24 2019-07-26 京东方科技集团股份有限公司 Chip, target base plate, manufacturing method, chip transfer method and display device
US20190326245A1 (en) * 2018-04-18 2019-10-24 Texas Instruments Incorporated Flip chip integrated circuit packages with spacers
US11521947B1 (en) * 2021-07-14 2022-12-06 Nxp Usa, Inc. Space efficient flip chip joint design

Patent Citations (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5834323A (en) * 1997-01-21 1998-11-10 Accurel Systems International Corporation Method of modification and testing flip-chips
EP0902330A1 (en) * 1997-09-16 1999-03-17 Sanei Giken Co., Ltd. Photomask and alignment method
JPH11191530A (en) * 1997-12-25 1999-07-13 Mitsutoyo Corp Alignment mark device
JPH11340277A (en) * 1998-05-22 1999-12-10 Nec Corp Semiconductor chip loading substrate, semiconductor device and method for loading semiconductor chip to semiconductor chip loading substrate
US20030146518A1 (en) * 1999-02-24 2003-08-07 Junichi Hikita Semiconductor device of chip-on-chip structure, assembling process therefor, and semiconductor chip to be bonded to solid surface
JP2001015552A (en) * 1999-07-02 2001-01-19 Shinkawa Ltd Flip-chip mounting method
US20020079577A1 (en) * 1999-12-03 2002-06-27 Ho Tony H. Advanced electronic package
US20040232537A1 (en) * 2002-12-28 2004-11-25 Kobrinsky Mauro J. Method and structure for interfacing electronic devices
KR20050023119A (en) * 2003-08-29 2005-03-09 동부아남반도체 주식회사 reticle for manufacturing semiconductor and reticle pre-alignment method using it
WO2005122706A2 (en) * 2004-05-31 2005-12-29 Joon-Mo Kang Method of aligning semiconductor device and semiconductor structure thereof
JP2005353857A (en) * 2004-06-11 2005-12-22 Matsushita Electric Works Ltd Semiconductor device and flip-chip mounting method
US20070001318A1 (en) * 2005-06-29 2007-01-04 Robert Starkston Soldering a die to a substrate
US20070216041A1 (en) * 2006-03-20 2007-09-20 Robert Patti Fiducial scheme adapted for stacked integrated circuits
US20100283144A1 (en) * 2007-12-26 2010-11-11 Steve Xin Liang In-situ cavity circuit package
JP2010003927A (en) * 2008-06-20 2010-01-07 Fujitsu Ltd Circuit substrate and method for manufacturing the same
US20110215466A1 (en) * 2010-03-04 2011-09-08 Hung-Hsin Hsu Flip chip package maintaining alignment during soldering
US20120086123A1 (en) * 2010-10-06 2012-04-12 Samsung Electronics Co., Ltd. Semiconductor assembly and semiconductor package including a solder channel
US20120153462A1 (en) * 2010-12-17 2012-06-21 Sony Corporation Semiconductor device and method of manufacturing semiconductor device
US20120313236A1 (en) * 2011-06-09 2012-12-13 Sony Corporation Semiconductor device and manufacturing method for semiconductor device
CN102593110A (en) * 2012-01-05 2012-07-18 三星半导体(中国)研究开发有限公司 Laminated inverted chip packaging structure of ultra-fine spacing welding plates and bottom filling material preparation method
US20130181339A1 (en) * 2012-01-12 2013-07-18 Mars Technology Multi-chip self-alignment assembly which can be used with flip-chip bonding
US20140217567A1 (en) * 2013-02-04 2014-08-07 Fujitsu Semiconductor Limited Semiconductor device and manufacturing method of the same
US20140252604A1 (en) * 2013-03-07 2014-09-11 Tohoku-Microtec Co., Ltd Stacked device and method of manufacturing the same
US20160071897A1 (en) * 2013-06-07 2016-03-10 Olympus Corporation Semiconductor device, solid-state imaging device, and imaging device
US20150228587A1 (en) * 2014-02-13 2015-08-13 Taiwan Semiconductor Manufacturing Company, Ltd. Concentric Bump Design for the Alignment in Die Stacking
US20170373003A1 (en) * 2016-06-22 2017-12-28 Nanya Technology Corporation Semiconductor chip and multi-chip package using thereof
CN106601672A (en) * 2016-11-28 2017-04-26 西安空间无线电技术研究所 Method for eliminating cutting burrs of film circuit
US20180342475A1 (en) * 2017-05-23 2018-11-29 Micron Technology, Inc. Semiconductor device assembly with die support structures
US20190326245A1 (en) * 2018-04-18 2019-10-24 Texas Instruments Incorporated Flip chip integrated circuit packages with spacers
CN110061106A (en) * 2019-04-24 2019-07-26 京东方科技集团股份有限公司 Chip, target base plate, manufacturing method, chip transfer method and display device
US11521947B1 (en) * 2021-07-14 2022-12-06 Nxp Usa, Inc. Space efficient flip chip joint design

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117912963A (en) * 2024-03-13 2024-04-19 荣耀终端有限公司 Ball planting tool, ball planting equipment and ball planting method

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