CN113506792A - Semiconductor package device and method of manufacturing the same - Google Patents
Semiconductor package device and method of manufacturing the same Download PDFInfo
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- CN113506792A CN113506792A CN202110683033.0A CN202110683033A CN113506792A CN 113506792 A CN113506792 A CN 113506792A CN 202110683033 A CN202110683033 A CN 202110683033A CN 113506792 A CN113506792 A CN 113506792A
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The present disclosure relates to a semiconductor package device and a method of manufacturing the same. The semiconductor package device includes: a lead frame having opposing first and second surfaces; the first chip is arranged on the first surface, and the active surface faces the first surface; and the protective layer covers the first surface and at least part of the first chip, and at least part of the inactive surface of the first chip is exposed in a protective way. In the semiconductor packaging device, at least part of the inactive surface of the first chip is exposed out of the protective layer, so that the heat dissipation of the inactive surface of the first chip is facilitated.
Description
Technical Field
The present disclosure relates to the field of semiconductor packaging technologies, and in particular, to a semiconductor packaging device and a method for manufacturing the same.
Background
A common Advanced Embedded Active System Integration (aeasii) is to attach a non-Active surface of a chip to a lead frame and to dissipate heat of the chip through the lead frame. Since the lead frame is covered with the dielectric material, the heat dissipation capability of the lead frame is limited. As the power of the chip increases, the heat dissipation problem becomes more serious.
Disclosure of Invention
In a first aspect, the present disclosure provides a semiconductor package device, comprising:
a lead frame having opposing first and second surfaces;
the first chip is arranged on the first surface, and the active surface faces the first surface;
and the protective layer covers the first surface and at least part of the first chip, and at least part of the inactive surface of the first chip is exposed out of the protective layer.
In some optional embodiments, the apparatus further comprises:
and the circuit layer is arranged on the second surface, and the first chip is electrically connected with the circuit layer.
In some optional embodiments, the routing layer comprises a redistribution layer.
In some optional embodiments, the apparatus further comprises:
and the second chip is arranged on the second surface, the inactive surface of the second chip faces the second surface, and the second chip is electrically connected with the first chip through the circuit layer.
In some optional embodiments, the apparatus further comprises:
and the heat dissipation assembly is arranged on the inactive surface of the first chip.
In some optional embodiments, the apparatus further comprises:
and the electric connecting piece is arranged on the active surface of the first chip and penetrates through the lead frame.
In a second aspect, the present disclosure provides a semiconductor package device, comprising:
a lead frame having opposing first and second surfaces;
the first chip is arranged on the first surface, and the active surface faces the first surface;
the second chip is arranged on the second surface, and the inactive surface faces the second surface;
and the first chip is electrically connected with the second chip through the circuit layer.
In some optional embodiments, the active surface of the first chip and the active surface of the second chip both face the line layer.
In some optional embodiments, the apparatus further comprises:
and the protective layer covers the first surface and at least part of the first chip, and at least part of the inactive surface of the first chip is exposed out of the protective layer.
In some optional embodiments, the apparatus further comprises:
and the heat dissipation assembly is arranged on the inactive surface of the first chip.
In some optional embodiments, the apparatus further comprises:
and the bonding layer is arranged between the lead frame and the circuit layer and coats at least part of the active surface of the first chip, the active surface of the second chip and the second surface.
In some optional embodiments, the apparatus further comprises:
and the passive electronic element is arranged on the second surface.
In some alternative embodiments, the passive electronic component is electrically connected to the first chip.
In a third aspect, the present disclosure provides a method of manufacturing a semiconductor package device, comprising:
providing a lead frame, wherein the lead frame is provided with a first surface and a second surface which are opposite and an opening;
attaching the active surface of the first chip to the first surface corresponding to the opening;
attaching a second chip inactive surface to the second surface;
providing a circuit layer and a dielectric layer, wherein an adhesive layer is arranged on the circuit layer, and a protective layer is arranged on the dielectric layer;
pressing the protective layer corresponding to the first surface and the adhesive layer corresponding to the second surface so that at least part of the inactive surface of the first chip is abutted to the dielectric layer;
electrically connecting the active surface of the first chip with the circuit layer through the opening;
and electrically connecting the active surface of the second chip with the circuit layer so as to electrically connect the first chip with the second chip through the circuit layer.
In some optional embodiments, the method further comprises:
and forming a heat dissipation assembly at the position of the dielectric layer corresponding to the inactive surface of the first chip, wherein the heat dissipation assembly is attached to the inactive surface of the first chip.
In a semiconductor package device and a method of manufacturing the same provided by the present disclosure, designing a semiconductor package device includes: a lead frame having opposing first and second surfaces; the first chip is arranged on the first surface, and the active surface faces the first surface; and the protective layer covers the first surface and at least part of the first chip, and at least part of the inactive surface of the first chip is exposed out of the protective layer. Therefore, at least part of the inactive surface of the first chip is directly contacted with the outside of the protective layer, the inactive surface of the first chip is not required to be contacted with the lead frame, heat can be directly radiated to the outside, the heat radiation problem caused by the fact that the power of the first chip is improved due to the fact that the lead frame is limited by the heat radiation capacity caused by the fact that the lead frame is coated by the dielectric material is avoided, and the overall heat radiation performance of the semiconductor packaging device is further improved.
Drawings
Other features, objects and advantages of the disclosure will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
fig. 1 is a schematic longitudinal cross-sectional structure of one embodiment of a semiconductor package device according to the present disclosure;
fig. 2A to 2E are schematic longitudinal cross-sectional structural views of different embodiments of a semiconductor package device according to the present disclosure;
fig. 3A and 3B are schematic top and longitudinal cross-sectional structural views of a semiconductor package device at a stage of manufacture according to one embodiment of the present disclosure;
fig. 3C to 3E are schematic longitudinal sectional structure views of a semiconductor package device at a manufacturing stage according to an embodiment of the present disclosure.
Description of the symbols: 11-lead wireA frame; 11 a-a first surface; 11 b-a second surface; 12-a first chip; 12 a-a first chip active face; 12 b-a first chip inactive face; 123-electrical connections; 13-a second chip; 13 a-second chip active surface; 13 b-the second chip inactive face; 14-a protective layer; 15-an adhesive layer; 16-a line layer; 17-a dielectric layer; 18-a heat sink assembly; 19-passive electronic components; 20-routing; 21-a first carrier plate; 22-a second carrier plate; dR-a through hole diameter; dT-a perforation diameter; t isD-a dielectric layer thickness; t isT-a protective layer thickness; t isB-the thickness of the adhesive layer; t isL-a leadframe thickness; o isS-a leadframe opening width; dEThe horizontal distance of the first chip edge from the leadframe opening edge.
Detailed Description
The following description of the embodiments of the present disclosure will be provided in conjunction with the accompanying drawings and examples, and those skilled in the art can easily understand the technical problems and effects of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. In addition, for convenience of description, only portions related to the related invention are shown in the drawings.
It should be noted that the structures, proportions, and dimensions shown in the drawings and described in the specification are for the understanding and reading of the present disclosure, and are not intended to limit the conditions under which the present disclosure can be implemented, so they are not technically significant, and any modifications of the structures, changes in the proportions and adjustments of the dimensions should be made without affecting the efficacy and attainment of the same. In the present specification, the terms "upper", "first", "second" and "first" are used for clarity of description only, and are not intended to limit the scope of the present disclosure, and changes or modifications in relative relationships thereof should be construed as being within the scope of the present disclosure without substantial technical changes.
It should also be noted that the longitudinal section corresponding to the embodiment of the present disclosure may be a front view direction section, the transverse section may be a right view direction section, and the horizontal section may be a top view direction section.
In addition, the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict.
Referring to fig. 1, fig. 1 is a schematic longitudinal cross-sectional structure of one embodiment of a semiconductor package device according to the present disclosure.
As shown in fig. 1, the semiconductor package device 100 may include: the chip package comprises a lead frame 11, a first chip 12, a second chip 13, a protective layer 14 and a circuit layer 16. Wherein:
the lead frame 11 has a first surface 11a and a second surface 11b opposite to each other.
The lead frame is used as a chip carrier of an integrated circuit, and is a key structural member which realizes the electrical connection between the leading-out end of an internal circuit of a chip and an external lead by means of bonding materials (gold wires, aluminum wires and copper wires) to form an electrical circuit. In the present disclosure, the lead frame 11 may include a lead frame composed of a metallic material or a non-metallic material. Here, the metal material may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or an alloy thereof. The non-metallic material may include organic matter such as polyaniline or the like or non-metallic inorganic matter such as graphene or the like.
The first chip 12 is disposed on the first surface 11a, and the active surface 12a of the first chip 12 faces the first surface 11 a.
And the second chip 13 is arranged on the second surface 11b, and the inactive surface 13b of the second chip 13 faces the second surface 11 b.
The type of the first chip 12 is not particularly limited in the present disclosure, and the first chip 12 may include, for example, a die (die), an ASIC (Application Specific Integrated Circuit) chip, a Power Management Integrated Circuit (PMIC) chip, an HBM (High Bandwidth Memory) chip, or the like.
And the protective layer 14 covers the first surface 11a and at least part of the first chip 12, and the inactive surface 12b of the first chip is at least partially exposed out of the protective layer 14.
The protective layer 14 may comprise liquid and/or thin film organics such as: non-conductive glue (Non-conductive Plastic, NCP), Non-conductive Film (Non-conductive Film, NCF), Anisotropic Conductive Film (ACF), anisotropic conductive Film (ACP), Polyimide (Polyimide, PI), Epoxy, resin (resin), PP (preprg, PrePreg or so called PrePreg, PrePreg), ABF (Ajinomoto fabric-up Film), adhesive (glue), Polyamide fiber (PA), and the like. Here, the material of the protective layer 14 is only illustrated, and is not particularly limited.
At least part of the first chip inactive surface 12b is exposed out of the protection layer 14, so that the first chip 12 can radiate heat through at least part of the first chip 12 inactive surface 12b exposed out of the protection layer 14, the influence of limited heat radiation capability of the current lead frame 11 on the heat radiation of the first chip 12 is reduced, and the heat radiation effect on the first chip inactive surface 12b is improved.
The wiring layer 16 may be a redistribution layer composed of conductive traces and Dielectric material (Dielectric). It should be noted that, the redistribution layer forming technology currently known or developed in the future may be used in the manufacturing process, and the present application is not limited thereto, and for example, the redistribution layer may be formed by using processes including but not limited to photolithography, plating (plating), Electroless plating (electroplating), and the like. Here, the dielectric material may include organic and/or inorganic substances, wherein the organic substance may be, for example: polyamide fiber (PA), PI, Epoxy resin (Epoxy), Poly-p-Phenylene Benzobisoxazole (PBO) fiber, FR-4 Epoxy glass cloth laminate, PP, ABF, etc., and inorganic substances may be, for example, silicon (Si), glass (glass), ceramic (ceramic), silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material may include a seed layer and a metal layer. Here, the seed layer may be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., and the metal layer may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or an alloy thereof.
In some alternative embodiments, as shown in fig. 1, the first chip active side 12a and the second chip active side 13a both face the wiring layer 16. The electric connection paths between the first chip 12 and the second chip 13 and the circuit layer 16 are shortened, the resistance of the electric connection paths is reduced, the shorter electric connection paths can accelerate the heat transfer, and the heat conduction rate of the active surface 12a of the first chip 12 and the active surface 13a of the second chip 13 is improved.
Referring now to fig. 2A, fig. 2A is a schematic diagram of a longitudinal cross-sectional structure of one embodiment 200A of a semiconductor package device according to the present disclosure. The semiconductor package device 200A shown in fig. 2A is similar to the semiconductor package device 100 shown in fig. 1, except that the semiconductor package device 200A may further include: electrical connection 123 and adhesive layer 15, wherein:
the electrical connection member 123 is disposed on the active surface 12a of the first chip 12 and passes through the lead frame 11.
The electrical connector 123 can reduce the depth of the via hole formed in the circuit layer 16 during the electrical connection between the circuit layer 16 and the first chip 12. Due to the limitation of the photolithography process, the depth of the via hole is directly related to the diameter of the via hole on the circuit layer 16, so that the reduction of the depth of the via hole can reduce the size of the via hole on the circuit layer 16, thereby increasing the number of input/output (in/out, I/O) of the device 200A.
The adhesive layer 15 is disposed between the lead frame 11 and the circuit layer 16, and the electrical connector 15 covers at least a portion of the active surface of the first chip 12, the active surface of the second chip 13, and the second surface 11 b.
The adhesive layer 15 may comprise the same or different material as the protective layer 14.
Referring now to fig. 2B, fig. 2B is a schematic diagram of a longitudinal cross-sectional structure of one embodiment 200B of a semiconductor package device according to the present disclosure. The semiconductor package device 200B shown in fig. 2B is similar to the semiconductor package device 200A shown in fig. 2A, except that the semiconductor package device 200B may further include a heat dissipation assembly 18, wherein:
the heat dissipation assembly 18 is disposed on the first chip inactive surface 12 b.
Heat transfer is enabled between the first chip inactive side 12b and the heat sink assembly 18. Heat can be transferred from the first chip inactive side 12b to the heat dissipation assembly 18 to increase the heat dissipation rate of the first chip inactive side 12 b. The heat sink assembly 18 may include heat sink circuitry.
In some alternative embodiments, as shown in fig. 2B, the heat dissipation member 18 may be disposed on the dielectric layer 17 and contact the first chip inactive surface 12B.
Referring now to fig. 2C, fig. 2C is a schematic diagram of a longitudinal cross-sectional structure of one embodiment 200C of a semiconductor package device according to the present disclosure. The semiconductor package device 200C shown in fig. 2C is similar to the semiconductor package device 200B shown in fig. 2B, except that the semiconductor package device 200C may further include a passive electronic component 19, wherein:
the passive electronic element 19 is disposed on the second surface 11 b. The passive electronic component 19 may be electrically connected to the first chip 12.
In some alternative embodiments, as shown in fig. 2C, the semiconductor package device 200C may further include a wire bond 20 disposed on the adhesive layer 15, and the first chip 12 may be electrically connected to the lead frame 11 through the wire bond 20.
Referring now to fig. 2D, fig. 2D is a schematic diagram of a longitudinal cross-sectional structure of one embodiment 200D of a semiconductor package device according to the present disclosure. The semiconductor package device 200D shown in fig. 2D is similar to the semiconductor package device 200B shown in fig. 2B, except that in the semiconductor package device 200D, the adhesive layer 15 may include a mixed material of an organic material and an inorganic material, wherein the organic material may be the same as or different from the organic material included in the protective layer 14, and the inorganic material may be, for example, silicon (Si), glass (glass), ceramic (ceramic), silicon oxide, silicon nitride, tantalum oxide, or the like. The mixed material of the organic substance and the inorganic substance can increase the strength of the adhesive layer 15 after curing, and can improve the support of the semiconductor package device 200D, thereby improving the overall strength of the semiconductor package device 200D.
With continued reference to fig. 2E, fig. 2E illustrates dimensional indicia of various primary structures in a semiconductor package device 200B in accordance with the embodiment of fig. 2B of the present disclosure, wherein:
DRd is not less than 5um for the diameter of the via hole arranged in the dielectric layer 17R≤20um。
TDThe thickness of the dielectric layer 17 or the dielectric layer 16 is not less than 5um and not more than TDNot more than 10um and not more than 1DR/TD≤4。
DTA via diameter of 50 um. ltoreq. D for penetrating the dielectric layer 17 and the protective layer 14T≤100um。
TTIs the thickness of the protective layer 14, T is more than or equal to 25umTNot more than 100um and not more than 0.5T/TT≤3.5。
TBThe thickness of the adhesive layer 15 is 50um ≤ TB≤200um。
TLT is more than or equal to 50um and is the thickness of the lead frame 11L≤200um。
OSIs the opening width, O, of the lead frame 11S>50um。
DEThe distance between the edge of the first chip 12 and the edge of the opening of the lead frame 11, DE>10um。
Referring now to fig. 3A through 3E, fig. 3A and 3B are schematic horizontal and longitudinal cross-sectional structures of a semiconductor package device at a manufacturing stage according to one embodiment of the present disclosure, with a lower portion of fig. 3A and 3B being a schematic longitudinal cross-sectional structure of the semiconductor package device and an upper portion being a corresponding schematic horizontal cross-sectional structure. Fig. 3C to 3E are schematic longitudinal sectional structure views of a semiconductor package device at a manufacturing stage according to an embodiment of the present disclosure.
Referring to fig. 3A, a lead frame 11 and a first chip 12 are provided.
Here, the lead frame 11 has first and second opposing surfaces 11a and 11b and an opening.
Here, the opening of the lead frame 11 may be a standard lead frame opening that is preset, or may be an opening that is etched or mechanically drilled according to the actual application.
Then, an electrical connection member 123 is provided on the first chip active surface 12 a.
Next, the first chip active surface 12a is attached to the first surface 11a corresponding to the opening, so that the electrical connector 123 passes through the lead frame 11 through the opening of the lead frame 11.
Here, the active surface 12a of the first chip 12 may be attached to the first surface 11a corresponding to the opening by an adhesive provided at an edge of the active surface 12a of the first chip. The adhesive may comprise, for example, an Epoxy (Epoxy).
Referring to fig. 3B, the lead frame 11 is turned over so that the second surface 11B faces upward.
Then, a second chip 13 is provided, and a second chip inactive surface 13b is attached to the second surface 11 b.
Here, the second chip inactive surface 13b may be attached to the second surface 11b by an adhesive by providing the adhesive on the second chip inactive surface 13 b.
Referring to fig. 3C, a first carrier plate 21 is provided.
Here, the first carrier 21 is provided with a wiring layer 16 thereon, and the wiring layer 16 is provided with an adhesive layer 15 thereon.
Then, a second carrier 22 is provided, wherein a dielectric layer 17 is disposed on the second carrier 22, and a protective layer 14 is disposed on the dielectric layer 17.
Then, through a semi-polymerization semi-curing (B-Stage) process of the thermosetting resin, the passivation layer 14 is pressed against the first surface 11a, and the adhesive layer 15 is pressed against the second surface 11B, so that the first chip inactive surface 12B is at least partially abutted against the dielectric layer 17.
Referring to fig. 3D, after heating to cure the protective layer 14 and the adhesive layer 15, the first carrier 21 and the second carrier 22 are removed, respectively.
Referring to fig. 3E, the first chip active surface 12a is electrically connected to the wiring layer 16 through the opening.
Here, the first active surface 12a of the first wire piece may be electrically connected to the wire layer 16 through the opening by providing the via holes for electrically connecting the wire layer 16 and the electrical connector 123.
Then, the second chip active surface 13a is electrically connected to the circuit layer 16, so that the first chip 12 is electrically connected to the second chip 13 through the circuit layer 16.
For example, Flip Chip Bonding (FCB), Thermal Compression Bonding (FCB), or the like may be used for the electrical connection process.
Then, a heat dissipation assembly 18 is formed at the position of the dielectric layer 17 corresponding to the first chip inactive surface 12b, and the heat dissipation assembly 18 is attached to the first chip inactive surface 12 b.
Here, for example, a part of the dielectric layer 17 may be removed by laser lithography, a cavity communicating the dielectric layer 17 and the first chip inactive surface 12b is formed, a seed layer is formed on a surface of the cavity by Physical Vapor Deposition (PVD), and an electroplating layer is formed on the seed layer by an electroplating manner to form the heat dissipation assembly 18.
Finally, a flip Chip Connection (C4) method is used to place solder bumps on the bottom of the circuit layer 16.
The method for manufacturing the semiconductor packaging device provided by the present disclosure can achieve similar technical effects to the aforementioned semiconductor packaging device, and is not described herein again.
While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof within the embodiments without departing from the true spirit and scope of the disclosure as defined by the appended claims. The illustrations may not be drawn to scale. There may be a difference between the technical reproduction and the actual implementation in the present disclosure due to variables in the manufacturing process, and the like. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present disclosure.
Claims (10)
1. A semiconductor package device, comprising:
a lead frame having opposing first and second surfaces;
the first chip is arranged on the first surface, and the active surface faces the first surface;
and the protective layer covers the first surface and at least part of the first chip, and at least part of the inactive surface of the first chip is exposed out of the protective layer.
2. The apparatus of claim 1, wherein the apparatus further comprises:
and the circuit layer is arranged on the second surface, and the first chip is electrically connected with the circuit layer.
3. The apparatus of claim 2, wherein the apparatus further comprises:
and the second chip is arranged on the second surface, the inactive surface of the second chip faces the second surface, and the second chip is electrically connected with the first chip through the circuit layer.
4. The apparatus of claim 1, wherein the apparatus further comprises:
and the heat dissipation assembly is arranged on the inactive surface of the first chip.
5. The apparatus of claim 1, wherein the apparatus further comprises:
and the electric connecting piece is arranged on the active surface of the first chip and penetrates through the lead frame.
6. A semiconductor package device, comprising:
a lead frame having opposing first and second surfaces;
the first chip is arranged on the first surface, and the active surface faces the first surface;
the second chip is arranged on the second surface, and the inactive surface faces the second surface;
and the first chip is electrically connected with the second chip through the circuit layer.
7. The apparatus of claim 6, wherein the apparatus further comprises:
and the protective layer covers the first surface and at least part of the first chip, and at least part of the inactive surface of the first chip is exposed out of the protective layer.
8. The apparatus of claim 7, wherein the apparatus further comprises:
and the heat dissipation assembly is arranged on the inactive surface of the first chip.
9. The apparatus of claim 6, wherein the apparatus further comprises:
and the bonding layer is arranged between the lead frame and the circuit layer and coats at least part of the active surface of the first chip, the active surface of the second chip and the second surface.
10. A method of manufacturing a semiconductor package device, comprising:
providing a lead frame, wherein the lead frame is provided with a first surface and a second surface which are opposite and an opening;
attaching the active surface of the first chip to the first surface corresponding to the opening;
attaching a second chip inactive surface to the second surface;
providing a circuit layer and a dielectric layer, wherein an adhesive layer is arranged on the circuit layer, and a protective layer is arranged on the dielectric layer;
pressing the protective layer corresponding to the first surface and the adhesive layer corresponding to the second surface so that at least part of the inactive surface of the first chip is abutted to the dielectric layer;
electrically connecting the active surface of the first chip with the circuit layer through the opening;
and electrically connecting the active surface of the second chip with the circuit layer so as to electrically connect the first chip with the second chip through the circuit layer.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110683033.0A CN113506792A (en) | 2021-06-18 | 2021-06-18 | Semiconductor package device and method of manufacturing the same |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110683033.0A CN113506792A (en) | 2021-06-18 | 2021-06-18 | Semiconductor package device and method of manufacturing the same |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6140707A (en) * | 1998-05-07 | 2000-10-31 | 3M Innovative Properties Co. | Laminated integrated circuit package |
| CN101256965A (en) * | 2007-03-01 | 2008-09-03 | 全懋精密科技股份有限公司 | Structure embedded with semiconductor chip and its manufacturing method |
| TW200942105A (en) * | 2008-03-27 | 2009-10-01 | Phoenix Prec Technology Corp | Method of fabricating package substrate having semiconductor component embedded therein |
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2021
- 2021-06-18 CN CN202110683033.0A patent/CN113506792A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6140707A (en) * | 1998-05-07 | 2000-10-31 | 3M Innovative Properties Co. | Laminated integrated circuit package |
| CN101256965A (en) * | 2007-03-01 | 2008-09-03 | 全懋精密科技股份有限公司 | Structure embedded with semiconductor chip and its manufacturing method |
| TW200942105A (en) * | 2008-03-27 | 2009-10-01 | Phoenix Prec Technology Corp | Method of fabricating package substrate having semiconductor component embedded therein |
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