CN101256965A - Structure embedded with semiconductor chip and its manufacturing method - Google Patents
Structure embedded with semiconductor chip and its manufacturing method Download PDFInfo
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- CN101256965A CN101256965A CNA2007100861142A CN200710086114A CN101256965A CN 101256965 A CN101256965 A CN 101256965A CN A2007100861142 A CNA2007100861142 A CN A2007100861142A CN 200710086114 A CN200710086114 A CN 200710086114A CN 101256965 A CN101256965 A CN 101256965A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The present invention discloses a structure of a embedded semiconductor chip and its manufacturing method, the method mostly provides a loading plate opposing first and second surface, forming multi- through opening in the loading plate, and forming first plow groove surrounding the opening and without through the loading plate at the first surface of the loading plate, and placing the semiconductor chip in the opening severalty, and pressing the first surface of the loading plate and the semiconductor chip on the first dielectric layer for stuffing the first dielectric layer into the first plow groove and the gapping place between the semiconductor chip and the loading plate, forming the second plow groove at the second surface corresponding to the first plow groove position, and the second plow groove is communicated with the first plow groove to forming the plow groove through the loading plate, thereby the subsequent cutting operation can be executed by the through plow groove, furthermore the loading plate space is used efficiently and the typesetting rate is improved, and the molding time is reduced.
Description
Technical field
The present invention relates to a kind of structure and method for making thereof of embedded with semi-conductor chip, particularly relate to a kind of structure and method for making thereof that is integrated with the embedded with semi-conductor chip of semiconductor chip and line construction simultaneously.
Background technology
Flourish along with electronic industry, electronic product also develops towards light, thin, short, little, high integration, multifunction direction.For satisfying the package requirements of semiconductor package part high integration (Integration) and microminiaturized (Miniaturization), the encapsulation shape of semiconductor chip is encapsulated or crystal covering type (FlipChip by the ball grid array (BGA) of one chip gradually, FC) encapsulation evolves to 3D encapsulation and modularization encapsulation form, make the structure of encapsulation produce for example SiP (System in Package) of different looks, SIP (SystemIntegrated Package), SiB various ways such as (System in Board).
But, those 3D and modularization encapsulation form are with Flip Chip (flip chip), or routing technology (wire bonding) with single semiconductor chip one by one be connected to chip bearing plate surface, also or with surface mount technology (SMT) then in the chip bearing member surface.So, though can reach the purpose of high pin number, but when high frequency more uses or during high speed operation, its usefulness that will produce electrical characteristic because of the lead access path is long can't promote, and restriction to some extent, in addition, because of conventional package needs connecting interface repeatedly, relatively increase manufacturing cost.
In view of this, meet down the application of product from generation to generation in order to promote electrical quality effectively, industry is studied employing one after another with in the chip buried bearing part, does directly to electrically connect, shorten electrical conducting path, and reduce the loss of signal, distorted signals and be lifted at the ability of high speed operation.
As shown in Figure 1, be the encapsulating structure generalized section of existing embedded semi-conductor element.As shown in the figure, this encapsulating structure comprises a loading plate 10, and a surface 100 of this loading plate 10 is formed with at least one opening 100a; At least one semiconductor chip 11, it has an active surface 11a and a relative non-active surface 11b, is formed with a plurality of electronic padses 110 on this active surface 11a, and this semiconductor chip connects and places on this loading plate 10 and be accommodated in this opening 100a; One circuit circuit layer reinforced structure 12, it is formed on this loading plate 10, and this circuit circuit layer reinforced structure 12 is electrically connected to electronic pads 110 on this semiconductor chip 11 by a plurality of conductive blind holes 120.The non-active surface 11b of this of this semiconductor chip 11 connects by gluing drug 13 and places this loading plate opening 100a.
This circuit layer reinforced structure 12 comprises at least one insulating barrier 121, at least one line layer 122 that is stacked and placed on this insulating barrier 121, and a plurality of conductive blind holes 120, it runs through this insulating barrier 121 to be electrically connected to this line layer 122, on these circuit layer reinforced structure 12 outer surfaces, have a plurality of electric connection pads 123, and has a welding resisting layer 124, it has a plurality of openings to appear those electric connection pads 123, plant the usefulness of putting solder ball (Solder ball) 123 thereby provide, to be electrically conducted to outer member.
But, for saving packaging cost, generally in a substrate panel (panel), bury a plurality of semiconductor chips simultaneously underground, afterwards in this substrate panel and the enterprising line of semiconductor chip road processing procedure to form the circuit that electrically connects with those semiconductor chips, to finish the outside electric connection of those semiconductor chips, afterwards again by cutting single job to form the packaging part of the single semiconductor chip of tool.So, in the above-mentioned existing processing procedure, when being to carry out on this substrate panel the semiconductor chip composing, need on this substrate panel, to reserve some zones, cut single job for the later use make-up machine, because make-up machine is general bigger, the zone of reserving on this substrate panel is also corresponding big, thereby the spendable configuration of waste substrate space, perhaps cause the reduction of composing rate, the cost of substrate panel to increase.
Again, be after semiconductor chip is directly inserted substrate panel in the above-mentioned existing processing procedure, carry out the circuit processing procedure in the single side surface of this substrate panel, cause formed encapsulating structure apparent surface's unequal power distribution, make substrate panel in manufacture process, easily produce warpage, cause the low and difficult production of product yield.
Moreover, be to utilize the moulding board directly the base plate for packaging panel to be cut in the existing processing procedure, molding time can't be shortened.On the other hand, circuit generally is to be made by metallic copper, and when cutting single job, the metallic copper of the big ductility of tool extends owing to the pressure that is subjected to the moulding board causes copper face, easily cause the mutual scratch of encapsulating structure after cutting singly, and then make encapsulating structure suffer to destroy, produce the yield reduction.
Therefore, how a kind of structure and method for making thereof of embedded with semi-conductor chip are provided, the waste of substrate panel usage space, substrate composing rate are low to avoid in the prior art, substrate warp, encapsulating structure suffer to destroy, defectives such as yield is low, cost increases, molding time increase, and reality has become the difficult problem that present industry is demanded urgently capturing.
Summary of the invention
In view of the many disadvantages of above-mentioned prior art, main purpose of the present invention provides a kind of structure and method for making thereof of embedded with semi-conductor chip, and using increases chip bearing member composing rate, effectively utilizes the usage space of chip bearing member.
Another object of the present invention is to provide a kind of structure and method for making thereof of embedded with semi-conductor chip, use balance bearing part suffered stress in manufacture process, and then avoid taking place warping phenomenon, can avoid overall structure to be damaged simultaneously.
A further object of the present invention is to provide a kind of structure and method for making thereof of embedded with semi-conductor chip, uses and promotes yield, lowers molding time and cost.
For reaching above-mentioned and other purpose, the present invention proposes a kind of structure method for making of embedded with semi-conductor chip, it comprises: the loading plate that a tool first surface and opposing second surface are provided, in this loading plate, form a plurality of openings that run through, and form first groove that centers on those openings and do not run through this loading plate in this first surface of this loading plate; One first dielectric layer is provided, this first surface of this loading plate is placed on this first dielectric layer; The semiconductor chip is provided, it has active surface and relative non-active surface, this active surface has a plurality of electronic padses, this semiconductor chip is placed in the opening of this loading plate, and this non-active surface places on this first dielectric layer, this loading plate of pressing, this semiconductor chip and this first dielectric layer then so that this first dielectric layer is inserted in this first groove and this semiconductor chip and this loading plate between the gap in; And in this second surface of this loading plate to should forming second groove in the first groove position, and this second groove is connected with this first groove, use forming the groove that runs through this loading plate.
The method for making of said structure comprises again: form one second dielectric layer on this active surface of this loading plate second surface and this semiconductor chip, and this second dielectric layer is to insert in this second groove; And in this second dielectric layer, form a plurality of conductive blind holes, and on this second dielectric layer, form a line layer, those conductive blind holes electrically connect those electronic padses of this line layer and this semiconductor chip.In the method for making of the present invention, again can be when forming line layer on this second dielectric layer, form a metal level in the outer surface of this first dielectric layer.
In addition, above-mentioned method for making is included in again and forms a circuit layer reinforced structure on this second dielectric layer and this line layer, it has at least one dielectric layer, at least one build-up circuit layer, a plurality of connection gasket and a plurality of conductive blind hole, partly those conductive blind holes are this line layer that is electrically connected on this second dielectric layer, this circuit layer reinforced structure also comprises a welding resisting layer, it has a plurality of perforates, to manifest those connection gaskets of this circuit layer reinforced structure.In the method for making of the present invention, when conducting transmission line increases layer processing procedure, also can continue the laminated metal layer in the metal level of this first dielectric layer outer surface to form the metallic plate of tool multi-layer metal structure.
Again, above-mentioned method for making is included in again in this metallic plate the groove position of running through that should loading plate is formed opening, can cut single job to form the encapsulating structure of a plurality of integrating semiconductor chips and line layer by the formed groove that runs through in this loading plate afterwards.
The present invention also provides a kind of structure of embedded with semi-conductor chip, and it comprises: a loading plate, and this loading plate has first surface and opposing second surface, and has a plurality of openings that run through in this loading plate, and this loading plate also has the groove that runs through around those openings; A plurality of semiconductor chips respectively are placed in those openings of this loading plate, and this semiconductor chip has active surface and relative non-active surface, and this active surface has a plurality of electronic padses; And one first dielectric layer, be formed on this non-active surface of this first surface of this loading plate and this semiconductor chip, and insert in the gap between this semiconductor chip and this loading plate, and this runs through in the groove to insert part.
The structure of above-mentioned embedded with semi-conductor chip can comprise again: one second dielectric layer, be formed on this active surface of this second surface of this loading plate and this semiconductor chip, and this second dielectric layer is inserted the remaining space that this runs through groove; And a line layer, be formed on this second dielectric layer, with a plurality of conductive blind holes, be formed in this second dielectric layer, this conductive blind hole is for electrically connecting those electronic padses of this line layer and this semiconductor chip.
Above-mentioned structure can comprise a circuit layer reinforced structure again, be formed on this second dielectric layer and this line layer, this circuit layer reinforced structure has at least one dielectric layer, at least one build-up circuit layer, a plurality of connection gasket and a plurality of conductive blind hole, partly those conductive blind holes are electrically connected to this line layer on this second dielectric layer, this circuit layer reinforced structure also comprises a welding resisting layer, it has a plurality of perforates, to manifest those connection gaskets of this circuit layer reinforced structure.
In addition, structure of the present invention comprises a metallic plate again, it is formed on the outer surface of this first dielectric layer, and in this metallic plate the groove position of running through that should loading plate is formed with opening, the follow-up less groove (comprising first groove and second groove) of width that single job uses of cutting can be provided, thereby can promote the utilance of loading plate arrangement space, thereby can avoid in substrate panel, needing to reserve enough spaces in the prior art and cut single job with the shaping board for follow-up, due to can't effectively increase the space utilization rate of base plate line layout, perhaps can't promote the defectives such as unit substrate composing rate of substrate panel.
In addition, the present invention is after the loading plate moulding, use first, second dielectric material that loading plate and semiconductor chip is fixing in advance, loading plate and semiconductor chip are become one, reduce existing single face processing procedure and produce plate prying problem, and can promote process rate and production, reach cost-effective purpose.And, in loading plate, form among the present invention and can cut the groove that single job is used, thereby can avoid base plate for packaging is cut when forming a plurality of single encapsulating structure for follow-up, the not busy scratch mutually of encapsulating structure, and the encapsulating structure that can avoid finishing is destroyed.
Description of drawings
Fig. 1 is the encapsulating structure generalized section of existing embedded semi-conductor element; And
Fig. 2 A to Fig. 2 I is the method for making generalized section of the structure of embedded with semi-conductor chip of the present invention.
The component symbol simple declaration
10,20 loading plates
100 surfaces
100a, 200,27 openings
11,22 semiconductor chips
110,2200 electronic padses
11a, 220 active surfaces
11b, 221 non-active surfaces
12,25 circuit layer reinforced structures
120,240, the 251c conductive blind hole
121,250 dielectric layers
123 electric connection pads
124,26 welding resisting layers
125 solder balls
20a, 20b first surface, second surface
201,202 first grooves, second groove
203 grooves
210, first dielectric layer
211 thin metal layers
212 metal levels
213 metallic plates
220,221 active surfaces, non-active surface
23 second dielectric layers
122,24, the 251a line layer
230,260 perforates
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by the content that this specification disclosed.The present invention also can be implemented or be used by other different specific embodiment, and each details in this specification also can be based on different viewpoints and application, carries out various modifications and change under the spirit of the present invention not deviating from.
See also Fig. 2 A to Fig. 2 I, be the method for making generalized section of the structure that shows embedded with semi-conductor chip of the present invention.It is noted that described accompanying drawing is the schematic diagram of simplification, the processing procedure of circuit board of the present invention only is described in a schematic way.But described accompanying drawing only shows the element relevant with the present invention, the state that its shown element is non-when being actual enforcement, and component number, shape and the dimension scale during its actual enforcement is a kind of optionally design, and its component placement kenel may be more complicated.
Shown in Fig. 2 A, one loading plate 20 at first is provided, this loading plate 20 has a first surface 20a and reaches and this first surface 20a opposing second surface 20b, and in this loading plate 20, form a plurality of openings 200 that run through, and form first groove 201 that centers on those openings 200 and do not run through this loading plate 20 in the first surface 20a of this loading plate 20.Above-mentioned loading plate 20 can be the made heating panel of metal material, in addition, this loading plate also can be the made insulation boards of resin material such as BT resin, RF4 resin, epoxy resin, glass fibre, policapram or cyanogen fat, or for being formed with the circuit board of line construction.In the present invention, this first groove 201 forms with etching or forms with router (router).
Shown in Fig. 2 B and Fig. 2 C; one first dielectric layer 210 is provided; this first surface 20a of this loading plate 20 is placed on this first dielectric layer 210; ccontaining semiconductor chip 22 in these loading plate 20 openings 200; it has active surface 220 and relative non-active surface 221; this active surface 220 has a plurality of electronic padses 2200; the non-active surface 221 of this of this semiconductor chip 22 places on this first dielectric layer 210; stick this active surface 220 of this second surface 20b of this loading plate 20 and this semiconductor chip 22 temporarily to fix this semiconductor chip 22 by a removable diaphragm (not shown) then; follow this loading plate 20 of pressing; this semiconductor chip 22 and this first dielectric layer 210; so that this first dielectric layer 210 is filled in this first groove 201 and the gap of 20 of this semiconductor chip 22 and this loading plates in, this first dielectric layer 210 of mat is fixed in this semiconductor chip 22 in the opening 200 of this loading plate 20.
The side surface that this first dielectric layer 210 does not contact with this loading plate 20 can be formed with a thin metal layer 211 again, wherein, this first dielectric layer 210 can be epoxy resin (Epoxy resin), policapram (Polyimide), hydrocyanic ester (Cyanate Ester), ABF (Ajinomo build-upfilm), bismaleimide/three nitrogen traps (Bismaleimide Triazine, BT) or the FR5 material of blending epoxy and glass fibre made; This thin metal layer 211 is general based on the preferable copper of conductivity (Cu), and this thin metal layer 211 can first pressing or is deposited on this first dielectric layer, preferable specific embodiment is before these thin metal layer 211 depositions, must in advance first dielectric layer, 210 surfaces be imposed asperitiesization, so that the follow-up adherence that continues electroplated metal layer on this thin metal layer effectively to be provided, perhaps can directly use a resin pressing Copper Foil (Resincoated copper, RCC).
Shown in Fig. 2 D, in this second surface 20b of this loading plate 20 to forming a plurality of second grooves 202 in first groove, 201 positions, and this second groove 202 is connected with this first groove 201 runs through groove 203, for the follow-up usefulness of utilizing shaping jig to cut single job with what formation ran through this loading plate 20.Therefore, the present invention mainly in the encapsulation procedure of semiconductor chip, promptly in this loading plate 20, be pre-formed can for follow-up cut single job and width less run through groove 203, thereby can effectively increase the space utilization rate of base plate line layout, perhaps can promote the composing rate of loading plate unit substrate, simultaneously can run through groove 203 by this utilizes shaping jig simply to cut the package substrate construction that can form the single semiconductor chip of tool, thereby can reduce molding time, save cost.
Shown in Fig. 2 E, on this loading plate 20 second surface 20b and this semiconductor chip 22, form one second dielectric layer 23 and line layer 24 in regular turn, and this line layer 24 is for being electrically connected to the electronic pads 2200 of these semiconductor chip 22 active surfaces 220.This second dielectric layer 23 is filled in this second groove 202, and is formed with a plurality of perforates 230 in this second dielectric layer 23 to expose the electronic pads 2200 of these semiconductor chip 22 active surfaces 220.This second dielectric layer 23 is formed at this loading plate and those semiconductor chip surface by the pressing mode, and inserts in this second groove 202.This line layer 24 is patterned metal layer (a for example metal copper layer), and this line layer 24 is electrically connected to the electronic pads 2200 of this semiconductor chip 22 by being formed at conductive blind hole 231 in these second dielectric layer, 23 perforates 230.
In the present invention, also can be when forming this line layer 24, at the thin metal layer 211 enterprising electroplating processing procedures of these first dielectric layer, 210 outer surfaces to form a metal level 212 (for example metal copper layer).
The present invention is after the loading plate moulding, use first, second dielectric material that loading plate and semiconductor chip is fixing in advance, loading plate and semiconductor chip are become one, reduce existing single face and make the plate prying problem that produces, and can promote process rate and production, reach cost-effective purpose.
Shown in Fig. 2 F, can on this second dielectric layer 23 and this line layer 24, form circuit layer reinforced structure 25 again afterwards, it has at least one dielectric layer 250, is stacked and placed on the build-up circuit layer 251a on this dielectric layer 250, a plurality of connection gasket 251b and a plurality of conductive blind hole 251c, and partly this conductive blind hole 251c electrically connects this line layer 251a and this line layer 24.This circuit increases a layer processing procedure to be known by industry, so do not give unnecessary details.
In addition, among the present invention, also can need when forming line layer 252, on above-mentioned metal level 212, repeatedly electroplate according to actual design with the stacked multilayer metal, to generate the metallic plate 213 of tool multi-layer metal structure in these first dielectric layer, 210 outer surfaces, but when in previous electroplating process, having reached predetermined thickness, can on this metallic plate 213, cover a resistance layer and continue to generate to prevent it as if this metallic plate 213.This metallic plate 213 can be used as the heating panel of semiconductor chip 22 heat transmissions, but also balance has the stress that the single face circuit increases layer processing procedure now, to reduce the plate prying problem that produces.
Shown in Fig. 2 G, can form a welding resisting layer 26 in the outer surface of this circuit layer reinforced structure 25 again afterwards, it has a plurality of perforates 260 to expose the electric connection pad 251b in these circuit layer reinforced structure 25 outmost surface circuits, can on those electric connection pads 251b, connect again afterwards and put conducting element (not icon), to provide this semiconductor chip 22 outside electric connection.
Shown in Fig. 2 H, in this metallic plate 213, form opening 27 to running through groove 203 positions, so that follow-uply cut single job to running through groove 203, to form a plurality of integrating semiconductor chips 22 and line layer 24, the encapsulating structure of 251a (shown in Fig. 2 I), and first dielectric layer 210 arranged in the surrounded surface of this encapsulating structure is residual.
The present invention also provides the structure of an embedded with semi-conductor chip, shown in Fig. 2 H, comprise: a loading plate 20, this loading plate 20 has first surface 20a and opposing second surface 20b, and have a plurality of openings 200 that run through in this loading plate 20, this loading plate 20 also has and runs through groove 203 around those openings 200; A plurality of semiconductor chips 22 respectively are placed in those openings 200 of this loading plate 20, and this semiconductor chip 22 has active surface 220 and relative non-active surface 221, and this active surface 220 has a plurality of electronic padses 2200; And one first dielectric layer 210, be formed on this non-active surface 221 of this first surface 20a of this loading plate 20 and this semiconductor chip 22, and insert in the gap between this semiconductor chip 22 and this loading plate 20, and this runs through in the groove 203 to insert part.
Structure of the present invention can comprise again: one second dielectric layer 23, be formed on this active surface 220 of this second surface 20b of this loading plate 20 and this semiconductor chip 22, and this second dielectric layer 23 is inserted the remaining space that this runs through groove 203; And a line layer 24, be formed on this second dielectric layer 23, with a plurality of conductive blind holes 240, be formed in this second dielectric layer 23, those conductive blind holes 240 are for electrically connecting those electronic padses 2200 of this line layer 24 and this semiconductor chip 22.
Then, on this second dielectric layer 23 and this line layer 24, can form a circuit layer reinforced structure 25 again, it has at least one dielectric layer 250, is stacked and placed on the build-up circuit layer 251a on this dielectric layer 250, a plurality of connection gasket 251b and a plurality of conductive blind hole 251c, and partly this conductive blind hole 251c is for electrically connecting this line layer 251a and this line layer 24; Comprise a welding resisting layer 26 again, it has a plurality of perforates 260 to expose the electric connection pad 251b in these circuit layer reinforced structure 25 outmost surface circuits.
In addition, structure of the present invention can comprise the metallic plate 213 that is formed at these first dielectric layer, 210 outer surfaces again, and in this metallic plate 213 groove 203 positions of running through that should loading plate 20 are formed with opening 27, can supply the follow-up single job of cutting, to form a plurality of integrating semiconductor chips 22 and line layer 24, the encapsulating structure of 251a (shown in Fig. 2 I), and first dielectric layer 210 arranged in the surrounded surface of this encapsulating structure is residual.
Than prior art, the present invention can provide the follow-up less groove (comprising first groove and second groove) of width that single job uses of cutting, thereby can promote the utilance of loading plate arrangement space, thereby can avoid in substrate panel, needing to reserve enough spaces in the prior art and cut single job with the shaping board for follow-up, due to can't effectively increase the space utilization rate of base plate line layout, perhaps can't promote the defectives such as unit substrate composing rate of substrate panel.
In addition, the present invention is after the loading plate moulding, use first, second dielectric material that loading plate and semiconductor chip is fixing in advance, loading plate and semiconductor chip are become one, reduce existing single face and make the plate prying problem that produces, and can promote process rate and production, reach cost-effective purpose.
And, forming in loading plate among the present invention can be for the follow-up groove of cutting the single job use, thereby can avoid base plate for packaging is cut when forming a plurality of single encapsulating structure, the pressure that is subjected to shaping jig owing to the material (metallic copper) of circuit produces to extend and makes between encapsulating structure mutually that the situation of scratch takes place, and the encapsulating structure that can avoid generating is destroyed.
The foregoing description only is illustrative principle of the present invention and effect thereof, but not is used to limit the present invention.Any those skilled in the art all can make amendment to the foregoing description under spirit of the present invention and category.Therefore the scope of the present invention should be foundation with the scope of claims of the present invention.
Claims (17)
1. the method for making of the structure of an embedded with semi-conductor chip comprises:
One loading plate is provided, and this loading plate has first surface and opposing second surface, forms a plurality of openings that run through in this loading plate, and forms first groove that centers on those openings and do not run through this loading plate in this first surface of this loading plate;
One first dielectric layer is provided, this first surface of this loading plate is placed on this first dielectric layer;
The semiconductor chip is provided, it has active surface and relative non-active surface, this active surface has a plurality of electronic padses, this semiconductor chip is placed in the opening of this loading plate, and this non-active surface places on this first dielectric layer, this loading plate of pressing, this semiconductor chip and this first dielectric layer are fixed in this semiconductor chip in the opening of this loading plate so that this first dielectric layer is inserted in the gap that reaches in this first groove between this semiconductor chip and this loading plate by this first dielectric layer then; And
To should forming second groove in the first groove position, and this second groove is connected in this second surface of this loading plate with this first groove, uses forming the groove that runs through this loading plate.
2. the method for making of the structure of embedded with semi-conductor chip according to claim 1 comprises a metal level again, its be formed at this first dielectric layer not with surface that this loading plate contacts on.
3. the method for making of the structure of embedded with semi-conductor chip according to claim 1 comprises again:
On this active surface of this second surface of this loading plate and this semiconductor chip, form one second dielectric layer, and this second dielectric layer is inserted in this second groove; And
Form a plurality of conductive blind holes in this second dielectric layer, and form a line layer on this second dielectric layer, those conductive blind holes are for electrically connecting those electronic padses of this line layer and this semiconductor chip.
4. the method for making of the structure of embedded with semi-conductor chip according to claim 3, be included in again and form a circuit layer reinforced structure on this second dielectric layer and this line layer, this circuit layer reinforced structure has at least one dielectric layer, at least one build-up circuit layer, a plurality of connection gasket and a plurality of conductive blind hole, partly this conductive blind hole is this line layer that is electrically connected on this second dielectric layer, this circuit layer reinforced structure also comprises a welding resisting layer, it has a plurality of perforates, to manifest those connection gaskets of this circuit layer reinforced structure.
5. the method for making of the structure of embedded with semi-conductor chip according to claim 3 when forming this line layer on this second dielectric layer, is included in again and forms a metal level on this first dielectric layer outer surface.
6. the method for making of the structure of embedded with semi-conductor chip according to claim 4 wherein, when forming this build-up circuit layer, continues laminated metal layer to form the metallic plate of a tool multi-layer metal structure in this metal level again.
7. the method for making of the structure of embedded with semi-conductor chip according to claim 6 is included in this metallic plate again to forming opening in the groove position.
8. the method for making of the structure of embedded with semi-conductor chip according to claim 7, the groove that is included in this loading plate is again cut single job and is integrated with the encapsulating structure of embedded with semi-conductor chip and line layer with formation, and in the surrounded surface of this encapsulating structure is residual this first dielectric layer is arranged.
9. the structure of an embedded with semi-conductor chip comprises:
One loading plate, this loading plate has first surface and opposing second surface, and has a plurality of openings that run through in this loading plate, and this loading plate also has the groove that runs through around those openings;
A plurality of semiconductor chips respectively are placed in those openings of this loading plate, and this semiconductor chip has active surface and relative non-active surface, and this active surface has a plurality of electronic padses; And
One first dielectric layer is formed on this non-active surface of this first surface of this loading plate and this semiconductor chip, and inserts in the gap between this semiconductor chip and this loading plate, and this runs through in the groove to insert part.
10. the structure of embedded with semi-conductor chip according to claim 9 comprises again:
One second dielectric layer be formed on this active surface of this second surface of this loading plate and this semiconductor chip, and this second dielectric layer is inserted the remaining space that this runs through groove; And
One line layer is formed on this second dielectric layer, with a plurality of conductive blind holes, is formed in this second dielectric layer, and this conductive blind hole electrically connects those electronic padses of this line layer and this semiconductor chip.
11. the structure of embedded with semi-conductor chip according to claim 10, comprise a circuit layer reinforced structure again, be formed on this second dielectric layer and this line layer, this circuit layer reinforced structure has at least one dielectric layer, at least one build-up circuit layer, a plurality of connection gasket and a plurality of conductive blind hole, partly those conductive blind holes are this line layer that is electrically connected on this second dielectric layer, this circuit layer reinforced structure also comprises a welding resisting layer, it has a plurality of perforates, to manifest those connection gaskets of this circuit layer reinforced structure.
12. as apply for a patent the structure of method scope the 9th described embedded with semi-conductor chip, comprise a metallic plate again, be formed on the outer surface of this first dielectric layer.
13. as apply for a patent the structure of method scope the 12nd described embedded with semi-conductor chip, comprise the opening that is formed at this metallic plate again, corresponding those in its position run through groove.
14. the structure of an embedded with semi-conductor chip comprises:
One loading plate, this loading plate has first surface and opposing second surface, and has a plurality of openings that run through in this loading plate;
The semiconductor chip, it is placed in this opening of this loading plate, and this semiconductor chip has active surface and relative non-active surface, and this active surface has a plurality of electronic padses;
One first dielectric layer is formed on this non-active surface of the first surface of this loading plate and this semiconductor chip, and in the surrounded surface of this loading plate is residual this first dielectric layer is arranged; And
One second dielectric layer is formed on this active surface of the second surface of this loading plate and this semiconductor chip.
15. the structure of embedded with semi-conductor chip according to claim 14, comprise a line layer again, be formed on this second dielectric layer, with a plurality of conductive blind holes, be formed in this second dielectric layer, those conductive blind holes are for electrically connecting those electronic padses of this line layer and this semiconductor chip.
16. the structure of embedded with semi-conductor chip according to claim 15, comprise a circuit layer reinforced structure again, be formed on this second dielectric layer and this line layer, this circuit layer reinforced structure has at least one dielectric layer, at least one build-up circuit layer, a plurality of connection gasket and a plurality of conductive blind hole, partly those conductive blind holes are this line layer that is electrically connected on this second dielectric layer, this circuit layer reinforced structure also comprises a welding resisting layer, it has a plurality of perforates, to manifest those connection gaskets of this circuit layer reinforced structure.
17. the structure of embedded with semi-conductor chip according to claim 14 comprises a metallic plate again, is formed on the outer surface of this first dielectric layer.
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| CNB2007100861142A CN100561696C (en) | 2007-03-01 | 2007-03-01 | The structure of embedded with semi-conductor chip and method for making thereof |
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| CNB2007100861142A CN100561696C (en) | 2007-03-01 | 2007-03-01 | The structure of embedded with semi-conductor chip and method for making thereof |
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