CN113506731A - 一种集成电路的制造工艺 - Google Patents
一种集成电路的制造工艺 Download PDFInfo
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- CN113506731A CN113506731A CN202110786617.0A CN202110786617A CN113506731A CN 113506731 A CN113506731 A CN 113506731A CN 202110786617 A CN202110786617 A CN 202110786617A CN 113506731 A CN113506731 A CN 113506731A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 41
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 215
- 238000000034 method Methods 0.000 claims abstract description 182
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 117
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- 238000005530 etching Methods 0.000 claims abstract description 46
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 claims abstract description 42
- 238000006243 chemical reaction Methods 0.000 claims abstract description 26
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical class F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims abstract description 25
- 229960000935 dehydrated alcohol Drugs 0.000 claims abstract description 10
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- 229910052681 coesite Inorganic materials 0.000 claims description 33
- 229910052906 cristobalite Inorganic materials 0.000 claims description 33
- 229910052682 stishovite Inorganic materials 0.000 claims description 33
- 229910052905 tridymite Inorganic materials 0.000 claims description 33
- 239000000758 substrate Substances 0.000 claims description 31
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 claims description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 22
- 238000000151 deposition Methods 0.000 claims description 21
- 229920005591 polysilicon Polymers 0.000 claims description 21
- 229910000040 hydrogen fluoride Inorganic materials 0.000 claims description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- 230000008021 deposition Effects 0.000 claims description 11
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 claims description 10
- 238000007667 floating Methods 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 4
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- 230000000694 effects Effects 0.000 description 11
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
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- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 8
- 229910021332 silicide Inorganic materials 0.000 description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 7
- 238000004140 cleaning Methods 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- PCLURTMBFDTLSK-UHFFFAOYSA-N nickel platinum Chemical compound [Ni].[Pt] PCLURTMBFDTLSK-UHFFFAOYSA-N 0.000 description 6
- 229910004014 SiF4 Inorganic materials 0.000 description 5
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 description 5
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- 238000002474 experimental method Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
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- 238000005092 sublimation method Methods 0.000 description 2
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
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Abstract
公开了一种集成电路的制造工艺,包括:去除晶片上的二氧化硅的方法,该方法可包括:向工艺腔室内通入脱水的氟化氢气体和脱水的醇类气体;使所述脱水的氟化氢气体和脱水的醇类气体混合,生成气态的刻蚀剂;使所述刻蚀剂与所述工艺腔室内的晶片反应,并使所述工艺腔室内保持高压状态以提高刻蚀选择比;以及将所述反应的副产物从所述工艺腔室内抽出。根据本发明的集成电路的制造工艺中,去除晶片上的二氧化硅的方法通过使气态的刻蚀剂在高压力下与二氧化硅直接反应,并在反应后将反应产物抽出,实现高选择比、高效率地去除二氧化硅。
Description
技术领域
本发明涉及集成电路制造工艺领域,更具体地,涉及一种集成电路的制造工艺。
背景技术
在集成电路制造工艺领域,目前通常使用硅基材料制造集成电路,硅 (或者多晶硅)在空气中放置的情况下表面会自然氧化形成一层致密的二氧化硅(SiO2)层,如图1a所示。在有些工艺中,例如,在金属硅化物(Silicide) 工艺中,金属镍铂(NiPt)薄膜要与硅衬底直接接触,如果衬底表面有一层 SiO2,则会增加电阻率,影响器件性能,因此,制造后续工艺前需要去除这层SiO2。而在去除这层SiO2的同时,必须保护其他薄膜/结构不能被去除或者损伤,如图1a所示,隔离层(Spacer,由氮化硅(Si3N4)材料制成)的线宽尺寸会影响器件电性,如漏电(leakage)增加等。因此,需要在去除 SiO2的同时尽量保持隔离层(Spacer,Si3N4)不被去除。
如图1b所示,现有工艺多采用湿法刻蚀、等离子体干法刻蚀等方法去除SiO2,其对Si3N4的刻蚀选择比低,对隔离层去除过多,造成隔离层尺寸缩小,增大漏电,从而影响器件性能。
因此,有必要开发一种应用于集成电路制造工艺中的高选择比、高效率的去除晶片上的二氧化硅的方法。
公开于本发明背景技术部分的信息仅仅旨在加深对本发明的一般背景技术的理解,而不应当被视为承认或以任何形式暗示该信息构成已为本领域技术人员所公知的现有技术。
发明内容
本发明提出了一种集成电路的制造工艺,包括去除晶片上的二氧化硅的方法,其通过使气态的刻蚀剂在高压力下与二氧化硅直接反应,并在反应后将反应产物抽出,实现高选择比、高效率地去除二氧化硅。
本发明提出了一种集成电路的制造工艺,包括去除晶片上的二氧化硅的方法,该方法包括:向工艺腔室内通入脱水的氟化氢气体和脱水的醇类气体;使所述脱水的氟化氢气体和脱水的醇类气体混合,生成气态的刻蚀剂;使所述刻蚀剂与所述工艺腔室内的晶片反应,并使所述工艺腔室内保持高压状态以提高刻蚀选择比;以及将所述反应的副产物从所述工艺腔室内抽出。
优选地,所述制造工艺包括利用HARP填充浅沟道绝缘层的轮廓调整的子工艺,在所述子工艺中,首先利用CVD工艺沉积一定厚度的HARP,而后采用所述的去除晶片上的二氧化硅的方法对STI进行刻蚀而使开口变大,重复执行上述沉积和刻蚀操作,直至工艺结束。
优选地,所述制造工艺包括去除STI的硬掩膜层上的SiO2自然氧化层的子工艺,所述STI的硬掩膜层为Si3N4,在所述子工艺中,利用所述的去除晶片上的二氧化硅的方法对STI的硬掩膜层表面上的SiO2自然氧化层进行刻蚀,并控制所述SiO2自然氧化层相对于STIHARP的刻蚀选择比,以便快速去除所述SiO2自然氧化层,且避免过度刻蚀STI HARP。
优选地,所述制造工艺包括去除衬垫氧化层的子工艺,所述衬垫氧化层为采用加热方式在衬底表面氧化形成SiO2层,其为STI的硬掩膜层Si3N4 的缓冲层,在所述子工艺中,利用所述的去除晶片上的二氧化硅的方法对所述衬垫氧化层进行刻蚀,并控制所述衬垫氧化层相对于STI HARP的刻蚀选择比,以便快速去除所述衬垫氧化层,且避免过度刻蚀STI HARP。
优选地,所述制造工艺包括沉积锗硅之前去除硅衬底上的SiO2自然氧化层的子工艺,在所述子工艺中,利用所述的去除晶片上的二氧化硅的方法对所述硅衬底上的SiO2自然氧化层进行刻蚀,并控制所述SiO2自然氧化层相对于多晶硅的刻蚀选择比,以便快速去除所述SiO2自然氧化层,且避免过度损伤Si衬底。
优选地,所述制造工艺包括沉积硅化物之前去除衬底表面和多晶硅栅极表面的SiO2自然氧化层的子工艺,在所述子工艺中,利用所述的去除晶片上的二氧化硅的方法对所述衬底表面和多晶硅栅极表面的SiO2自然氧化层进行刻蚀,并控制所述SiO2自然氧化层相对于多晶硅的刻蚀选择比,以便快速去除所述SiO2自然氧化层,且避免过度损伤Si衬底。
优选地,所述制造工艺包括2D NAND存储器制造过程中的STI凹槽子工艺,所述NAND存储器包括位于图形密集区域内的浮置栅极和图形密集区域STI HARP以及位于图形稀疏区域内的控制开关栅极和图形稀疏区域 STI HARP,所述浮置栅极和所述控制开关栅极为多晶硅,所述图形密集区域STI HARP和所述图形稀疏区域STI HARP为二氧化硅,在所述子工艺中,利用所述的去除晶片上的二氧化硅的方法对所述图形密集区域STI HARP 和所述图形稀疏区域STI HARP进行刻蚀,并控制所述STI HARP相对于所述浮置栅极或者相对于所述控制开关栅极的刻蚀选择比,以便快速去除所述STI HARP,且避免过度损伤所述浮置栅极和所述控制开关栅极。
优选地,在所述的去除晶片上的二氧化硅的方法中,反应的条件可以包括:工艺腔室内的压力为50Torr-300Torr,工艺腔室内的温度为20℃ -80℃。进一步优选地,所述反应的条件包括:工艺腔室内的压力为 200Torr,工艺腔室内的温度为40℃。
优选地,在所述的去除晶片上的二氧化硅的方法中,所述氟化氢气体的流量可以为100sccm-500sccm,所述醇类气体的流量为 100sccm-1000sccm。进一步优选地,所述氟化氢气体的流量为 150sccm-225sccm,所述醇类气体的流量为200sccm-450sccm。
优选地,在所述的去除晶片上的二氧化硅的方法中,所述氟化氢气体与所述醇类气体的流量比可以为0.8~1.2:1。进一步优选地,所述氟化氢气体与所述醇类气体的流量比为1:1。
优选地,在所述的去除晶片上的二氧化硅的方法中,所述醇类气体可以为C1-C8一元醇气体中的至少一种。进一步优选地,所述醇类气体为甲醇、乙醇和异丙醇中的至少一种。
根据本发明的集成电路的制造工艺的优点在于:
1、在去除晶片上的二氧化硅的方法中,采用气相刻蚀工艺,不同于湿法刻蚀工艺或等离子体干法刻蚀工艺,气相刻蚀工艺不容易形成其他副产物,对晶片不会造成电损伤,腔室内干净,颗粒少;同时降低设备成本。
2、在去除晶片上的二氧化硅的方法中,采用高压工艺,提高了SiO2对Si3N4(或多晶硅、HARP等)的刻蚀选择比,还能够降低对衬底损伤。
3、在去除晶片上的二氧化硅的方法中,通过气相刻蚀工艺的化学反应去除SiO2,无固态产物,反应物可以被泵抽出。
4、在去除晶片上的二氧化硅的方法中,低温反应,反应过程简单,无需加热和/或冷却步骤,一步即可完成反应,产能高。
5、去除晶片上的二氧化硅的方法采用的工艺腔室可以与下一道工序的工艺腔室集成在一个真空平台,晶片在去除了其表面的SiO2后,无需破坏其所处的真空环境,即可进入其他工艺腔室进行下一道工序,防止晶片在空气中放置再次氧化,影响后续工艺。
本发明的方法具有其它的特性和优点,这些特性和优点从并入本文中的附图和随后的具体实施方式中将是显而易见的,或者将在并入本文中的附图和随后的具体实施方式中进行详细陈述,这些附图和具体实施方式共同用于解释本发明的特定原理。
附图说明
通过结合附图对本发明示例性实施方式进行更详细的描述,本发明的上述以及其它目的、特征和优势将变得更加明显,其中,在本发明示例性实施方式中,相同的参考标号通常代表相同部件。
图1a示出了具有自然氧化层的集成电路器件的示意图。
图1b示出了根据现有技术的方法去除二氧化硅的效果的示意图。
图2示出了根据本发明的去除晶片上的二氧化硅的方法的步骤的流程图。
图3示出了根据本发明的去除晶片上的二氧化硅的方法的效果的示意图。
图4a、4b和4c分别示出了根据现有技术的HARP填充浅沟道绝缘层轮廓调整的示意图。
图5a、5b、5c和5d分别示出了根据本发明的去除晶片上的二氧化硅的方法在HARP填充浅沟道绝缘层轮廓调整过程中的作用的示意图。
图6a和6b分别示出了具有自然氧化层的器件和根据本发明的方法去除自然氧化层后的器件的示意图。
图7a和7b分别示出了具有衬垫氧化层的器件和根据本发明的方法去除衬垫氧化层后的器件的示意图。
图8a和8b分别示出了具有自然氧化层的器件和根据本发明的方法去除自然氧化层后的器件的示意图。
图9a和9b分别示出了具有氧化物凹槽的集成电路器件和根据本发明的方法去除二氧化硅后的器件的效果的示意图。
具体实施方式
下面将参照附图更详细地描述本发明。虽然附图中显示了本发明的优选实施方式,然而应该理解,可以以各种形式实现本发明而不应被这里阐述的实施方式所限制。相反,提供这些实施方式是为了使本发明更加透彻和完整,并且能够将本发明的范围完整地传达给本领域的技术人员。
图2示出了根据本发明的去除晶片上的二氧化硅的方法的步骤的流程图。
在该实施方式中,根据本发明的去除晶片上的二氧化硅的方法包括:步骤201,向工艺腔室内通入脱水的氟化氢气体和脱水的醇类气体;步骤 202,使所述脱水的氟化氢气体和脱水的醇类气体混合,生成气态的刻蚀剂;步骤203,使所述刻蚀剂与所述工艺腔室内的晶片反应,并使所述工艺腔室内保持高压状态以提高刻蚀选择比;以及步骤204,将所述反应的副产物从所述工艺腔室内抽出。
该实施方式通过使气态的刻蚀剂在高压力下与二氧化硅直接反应,并在反应后将反应产物抽出,实现高选择比、高效率地去除二氧化硅。
下面详细说明根据本发明的去除晶片上的二氧化硅的方法的具体步骤。
在一个示例中,根据本发明的去除晶片上的二氧化硅的方法可以包括:步骤201,向工艺腔室内通入脱水的氟化氢气体和脱水的醇类气体;步骤 202,使所述脱水的氟化氢气体和脱水的醇类气体混合,生成气态的刻蚀剂;步骤203,使所述刻蚀剂与所述工艺腔室内的晶片反应,并使所述工艺腔室内保持高压状态以提高刻蚀选择比;以及步骤204,将所述反应的副产物从所述工艺腔室内抽出。
优选地,所述反应的条件可以包括:工艺腔室内的压力为 50Torr-300Torr,工艺腔室内的温度为20℃-80℃。进一步优选地,所述反应的条件包括:工艺腔室内的压力为200Torr,工艺腔室内的温度为40℃。实验发现高压工艺反应气体更容易凝结在晶片表面并与SiO2发生反应,这时 SiO2去除速率大大增加,而同时Si3N4的去除速率几乎不增加,这样就大大增加SiO2对Si3N4(或多晶硅、HARP等)的去除选择比。
优选地,所述氟化氢气体的流量可以为100sccm-500sccm,所述醇类气体的流量为100sccm-1000sccm。进一步优选地,所述氟化氢气体的流量为 150sccm-225sccm,所述醇类气体的流量为200sccm-450sccm。
优选地,所述氟化氢气体与所述醇类气体的流量比可以为0.8~1.2:1。例如,所述氟化氢气体与所述醇类气体的流量比可以为0.8:1、1:1或1.2:1。进一步优选地,所述氟化氢气体与所述醇类气体的流量比为1:1。使氟化氢气体与醇类气体的流量接近,可以提高去除二氧化硅的均匀性。
优选地,所述醇类气体可以为C1-C8一元醇气体中的至少一种。进一步优选地,所述醇类气体为甲醇(CH3OH)、乙醇(C2H5OH)和异丙醇(IPA) 中的至少一种。
在所述醇类气体为气化的甲醇的情况下;所述刻蚀剂为HF2 -和 CH3OH2 +;所述反应产物为四氟化硅、甲醇以及水。具体地,在采用甲醇 (CH3OH)时,根据本发明的去除晶片上的二氧化硅的方法的反应式可以表示为:
HF+CH3OH→HF2 -+CH3OH2+ (1)
HF2 -+CH3OH2 ++SiO2→SiF4+CH3OH+H2O (2)
可以使用经过脱水的HF气体和脱水的CH3OH气体在腔室内部混合,生成气态的刻蚀剂HF2 -和CH3OH2 +,工艺时腔室压力可以设定为200Torr,温度为40℃,HF2 -和CH3OH2 +混合与SiO2反应生成SiF4、CH3OH和H2O。 CH3OH有很强的吸水性,能够减少H2O在晶片表面的残留量,同时SiF4、 CH3OH和H2O都可以在反应后用泵抽出。
根据本发明的去除晶片上的二氧化硅的方法的优点在于:
1、选择比高。图3示出了根据本发明的去除晶片上的二氧化硅的方法的效果的示意图。如图3所示,本发明通过高压工艺(工艺压力为200Torr) 来提高选择比,实验发现高压工艺(200Torr)反应气体更容易凝结在晶片表面并与SiO2发生反应,这时SiO2去除速率大大增加,而同时Si3N4的去除速率几乎不增加,这样就大大增加SiO2对Si3N4(或多晶硅、HARP等) 的去除选择比。同样,高选择比还降低对衬底损伤。
2、不使用等离子体,不容易形成其他副产物,对衬底不会造成电损伤,腔室内干净,颗粒少;同时降低设备成本。
3、无固态产物,反应物可以被泵抽出,通过化学反应去除SiO2。图5 示出了根据本发明的去除晶片上的二氧化硅的方法的另一效果的示意图。如图5所示,由于反应物扩散好,所以对于密集区域的小孔洞中的SiO2和稀疏区域的SiO2去除量一致,反应生成物气态SiF4,被泵抽出,不会造成小孔洞堵塞,清洗效果好,对小孔洞清洗效果高,去除均匀性高。而且还可以改善衬垫氧化层移除(pad oxide removal)和STI凹槽(recess)刻蚀的负载作用(loading effect)(大,小的孔洞凹槽深刻蚀一致,STI高度一致)。另外CH3OH和H2O也很容易被抽走,不会凝结在腔室壁,颗粒少。
4、低温反应,反应过程简单,无需加热和/或冷却步骤,一步即可完成反应,产能高。
5、本工艺腔室可以与下一道工艺集成在一个真空平台,去除晶片表面 SiO2后在不破真空情况下进行下一道工艺,防止在空气中放置再次氧化,影响下一工艺。例如,硅化(Silicide)工艺中铂镍(NiPt)沉积前;锗硅(SiGe) 沉积前。
应用示例
根据本发明的另一方面,还可以提供一种集成电路制造工艺,所述制造工艺包括如上所述的去除晶片上的二氧化硅的方法。
为便于理解本发明实施方式的方案及其效果,以下给出几个具体应用示例。本领域技术人员应理解,该示例仅为了便于理解本发明,其任何具体细节并非意在以任何方式限制本发明。
示例1:HARP填充浅沟道绝缘层轮廓调整(STIHAPR deposition gap fill
profile modified):
图4a、4b和4c分别示出了根据现有技术的HARP填充浅沟道绝缘层轮廓调整的示意图,其中,图4a为STI(浅沟道隔离)刻蚀之后的器件,图4b为STI HARP沉积过程中的器件,图4c为STI HARP沉积后产生空洞 (void)的器件;图5a、5b、5c和5d分别示出了根据本发明的去除晶片上的二氧化硅的方法在HARP填充浅沟道绝缘层轮廓调整过程中的作用的示意图,其中,图5a为STI(浅沟道隔离)刻蚀之后的器件,图5b为STI HARP 沉积过程中的器件,图5c为采用本发明的去除晶片上的二氧化硅的方法进行STI开口调整的器件,图5d为STI HARP沉积后的器件。
在该示例中,根据本发明的去除晶片上的二氧化硅的方法的步骤为:将脱水的氟化氢气体和脱水的甲醇混合,生成气态的刻蚀剂HF2 -和 CH3OH2 +;然后,将刻蚀剂通入工艺腔室中,与所述工艺腔室内的晶片接触进行反应生成SiF4、CH3OH和H2O,其中,工艺腔室中的压力设定为200Torr,温度保持在40℃;反应完成后,用泵抽出SiF4、CH3OH和H2O。
如图4a、4b和4c所示,STI HAPR沉积是使用CVD方式沉积,由于 28nm STI深宽比大,同时STI刻蚀的轮廓不好,造成STI HARP沉积时很容易产生空洞(void)。如图5a、5b、5c和5d所示,沉积一定厚度的HARP 后就要刻蚀一下STI,让开口变大,这样才能不产生void。现有技术具有固态生成物,小孔洞清洗效率低,产能低。根据本发明的方法可以控制腐蚀速率,控制开口轮廓(profile),增加CVD HARP孔隙填充(gap fill)能力。
示例2:STI Si3N4自然氧化层去除:
图6a和6b分别示出了具有自然氧化层的器件和根据本发明的方法去除自然氧化层后的器件的示意图。
在该示例中,处理步骤与示例1相同。如图6a所示,集成电路制造工艺使用Si3N4作为STI的硬掩膜(Hard Mask)层,去除时使用H3PO4湿法去除,晶片在空气中放置一段时间后在Si3N4层表面会自然氧化一层致密的SiO2层,而H3PO4对SiO2去除速率非常慢,所以在去除Si3N4之前先要去除这层自然氧化层。另外STI的台阶高度(是指STI高出衬底表面的高度)会影响器件的电性性能,这个高度既不能厚,也不能薄,同时STI HARP 是使用CVD方式沉积的SiO2层,薄膜致密性很低,所以去除自然氧化层时需要控制好STI HARP的去除量。图6b是去除Si3N4表面氧化层后的形貌。现有技术中刻蚀SiO2时对HARP的选择比低,不容易控制STI的台阶高度;或者具有固态生成物,小孔洞清洗效率低,产能低。根据本发明的方法采用高压工艺,提高刻蚀SiO2对HARP的选择比,可以很好控制STI 台阶高度。
示例3:集成电路衬垫氧化层去除(IC Pad oxide remove):
图7a和7b分别示出了具有衬垫氧化层的器件和根据本发明的方法去除衬垫氧化层后的器件的示意图。
在该示例中,处理步骤与示例1相同。如图7a所示,衬垫氧化层(Pad oxide)作为STI的硬掩膜层Si3N4的缓冲层,是使用炉管方式在衬底表面热氧化一层SiO2层,28nm工艺厚度大约50A左右(根据不同的工艺选择不同厚度),在后续工艺制造前需要去除。另外STIHARP是使用CVD方式沉积的SiO2,密度低,致密性差,刻蚀速率高。现有技术中刻蚀SiO2对HARP 的选择比低,不容易控制STI的台阶高度,同时产生凹陷(divot),影响电性能。如图7b所示,本发明采用高压工艺,提高刻蚀SiO2对HARP的选择比,控制好STI台阶高度,避免湿法刻蚀产生凹陷的问题。
示例4:沉积锗硅(SiGe)之前去除自然氧化层:
图8a和8b分别示出了具有自然氧化层的器件和根据本发明的方法去除自然氧化层后的器件的示意图。
在该示例中,处理步骤与示例1相同。如图8a所示,SiGe刻蚀后,衬底内部会暴露在空气中而自然氧化,这层氧化层会造成器件电性失效等问题,所以沉积SiGe之前必须先去除干净,同时去除这层SiO2过程不能损伤 Si衬底。28nm SiGe线宽非常小,现有技术中刻蚀SiO2对多晶硅(Poly silicon)选择比低,容易对栅极和Si衬底有损伤;或者具有固态生成物残留,高温升华过程对Si衬底再次氧化,产能低。如图8b所示,本发明使用气相高压工艺,提高刻蚀SiO2对多晶硅的选择比,对栅极和衬底损伤小。
示例5:沉积硅化物(Silicide)之前去除自然氧化层:
图1a和图3分别示出了具有自然氧化层的器件和根据本发明的方法去除二氧化硅后的器件的示意图。
在该示例中,处理步骤与示例1相同。如图1a所示,晶片在空气中放置中Si衬底表面和多晶硅表面会自然氧化一层致密的SiO2层,沉积Ni或 NiPt(5-10%)(在后续工艺中会形成NiPt硅化物)之前必须将这次自然氧化的SiO2层去除掉,不然会造成接触(contact)与衬底之间非常大的接触电阻,同时多晶硅栅极两侧有Si3N4作为绝缘隔离片(spacer),去除SiO2过程不能损伤Si3N4和Si衬底。现有技术中刻蚀SiO2对Si3N4选择比低,容易造成绝缘隔离片尺寸缩小,电漏率增大和Si衬底有损伤问题;或者具有固态生成物残留,孔洞底部SiO2去除效率低,高温升华过程对Si衬底再次氧化,产能低。如图3所示,本发明的方法使用高压工艺,提高SiO2对Si3N4的去除选择比,并且不会有再次氧化问题。
示例6:STI HARP氧化凹槽刻蚀(STI
HARP
oxide
recess
etch):
图9a和9b分别示出了具有氧化物凹槽的集成电路器件和根据本发明的方法去除二氧化硅后的器件的效果的示意图。
在该示例中,处理步骤与示例1相同。如图9a所示,STI凹槽(recess) 工艺是2DNAND制造过程中工艺,由于NAND是存储器件,器件中存储单元(栅极和STI)是密集区域,控制区域(源极/漏极的选择性控制开关栅极)是稀疏区域,在STI凹槽工艺过程中需要器件密集区域和稀疏区域的STI去除量要一致。现有技术中刻蚀SiO2对多晶硅的选择比低,对控制栅极(Control gate)和浮置栅极(floating gate)有损伤;或者具有固态生成物残留,小孔洞清洗效率低,产能低。如图9b所示,本发明的方法使用高压工艺,提高SiO2对多晶硅的去除选择比,没有固态生成物,小孔洞清洗效率高。
本领域技术人员应理解,上面对本发明的实施方式的描述的目的仅为了示例性地说明本发明的实施方式的有益效果,并不意在将本发明的实施方式限制于所给出的任何示例。
以上已经描述了本发明的各实施方式,上述说明是示例性的,并非穷尽性的,并且也不限于所披露的各实施方式。在不偏离所说明的各实施方式的范围和精神的情况下,对于本技术领域的普通技术人员来说许多修改和变更都是显而易见的。本文中所用术语的选择,旨在最好地解释各实施方式的原理、实际应用或对市场中的技术的改进,或者使本技术领域的其它普通技术人员能理解本文披露的各实施方式。
Claims (17)
1.一种集成电路的制造工艺,其特征在于,包括:去除晶片上的二氧化硅的方法,该方法包括:
向工艺腔室内通入脱水的氟化氢气体和脱水的醇类气体;
使所述脱水的氟化氢气体和脱水的醇类气体混合,生成气态的刻蚀剂;
使所述刻蚀剂与所述工艺腔室内的晶片反应,并使所述工艺腔室内保持高压状态以提高刻蚀选择比;以及
将所述反应的副产物从所述工艺腔室内抽出。
2.根据权利要求1所述的集成电路的制造工艺,其特征在于,所述制造工艺包括利用HARP填充浅沟道绝缘层的轮廓调整的子工艺,
在所述子工艺中,首先利用CVD工艺沉积一定厚度的HARP,而后采用所述的去除晶片上的二氧化硅的方法对STI进行刻蚀而使开口变大,重复执行上述沉积和刻蚀操作,直至工艺结束。
3.根据权利要求1所述的集成电路的制造工艺,其特征在于,所述制造工艺包括去除STI的硬掩膜层上的SiO2自然氧化层的子工艺,所述STI的硬掩膜层为Si3N4,
在所述子工艺中,利用所述的去除晶片上的二氧化硅的方法对STI的硬掩膜层表面上的SiO2自然氧化层进行刻蚀,并控制所述SiO2自然氧化层相对于STI HARP的刻蚀选择比,以便快速去除所述SiO2自然氧化层,且避免过度刻蚀STI HARP。
4.根据权利要求1所述的集成电路的制造工艺,其特征在于,所述制造工艺包括去除衬垫氧化层的子工艺,所述衬垫氧化层为采用加热方式在衬底表面氧化形成SiO2层,其为STI的硬掩膜层Si3N4的缓冲层,
在所述子工艺中,利用所述的去除晶片上的二氧化硅的方法对所述衬垫氧化层进行刻蚀,并控制所述衬垫氧化层相对于STI HARP的刻蚀选择比,以便快速去除所述衬垫氧化层,且避免过度刻蚀STI HARP。
5.根据权利要求1所述的集成电路的制造工艺,其特征在于,所述制造工艺包括沉积锗硅之前去除硅衬底上的SiO2自然氧化层的子工艺,
在所述子工艺中,利用所述的去除晶片上的二氧化硅的方法对所述硅衬底上的SiO2自然氧化层进行刻蚀,并控制所述SiO2自然氧化层相对于多晶硅的刻蚀选择比,以便快速去除所述SiO2自然氧化层,且避免过度损伤Si衬底。
6.根据权利要求1所述的集成电路的制造工艺,其特征在于,所述制造工艺包括沉积硅化物之前去除衬底表面和多晶硅栅极表面的SiO2自然氧化层的子工艺,
在所述子工艺中,利用所述的去除晶片上的二氧化硅的方法对所述衬底表面和多晶硅栅极表面的SiO2自然氧化层进行刻蚀,并控制所述SiO2自然氧化层相对于多晶硅的刻蚀选择比,以便快速去除所述SiO2自然氧化层,且避免过度损伤Si衬底。
7.根据权利要求1所述的集成电路的制造工艺,其特征在于,所述制造工艺包括2DNAND存储器制造过程中的STI凹槽子工艺,所述NAND存储器包括位于图形密集区域内的浮置栅极和图形密集区域STI HARP以及位于图形稀疏区域内的控制开关栅极和图形稀疏区域STI HARP,所述浮置栅极和所述控制开关栅极为多晶硅,所述图形密集区域STI HARP和所述图形稀疏区域STI HARP为二氧化硅,
在所述子工艺中,利用所述的去除晶片上的二氧化硅的方法对所述图形密集区域STIHARP和所述图形稀疏区域STI HARP进行刻蚀,并控制所述STI HARP相对于所述浮置栅极或者相对于所述控制开关栅极的刻蚀选择比,以便快速去除所述STI HARP,且避免过度损伤所述浮置栅极和所述控制开关栅极。
8.根据权利要求1-7任一项所述的集成电路的制造工艺,其特征在于,在所述的去除晶片上的二氧化硅的方法中,所述工艺腔室内的压力为50Torr-300Torr。
9.根据权利要求8所述的集成电路的制造工艺,其特征在于,所述工艺腔室内的压力为200Torr。
10.根据权利要求1-7任一项所述的集成电路的制造工艺,其特征在于,在所述的去除晶片上的二氧化硅的方法中,所述工艺腔室内的温度为20℃-80℃。
11.根据权利要求10所述的集成电路的制造工艺,其特征在于,所述工艺腔室内的温度为40℃。
12.根据权利要求1-7任一项所述的集成电路的制造工艺,其特征在于,在所述的去除晶片上的二氧化硅的方法中,所述氟化氢气体的流量为100sccm-500sccm,所述醇类气体的流量为100sccm-1000sccm。
13.根据权利要求12所述的集成电路的制造工艺,其特征在于,所述氟化氢气体的流量为150sccm-225sccm,所述醇类气体的流量为200sccm-450sccm。
14.根据权利要求1-7任一项所述的集成电路的制造工艺,其特征在于,在所述的去除晶片上的二氧化硅的方法中,所述氟化氢气体与所述醇类气体的流量比为0.8~1.2:1。
15.根据权利要求14所述的集成电路的制造工艺,其特征在于,所述氟化氢气体与所述醇类气体的流量比为1:1。
16.根据权利要求1-7任一项所述的集成电路的制造工艺,其特征在于,在所述的去除晶片上的二氧化硅的方法中,所述醇类气体为C1-C8一元醇气体中的至少一种。
17.根据权利要求16所述的集成电路的制造工艺,其特征在于,所述醇类气体为甲醇、乙醇和异丙醇中的至少一种。
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