CN113485523B - Clock compensation method and device - Google Patents
Clock compensation method and device Download PDFInfo
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- CN113485523B CN113485523B CN202110594147.8A CN202110594147A CN113485523B CN 113485523 B CN113485523 B CN 113485523B CN 202110594147 A CN202110594147 A CN 202110594147A CN 113485523 B CN113485523 B CN 113485523B
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- 230000005540 biological transmission Effects 0.000 claims abstract description 81
- 238000012545 processing Methods 0.000 claims description 16
- 238000005516 engineering process Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 11
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- 238000004590 computer program Methods 0.000 description 7
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- 230000006872 improvement Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 108700009949 PTP protocol Proteins 0.000 description 1
- 238000003491 array Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
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Abstract
The present disclosure relates to the field of clock synchronization technologies, and in particular, to a clock compensation method and apparatus. The method is applied to a main control board of network equipment, wherein the main control board comprises a main clock chip, and the method comprises the following steps: acquiring a time point T of the master clock chip, and acquiring transmission time DELAY TX_DELAY between an output pin of the master clock chip and an output interface of the network equipment; determining the sum of the time point T of the master clock chip and the transmission DELAY TX_DELAY as a time point T1 of the output interface of the master clock chip transmitted to the network equipment; transmitting the time point T1 to other network devices through an output interface of the network device, so that the other network devices perform clock synchronization based on the time point T1.
Description
Technical Field
The present disclosure relates to the field of clock synchronization technologies, and in particular, to a clock compensation method and apparatus.
Background
With the advent of high precision time terrestrial transmission demands of TD-SCDMA and TD-LTE systems, various types of high precision time synchronization interfaces are required to be provided by network equipment, base station equipment and the like, and the technology of the high precision time synchronization interface of 1pps+tod proposed by china mobile is formulated, and the specification of the high precision time synchronization 1pps+tod interface is formulated. The output clock synchronization of the GPS satellite positioning system receiver adopts a 1PPS+TOD interface, and each large clock chip manufacturer supports the clock input and output modes of 1PPS+TOD.
The 1pps+tod synchronization technique synchronizes the time every second, i.e., every synchronization is an entire second time, 1PPS is an entire second pulse, and the time is carried in TOD frames. With the development of an infinite communication network, the network will have a great improvement in performance indexes such as peak rate, network delay, system capacity and the like, so that the requirement on time synchronization of the system is gradually improved, wherein the precision of the PTP protocol reaches the level that the error is less than tens of ns, then the 1PPS synchronization delay also needs to meet the requirement, and at the moment, the routing delay of the 1PPS signal at the input and output of the device cannot be ignored, and accurate compensation is necessary.
At present, in a clock compensation mode, an FPGA is added between the output of a clock chip 1PPS and a device connection port, 1PPS wiring delay is compensated into the FPGA, the time (Counter count) increment function of part of the clock chip is realized by the FPGA, and a 1PPS signal is output. However, an FPGA chip is added between the PPS output of the clock chip 1 and the device connection port, so that the FPGA is required to realize the RTC function of the clock chip, and the requirement on the FPGA is high. Meanwhile, 1PPS is generated by the FPGA, so that 1PPS change output by the clock chip can be reflected by 1PPS output by the FPGA only in the next period, namely, 1 second delay is achieved, and the timeliness of clock compensation is not high.
Disclosure of Invention
The application provides a clock compensation method and device, which are used for solving the problem of low clock compensation timeliness in the prior art.
In a first aspect, the present application provides a clock compensation method applied to a main control board of a network device, where the main control board includes a master clock chip, and the method includes:
acquiring a time point T of the master clock chip, and acquiring transmission time DELAY TX_DELAY between an output pin of the master clock chip and an output interface of the network equipment;
determining the sum of the time point T of the master clock chip and the transmission DELAY TX_DELAY as a time point T1 of the output interface of the master clock chip transmitted to the network equipment;
transmitting the time point T1 to other network devices through an output interface of the network device, so that the other network devices perform clock synchronization based on the time point T1.
Optionally, if the network device does not have a time source input; the step of obtaining the time point T of the master clock chip comprises:
determining a local system time as a time point T of the master clock chip;
if the network device has a time source input, the step of acquiring the time point T of the master clock chip includes:
acquiring a time point T' of the time source, and determining transmission DELAY RX_DELAY between an input interface of the network equipment and an input pin of the master clock chip;
and determining the sum of the time point T' of the time source and the transmission DELAY RX_DELAY as the time point T of the master clock chip.
Optionally, the network device further includes a line board card, and the method further includes:
determining a transmission DELAY INNER_DELAY between an output pin of the master clock chip and an input pin of a clock chip of the line board card;
and carrying out clock synchronization on the line board card based on the time point T1 and the transmission DELAY INNER_DELAY.
Optionally, the step of clock synchronizing the line board card based on the time point T1 and the transmission DELAY incer_delay includes:
calculating a difference between the transmission DELAY INNER_DELAY and the transmission DELAY TX_DELAY;
judging whether the difference is greater than or equal to 0;
if the difference is greater than or equal to 0, transmitting the time point T1, the transmission DELAY tx_delay and the transmission DELAY inner_delay to the clock chip of the line board through the output pin of the master clock chip, so that the clock chip sets the time point of the line board to T2, where t2=t1-tx_delay+inner_delay.
Optionally, the method further comprises:
if the difference value is smaller than 0, processing the time point T1 through an FPGA to obtain a time point T3, wherein T3=T1-TX_DELAY;
and transmitting the time point T3 and the transmission DELAY INNER_DELAY to a clock chip of the line board card, so that the clock chip sets the time point of the line board card to be T4, wherein T4=T3+INNER_DELAY.
In a second aspect, the present application provides a clock compensation apparatus, applied to a main control board of a network device, where the main control board includes a main clock chip, the apparatus includes:
an obtaining unit, configured to obtain a time point T of the master clock chip, and obtain a transmission DELAY tx_delay between an output pin of the master clock chip and an output interface of the network device;
a determining unit, configured to determine a sum of a time point T of the master clock chip and the transmission DELAY tx_delay as a time point T1 of an output interface of the master clock chip transmitted to the network device;
and the transmission unit is used for transmitting the time point T1 to other network equipment through an output interface of the network equipment so as to enable the other network equipment to perform clock synchronization based on the time point T1.
Optionally, if the network device does not have a time source input; the acquiring unit is specifically configured to, when acquiring the time point T of the master clock chip:
determining a local system time as a time point T of the master clock chip;
if the network device has a time source input, the acquiring unit is specifically configured to:
acquiring a time point T' of the time source, and determining transmission DELAY RX_DELAY between an input interface of the network equipment and an input pin of the master clock chip;
and determining the sum of the time point T' of the time source and the transmission DELAY RX_DELAY as the time point T of the master clock chip.
Optionally, the network device further includes a line board card, and the apparatus further includes a synchronization unit:
the acquisition unit is further used for acquiring transmission DELAY INNER_DELAY between the output pin of the master clock chip and the input pin of the clock chip of the line board card;
the synchronization unit is configured to perform clock synchronization on the line board card based on the time point T1 and the transmission DELAY INNER_DELAY.
Optionally, when the line board card is clock-synchronized based on the time point T1 and the transmission DELAY INNER_DELAY, the synchronization unit is specifically configured to:
calculating a difference between the transmission DELAY INNER_DELAY and the transmission DELAY TX_DELAY;
judging whether the difference is greater than or equal to 0;
if the difference is greater than or equal to 0, transmitting the time point T1, the transmission DELAY tx_delay and the transmission DELAY inner_delay to the clock chip of the line board through the output pin of the master clock chip, so that the clock chip sets the time point of the line board to T2, where t2=t1-tx_delay+inner_delay.
Optionally, the synchronization unit is further configured to:
if the difference value is smaller than 0, processing the time point T1 through an FPGA to obtain a time point T3, wherein T3=T1-TX_DELAY;
and transmitting the time point T3 and the transmission DELAY INNER_DELAY to a clock chip of the line board card, so that the clock chip sets the time point of the line board card to be T4, wherein T4=T3+INNER_DELAY.
In a third aspect, an embodiment of the present application provides a clock compensation apparatus, including:
a memory for storing program instructions;
a processor for invoking program instructions stored in said memory, performing the steps of the method according to any of the first aspects above in accordance with the obtained program instructions.
In a fourth aspect, embodiments of the present application also provide a computer-readable storage medium storing computer-executable instructions for causing a computer to perform the steps of the method according to any one of the first aspects.
As can be seen from the foregoing, the clock compensation method provided in the embodiments of the present application is applied to a main control board of a network device, where the main control board includes a main clock chip, and the method includes: acquiring a time point T of the master clock chip, and acquiring transmission time DELAY TX_DELAY between an output pin of the master clock chip and an output interface of the network equipment; determining the sum of the time point T of the master clock chip and the transmission DELAY TX_DELAY as a time point T1 of the output interface of the master clock chip transmitted to the network equipment; transmitting the time point T1 to other network devices through an output interface of the network device, so that the other network devices perform clock synchronization based on the time point T1.
By adopting the clock compensation method provided by the embodiment of the application, the master clock chip of the network equipment has the function of 1PPS input synchronization time and the function of outputting 1PPS signals to other equipment for time synchronization. The 1PPS wiring delay compensation output by the clock chip achieves the effect of compensating 1PPS output delay compensation by adjusting the compensation value of the input 1PPS signal, thereby achieving the effect of compensating each 1PPS signal in real time.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following description will briefly describe the drawings that are required to be used in the embodiments of the present application or the description in the prior art, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings may also be obtained according to these drawings of the embodiments of the present application for a person having ordinary skill in the art.
FIG. 1 is a detailed flowchart of a clock compensation method according to an embodiment of the present disclosure;
FIG. 2 is a schematic process diagram of a clock compensation method according to an embodiment of the present disclosure;
FIG. 3 is a schematic structural diagram of a clock compensation device according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of another clock compensation device according to an embodiment of the present application.
Detailed Description
The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to any or all possible combinations including one or more of the associated listed items.
It should be understood that although the terms first, second, third, etc. may be used in embodiments of the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, a first message may also be referred to as a second message, and similarly, a second message may also be referred to as a first message, without departing from the scope of the present application. Depending on the context, furthermore, the word "if" used may be interpreted as "at … …" or "at … …" or "in response to a determination".
Referring to fig. 1, an exemplary embodiment of a detailed flowchart of a clock compensation method is provided, where the method is applied to a main control board of a network device, the main control board includes a main clock chip, and the method includes the following steps:
step 100: and acquiring a time point T of the master clock chip, and acquiring transmission time DELAY TX_DELAY between an output pin of the master clock chip and an output interface of the network equipment.
In the embodiment of the present application, if the network device does not have a time source input; when the time point T of the master clock chip is acquired, a preferred implementation is to determine the local system time as the time point T of the master clock chip.
That is, if the network device does not have an external time source input, the obtained local system time of the network device can be used as the reference time point T of the master clock chip of the network device, so that the problem that the reference time point received by the master clock chip is inaccurate due to clock signal transmission delay generated by wiring can be avoided.
Optionally, if the network device has a time source input, when acquiring the time point T of the master clock chip, a preferred implementation manner is to acquire the time point T' of the time source, and determine a transmission DELAY rx_delay between an input interface of the network device and an input pin of the master clock chip.
That is, if the network device has an external time source input, the master clock chip receives the clock signal T 'input by the external time source, and at this time, since there is a transmission DELAY rx_delay of the clock signal between the input interface of the network device and the input pin of the master clock chip, then compensation processing needs to be performed on the time of the master clock chip, that is, the sum of the time point T' of the external time source and the transmission DELAY rx_delay between the input interface of the network device and the input pin of the master clock chip is determined as the time point T of the master clock chip.
Step 110: and determining the sum of the time point T of the master clock chip and the transmission DELAY TX_DELAY as a time point T1 of the output interface of the network device transmitted by the master clock chip.
Further, the master control board needs to transmit the clock signal to other external network devices, and then, due to the fact that a trace exists between an output pin of a clock chip of the master control board and an output interface of the network device, a transmission DELAY tx_delay exists in clock signal transmission.
Step 120: transmitting the time point T1 to other network devices through an output interface of the network device, so that the other network devices perform clock synchronization based on the time point T1.
From the above, the clock signal transmitted by the other network device at the output interface of the network device is T1.
Still further, the network device further includes a line board card, and then the clock compensation method further includes the steps of:
determining a transmission DELAY INNER_DELAY between an output pin of the master clock chip and an input pin of a clock chip of the line board card;
and carrying out clock synchronization on the line board card based on the time point T1 and the transmission DELAY INNER_DELAY.
In this embodiment, when the line board card is clocked based on the time point T1 and the transmission DELAY INNER_DELAY, a preferred implementation manner is to calculate a difference between the transmission DELAY INNER_DELAY and the transmission DELAY TX_DELAY;
judging whether the difference is greater than or equal to 0;
if the difference is greater than or equal to 0, transmitting the time point T1, the transmission DELAY tx_delay and the transmission DELAY inner_delay to the clock chip of the line board through the output pin of the master clock chip, so that the clock chip sets the time point of the line board to T2, where t2=t1-tx_delay+inner_delay.
Further, if the difference is smaller than 0, processing the time point T1 through the FPGA to obtain a time point T3, where t3=t1-tx_delay;
and transmitting the time point T3 and the transmission DELAY INNER_DELAY to a clock chip of the line board card, so that the clock chip sets the time point of the line board card to be T4, wherein T4=T3+INNER_DELAY.
The following describes the structure of the network device provided in the embodiment of the present application in detail in connection with a specific application scenario. As an example, referring to fig. 2, which is a schematic structural diagram of a network device provided in this embodiment of the present application, the network device includes a main board card and a plurality of line boards (e.g., line board card 1, line board cards 2, … …, line board card N), a clock board of the main board card includes an FPGA and a clock chip (referred to as a master clock chip), if a time point of the master clock chip acquired by the network device is T, when a clock signal is transmitted to an external other network device through a node 3 (an output interface of the network card device), a transmission DELAY tx_delay between an output pin of the master clock chip and an output interface of the network device needs to be determined, and a compensation operation is performed on the time T in advance at the master clock chip, that is, after the master clock chip sets the time point to be t+tx_delay, the clock signal is transmitted to the external other network device through the output interface of the network device, so that the time point when the external other network device receives the clock signal is t+tx_delay.
Further, when the master clock chip performs clock synchronization with other line boards on the network device, since there is a transmission DELAY INNER_DELAY between the master control board and the other line boards, compensation operation needs to be performed in advance, since the master clock chip only has one clock output and has been compensated for once based on the transmission DELAY TX_DELAY between the output pin of the master clock chip and the output interface of the network device, and when the clock signal is synchronized with the other line boards, the clock signal does not need to pass through a route between the output pin of the master clock chip and the output interface of the network device, and then the comprehensively determined compensation value is INNER_DELAY-TX_DELAY and clock compensation is performed based on the INNER_DELAY-TX_DELAY.
For example, if INNER_DELAY-TX_DELAY is positive, the compensation value may be directly set on the PHY of the line card, if INNER_DELAY-TX_DELAY is negative, TX_DELAY may be delayed by 1PPS time of the FPGA to which the master clock output passes, and then issued to the corresponding line card, where the line card only needs to compensate INNER_DELAY.
An exemplary embodiment of a clock compensation device according to the present disclosure is shown in fig. 3, and the device is applied to a main control board of a network device, where the main control board includes a master clock chip, and the device includes:
an obtaining unit 30, configured to obtain a time point T of the master clock chip, and obtain a transmission DELAY tx_delay between an output pin of the master clock chip and an output interface of the network device;
a determining unit 31, configured to determine a sum of a time point T of the master clock chip and the transmission DELAY tx_delay as a time point T1 of the master clock chip transmitted to an output interface of the network device;
and the transmission unit 32 is configured to transmit the time point T1 to other network devices through an output interface of the network device, so that the other network devices perform clock synchronization based on the time point T1.
Optionally, if the network device does not have a time source input; the acquiring unit 30 is specifically configured to, when acquiring the time point T of the master clock chip:
determining a local system time as a time point T of the master clock chip;
if the network device has a time source input, the acquiring unit 30 is specifically configured to:
acquiring a time point T' of the time source, and determining transmission DELAY RX_DELAY between an input interface of the network equipment and an input pin of the master clock chip;
and determining the sum of the time point T' of the time source and the transmission DELAY RX_DELAY as the time point T of the master clock chip.
Optionally, the network device further includes a line board card, and the apparatus further includes a synchronization unit:
the obtaining unit 30 is further configured to obtain a transmission DELAY from an output pin of the master clock chip to an input pin of a clock chip of the line board;
the synchronization unit is configured to perform clock synchronization on the line board card based on the time point T1 and the transmission DELAY INNER_DELAY.
Optionally, when the line board card is clock-synchronized based on the time point T1 and the transmission DELAY INNER_DELAY, the synchronization unit is specifically configured to:
calculating a difference between the transmission DELAY INNER_DELAY and the transmission DELAY TX_DELAY;
judging whether the difference is greater than or equal to 0;
if the difference is greater than or equal to 0, transmitting the time point T1, the transmission DELAY tx_delay and the transmission DELAY inner_delay to the clock chip of the line board through the output pin of the master clock chip, so that the clock chip sets the time point of the line board to T2, where t2=t1-tx_delay+inner_delay.
Optionally, the synchronization unit is further configured to:
if the difference value is smaller than 0, processing the time point T1 through an FPGA to obtain a time point T3, wherein T3=T1-TX_DELAY;
and transmitting the time point T3 and the transmission DELAY INNER_DELAY to a clock chip of the line board card, so that the clock chip sets the time point of the line board card to be T4, wherein T4=T3+INNER_DELAY.
The above units may be one or more integrated circuits configured to implement the above methods, for example: one or more application specific integrated circuits (Application Specific Integrated Circuit, abbreviated as ASIC), or one or more microprocessors (digital singnal processor, abbreviated as DSP), or one or more field programmable gate arrays (Field Programmable Gate Array, abbreviated as FPGA), or the like. For another example, when a unit is implemented in the form of a processing element scheduler code, the processing element may be a general purpose processor, such as a central processing unit (Central Processing Unit, CPU) or other processor that may invoke the program code. For another example, the units may be integrated together and implemented in the form of a system-on-a-chip (SOC).
In a summary of the present invention it is known that,
further, in the clock compensation device provided in the embodiments of the present application, from a hardware level, a hardware architecture schematic diagram of the clock compensation device may be shown in fig. 4, and the clock compensation device may include: a memory 40 and a processor 41,
memory 40 is used to store program instructions; the processor 41 invokes the program instructions stored in the memory 40 to execute the above-described method embodiments in accordance with the obtained program instructions. The specific implementation manner and the technical effect are similar, and are not repeated here.
Optionally, the present application also provides a clock compensation device comprising at least one processing element (or chip) for performing the above-described method embodiments.
Optionally, the present application also provides a program product, such as a computer readable storage medium, storing computer executable instructions for causing the computer to perform the above-described method embodiments.
Here, a machine-readable storage medium may be any electronic, magnetic, optical, or other physical storage device that may contain or store information, such as executable instructions, data, or the like. For example, a machine-readable storage medium may be: RAM (Radom Access Memory, random access memory), volatile memory, non-volatile memory, flash memory, a storage drive (e.g., hard drive), a solid state drive, any type of storage disk (e.g., optical disk, dvd, etc.), or a similar storage medium, or a combination thereof.
The system, apparatus, module or unit set forth in the above embodiments may be implemented in particular by a computer chip or entity, or by a product having a certain function. A typical implementation device is a computer, which may be in the form of a personal computer, laptop computer, cellular telephone, camera phone, smart phone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or a combination of any of these devices.
For convenience of description, the above devices are described as being functionally divided into various units, respectively. Of course, the functions of each element may be implemented in one or more software and/or hardware elements when implemented in the present application.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present application may take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
Moreover, these computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The foregoing description of the preferred embodiments of the present invention is not intended to limit the invention to the precise form disclosed, and any modifications, equivalents, improvements and alternatives falling within the spirit and principles of the present invention are intended to be included within the scope of the present invention.
Claims (6)
1. A clock compensation method, characterized by being applied to a master control board of a network device, the master control board including a master clock chip, the method comprising:
acquiring a time point T of the master clock chip, and acquiring transmission time DELAY TX_DELAY between an output pin of the master clock chip and an output interface of the network equipment;
determining the sum of the time point T of the master clock chip and the transmission DELAY TX_DELAY as a time point T1 of the output interface of the master clock chip transmitted to the network equipment;
transmitting the time point T1 to other network equipment through an output interface of the network equipment so that the other network equipment performs clock synchronization based on the time point T1;
the network device further includes a line card, the method further comprising:
determining a transmission DELAY INNER_DELAY between an output pin of the master clock chip and an input pin of a clock chip of the line board card;
calculating a difference of the transmission DELAY INNER_DELAY minus the transmission DELAY TX_DELAY;
judging whether the difference is greater than or equal to 0;
if the difference value is smaller than 0, processing the time point T1 through an FPGA to obtain a time point T3, wherein T3=T1-TX_DELAY;
and transmitting the time point T3 and the transmission DELAY INNER_DELAY to a clock chip of the line board card, so that the clock chip sets the time point of the line board card to be T4, wherein T4=T3+INNER_DELAY.
2. The method of claim 1, wherein if the network device does not have a time source input; the step of obtaining the time point T of the master clock chip comprises:
determining a local system time as a time point T of the master clock chip;
if the network device has a time source input, the step of acquiring the time point T of the master clock chip includes:
acquiring a time point T' of the time source, and determining transmission DELAY RX_DELAY between an input interface of the network equipment and an input pin of the master clock chip;
and determining the sum of the time point T' of the time source and the transmission DELAY RX_DELAY as the time point T of the master clock chip.
3. The method of claim 1 or 2, wherein the method further comprises:
if the difference is greater than or equal to 0, transmitting the time point T1, the transmission DELAY tx_delay and the transmission DELAY inner_delay to the clock chip of the line board through the output pin of the master clock chip, so that the clock chip sets the time point of the line board to T2, where t2=t1-tx_delay+inner_delay.
4. A clock compensation device, characterized by a main control board applied to a network device, the main control board including a main clock chip, the device comprising:
an obtaining unit, configured to obtain a time point T of the master clock chip, and obtain a transmission DELAY tx_delay between an output pin of the master clock chip and an output interface of the network device;
a determining unit, configured to determine a sum of a time point T of the master clock chip and the transmission DELAY tx_delay as a time point T1 of an output interface of the master clock chip transmitted to the network device;
a transmission unit, configured to transmit the time point T1 to other network devices through an output interface of the network device, so that the other network devices perform clock synchronization based on the time point T1;
the network device further comprises a line board card, and the device further comprises a synchronization unit:
the acquisition unit is further used for acquiring transmission DELAY INNER_DELAY between the output pin of the master clock chip and the input pin of the clock chip of the line board card;
the synchronization unit is configured to calculate a difference value obtained by subtracting the transmission DELAY tx_delay from the transmission DELAY INNER_delay; judging whether the difference is greater than or equal to 0; if the difference value is smaller than 0, processing the time point T1 through an FPGA to obtain a time point T3, wherein T3=T1-TX_DELAY;
and transmitting the time point T3 and the transmission DELAY INNER_DELAY to a clock chip of the line board card, so that the clock chip sets the time point of the line board card to be T4, wherein T4=T3+INNER_DELAY.
5. The apparatus of claim 4, wherein if the network device does not have a time source input; the acquiring unit is specifically configured to, when acquiring the time point T of the master clock chip:
determining a local system time as a time point T of the master clock chip;
if the network device has a time source input, the acquiring unit is specifically configured to:
acquiring a time point T' of the time source, and determining transmission DELAY RX_DELAY between an input interface of the network equipment and an input pin of the master clock chip;
and determining the sum of the time point T' of the time source and the transmission DELAY RX_DELAY as the time point T of the master clock chip.
6. The apparatus of claim 4 or 5, wherein the synchronization unit is further configured to:
if the difference is greater than or equal to 0, transmitting the time point T1, the transmission DELAY tx_delay and the transmission DELAY inner_delay to the clock chip of the line board through the output pin of the master clock chip, so that the clock chip sets the time point of the line board to T2, where t2=t1-tx_delay+inner_delay.
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