CN103105889A - Clock synchronous device and system for Field Programmable Gate Array (FPGA) prototype test plate piling - Google Patents
Clock synchronous device and system for Field Programmable Gate Array (FPGA) prototype test plate piling Download PDFInfo
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Abstract
The invention discloses a clock synchronous device and a system for Field Programmable Gate Array (FPGA) prototype test plate piling, wherein the clock synchronous device for FPGA prototype test plate piling comprises a clock chip, a master control chip, at least one slave FPGA chip and at least one high-speed connector, wherein the main control chip further comprises a first data selector, a second data selector, a clock management unit and a global clock buffer. The master chip comprises a local clock input pin, a piling clock input pin, a selective signal input pin, a selective signal input pin, a feedback clock input pin, a slave FPGA clock synchronization clock signal output pin, a feedback clock synchronization clock signal output pin and a high-speed connector synchronization clock signal output pin. The clock synchronous device and the system for FPGA prototype test plate piling utilize a master control chip inner lock phrase loop to feed back, the time delay of a master control chip inner routing is equal to the corresponding routing time delay of an outer PCB plate, and the clocks which are output to all slave FPGA chip are enabled to achieve synchronization.
Description
Technical field
The invention belongs to FPGA prototype verification technical field, relate to especially a kind of clock synchronization apparatus and system of FPGA prototype verification stack of plates.
Background technology
field programmable gate array (Field Program Gate Array, FPGA) prototype verification is a kind of SOC (system on a chip) (System on Chip that builds on FPGA, SOC) and special IC (Application Specific Integrated Circuit, ASIC) methodology of prototype, can carry out easily hardware verification and early stage software development, the method is also referred to as ASIC prototype verification or SOC prototype verification, can accelerate the exploitation of the designs such as ASIC, shorten the R﹠D cycle, reduce the cost of development of ASIC application system, improved the success ratio of flow.
In FPGA prototype verification field, when the capacity of the fpga logic door of veneer does not also reach user's logic demand, tend to adopt stacking method.FPGA can realize by the connection of interconnection IO the mutual transmission of signal.When designing the stacking scheme of FPGA prototype verification plate, it is very important that the design of clock synchronous seems.Consider complicated SOC/ASIC design, need multiple-plate FPGA to work in coordination with and complete, will inevitably produce the demand of synchronous clock source.The quality of the synchronizing quality of FPGA prototype verification plate clock source has often directly determined the complexity that verifiable SOC/ASIC designs.
In prior art, in FPGA prototype verification field, the realization of clock synchronous by sharing single crystal oscillator, perhaps shares single programmable clock often, unanimously realizes multiple FPGA clock synchronous in lamina by clock source to the PCB cabling of each sheet FPGA.Also need to realize clock synchronous by means of the equal connecting line of time-delay for multilayer board.This method both had been subject to the restriction of single crystal oscillator or the shared pin of single programmable clock, also was subject to the impact of connecting line quality, and the quantity of synchronous clock is difficult to flexible change, and quality also can not be guaranteed.
Summary of the invention
For addressing the above problem, the object of the present invention is to provide a kind of clock synchronization apparatus of FPGA prototype verification stack of plates, in order to feed back by phaselocked loop in main control chip, the inner cabling of main control chip and the corresponding cabling time delay of outside pcb board equate, make to export to respectively and realize synchronous from the clock of fpga chip.
Another purpose of the present invention is to provide a kind of clock system of FPGA prototype verification stack of plates, main FPGA prototype verification plate and stacking by high-speed interface from FPGA prototype verification plate, be used for by phaselocked loop feedback in main control chip, the inner cabling of main control chip and the corresponding cabling time delay of outside pcb board equate, and the cabling time delay of corresponding signal transmission line equates, makes to export to respectively and realizes synchronous from the clock of fpga chip.
For achieving the above object, technical scheme of the present invention is:
a kind of clock synchronization apparatus of FPGA prototype verification stack of plates, comprise clock chip, main control chip, at least one is from fpga chip and high-speed interface, wherein main control chip further comprises the first data selector, the second data selector, Clock Managing Unit and global clock impact damper, main control chip comprises the local clock input pin, stacking clock input pin, select the signal input pin, the feedback clock input pin, from FPGA clock synchronous clock signal output pin, feedback clock synchronizing clock signals output pin and high-speed interface synchronizing clock signals output pin,
Described clock chip is for generation of local crystal oscillator clock signal;
Two input ports of described the first data selector are respectively by the local crystal oscillator clock signal of local clock input pin input, by the stacking clock input signal of stacking clock input pin input, be local crystal oscillator clock signal or stacking clock input signal by the high-low level control inputs of selecting signal pins;
Two input ports of described the second data selector by feedback clock input pin input feedback clock input signal, are arbitrary feedback clock input signal by the high-low level control inputs of selecting the signal input pin;
The output signal of the output port of described the first data selector inputs to the input end of clock mouth of Clock Managing Unit, and the output signal of the output port of the second data selector inputs to the feedback clock input port of Clock Managing Unit;
the output signal of the output port of described Clock Managing Unit inputs to the global clock impact damper, again by global clock impact damper output multi-channel synchronizing clock signals, by exporting FPGA clock synchronous clock signal from FPGA clock synchronous clock signal output pin extremely from fpga chip, by high-speed interface synchronizing clock signals output pin output high-speed interface synchronizing clock signals, export the feedback clock synchronizing clock signals to the feedback clock input pin by feedback clock synchronizing clock signals output pin, the phaselocked loop of Clock Managing Unit is adjusted input end of clock mouth and the same homophase frequently of feedback clock input port of Clock Managing Unit.
Preferably, by the isometric method of chip internal cabling, the local clock input pin is to the cabling time delay of the first data selector, and stacking clock input pin is to the cabling time delay of the first data selector, and the feedback clock input pin is equal to the cabling time delay of the second data selector;
The cabling time delay of the output port of the first data selector to the output port of the cabling time delay of the clock input signal port of clock administrative unit and the second data selector to the feedback clock input port of clock administrative unit equates;
Global clock buffer output end mouth divides and is clipped to from FPGA clock synchronous clock signal output pin, and the cabling time delay of feedback clock synchronizing clock signals output pin and high-speed interface synchronizing clock signals output pin equates;
By the isometric method of exterior PC B cabling, make from FPGA clock synchronous clock signal output pin equal to the cabling time delay of feedback clock input pin to cabling time delay and feedback clock synchronizing clock signals output pin from fpga chip.
Preferably, the phaselocked loop of described Clock Managing Unit is digital phase-locked loop or analog phase-locked look.
A kind of clock system of FPGA prototype verification stack of plates, the clock synchronization apparatus that comprises some FPGA prototype verification stack of plates as above, wherein one be set on main FPGA prototype verification plate, being arranged on from FPGA prototype verification plate in addition, main FPGA prototype verification plate with undertaken stacking from FPGA prototype verification plate by high-speed interface, the high-speed interface synchronizing clock signals of main FPGA prototype verification plate inputs to the stacking clock input pin from FPGA prototype verification plate
For main FPGA prototype verification plate, control the local crystal oscillator clock signal that is input as of the first data selector by the high-low level of selecting signal pins,
For from FPGA prototype verification plate, control the stacking clock input signal that is input as of the first data selector by the high-low level of selecting signal pins,
The high-speed interface synchronizing clock signals output pin of the main control chip of main FPGA prototype verification plate is to the cabling time delay of high-speed interface, the high-speed interface of main FPGA prototype verification plate is to the interface propagation delay of the high-speed interface of slave plate, from the high-speed interface of FPGA prototype verification plate to from the cabling time delay sum of the stacking clock input pin of FPGA prototype verification plate with equate to the cabling time delay from fpga chip from FPGA clock synchronous clock signal output pin.
Compared with prior art, the present invention has following technique effect:
(1) clock chip provides clock source to main control chip, Clock Managing Unit module in main control chip realizes phase-locked loop circuit by external feedback, and realize the clock synchronous of main control chip clock output pin by the wiring method of main control chip inside, simplify circuit design structure, improved clock synchronous efficient;
(2) main control chip of slave plate utilizes data selector to select stacking clock as clock source, guarantee that simultaneously two kinds of clock sources are equal to the time delay of the feedback clock input of clock administrative unit module from the input pin of main control chip to clock input and the feedback signal of clock administrative unit module from the input pin of main control chip, simplify circuit design structure, improved clock synchronous efficient;
(3) main control chip of main FPGA prototype verification plate and when stacking from the main control chip of FPGA prototype verification plate, make the clock line of the FPGA of feedback line in the plate and the clock synchronous that equates to realize output by the main control chip clock line time delay from the main control chip of FPGA prototype verification plate that stacking interface arrives by the isometric method of the PCB cabling of outside, simplify circuit design structure, improved clock synchronous efficient and precision.
Description of drawings
Fig. 1 is the principle assumption diagram of clock synchronization apparatus of the FPGA prototype verification stack of plates of the embodiment of the present invention;
Fig. 2 is the principle mechanism figure of clock system of the FPGA prototype verification stack of plates of the embodiment of the present invention.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, is not intended to limit the present invention.
On the contrary, the present invention contain any by claim definition make on marrow of the present invention and scope substitute, modification, equivalent method and scheme.Further, in order to make the public, the present invention is had a better understanding, in hereinafter details of the present invention being described, detailed some specific detail sections of having described.Do not have for a person skilled in the art the description of these detail sections can understand the present invention fully yet.
With reference to figure 1, be depicted as the principle assumption diagram of clock synchronization apparatus of the FPGA prototype verification stack of plates of the embodiment of the present invention, in order to simplify the structure of exemplary plot, the embodiment of the present invention is described from fpga chip as example take two, a main control chip band in figure.Those skilled in the art be to be understood that in concrete application process not with main control chip with the number from fpga chip the present invention is limited.as shown in Figure 1, the clock synchronization apparatus of the FPGA prototype verification stack of plates of the embodiment of the present invention comprises clock chip 10, main control chip 20, two from fpga chip, be respectively first from fpga chip 213 and second from fpga chip 214, and high-speed interface 30, wherein main control chip 20 further comprises the first data selector 201, the second data selector 202, Clock Managing Unit 203 and global clock impact damper 204, main control chip 20 comprises local clock input pin 205, stacking clock input pin 206, select signal input pin 207, feedback clock input pin 208, from FPGA clock synchronous clock signal output pin, feedback clock synchronizing clock signals output pin 209 and high-speed interface synchronizing clock signals output pin 210.Clock chip 10 is for generation of local crystal oscillator clock signal; Two input ports of the first data selector 201 are respectively by the local clock input pin 205 local crystal oscillator clock signal LOC_CLK of input, by the stacking clock input pin 206 stacking clock input signal ST_CLLK of input, high-low level SEL control inputs by selection signal pins 207 is local crystal oscillator clock signal LOC_CLK or stacking clock input signal ST_CLLK, in concrete application example, if as the clock synchronization apparatus on main FPGA prototype verification plate, select local crystal oscillator clock signal LOC_CLK as the input of main control chip; If the clock synchronization apparatus from the FPGA prototype verification plate selects stacking clock input signal ST_CLLK as the input of main control chip.By above setting, no matter as main FPGA prototype verification plate still from FPGA prototype verification plate, the clock synchronization apparatus of this FPGA prototype verification stack of plates can flexible adaptation, has improved the range of application of the clock synchronization apparatus of FPGA prototype verification stack of plates.Two input ports of the second data selector 202 are by feedback clock input pin 208 input feedback clock input signal FB_CLK, high-low level SEL control inputs by selection signal input pin 207 is arbitrary feedback clock input signal, because be all the same feedback clock input signal of input.By above setting, realized selecting the multiplexing of signal input pin 207, simplified circuit structure design, reduced the systematic error introducing.the output signal of the output port of the first data selector 201 inputs to the input end of clock mouth CLKIN of Clock Managing Unit 203, and the output signal of the output port of the second data selector 202 inputs to the feedback clock input port CLKFB of Clock Managing Unit 203, the output signal of the output port CLKOUT of Clock Managing Unit inputs to the global clock impact damper, again by global clock impact damper output multi-channel synchronizing clock signals, by exporting FPGA clock synchronous clock signal from FPGA clock synchronous clock signal output pin extremely from fpga chip, by high-speed interface synchronizing clock signals output pin 210 output high-speed interface synchronizing clock signals, export the feedback clock synchronizing clock signals to the feedback clock input pin by feedback clock synchronizing clock signals output pin 209, the phaselocked loop of Clock Managing Unit is adjusted input end of clock mouth CLKIN and the same homophase frequently of feedback clock input port CLKFB of Clock Managing Unit 203.By the setting of global buffer, the clock that has reduced Clock Managing Unit outputs to the time-delay between the clock output pin of main control chip, has reduced the difficulty that manual placement-and-routing makes each clock output time-delay equate.By the isometric method of chip internal cabling, the cabling time delay Tin_loc of local clock input pin 205 to first data selectors 201, the cabling time delay Tin_st of stacking clock input pin 206 to first data selectors 201, and the cabling time delay Tin_fb1 of feedback clock input pin 208 to second data selectors 202 equates; The cabling time delay Tin_fb2 of the output port of the first data selector 201 to the output port of the cabling time delay Tin_clk of the clock input signal port of clock administrative unit 203 and the second data selector 202 to the feedback clock input port of clock administrative unit 203 equates, meeting above condition namely meets: Tin_loc+Tin_clk=Tin_st+Tin_clk=Tin_fb1+Tin_fb2, can make the interior clock input signal port of Clock Managing Unit and the clock signal synchronization at feedback clock input port place
Global clock impact damper 204 output ports divide and are clipped to the first time delay To_fpga1 from FPGA clock synchronous clock signal output pin, to the second time delay To_fpga2 from FPGA clock synchronous clock signal output pin, equate to the time delay To_fb of feedback clock synchronizing clock signals output pin 209 and the cabling time delay To_st of high-speed interface synchronizing clock signals output pin 210, that is: To_fpga1=To_fpga2=To_st=To_fb, satisfy this condition and can make four clock output signals of main control chip keep clock synchronous.
By the isometric method of exterior PC B cabling, make from FPGA clock synchronous clock signal output pin to the cabling time delay from fpga chip, feedback clock synchronizing clock signals output pin 209 equates to the cabling time delay of feedback clock input pin 208, is Tex_fpga1=Tex_fpga2=Tex_fb shown in diagram.
In concrete application example, the phaselocked loop of Clock Managing Unit is digital phase-locked loop or analog phase-locked look.Digital phase-locked loop is based on the digital sampling mode, insert to postpone between input clock and feedback clock, makes that the input numeral is consistent with the rising edge of feedback clock to be realized; Analog phase-locked look has been used voltage control delay, with VCO realize with digital phase-locked loop in similar delay feature.Their difference is: the scope of analog phase-locked look frequency adjustment is larger, and that digital phase-locked loop is done on phase control is better, and noise immunity is stronger.
A kind of clock synchronization apparatus of FPGA prototype verification stack of plates is provided by above embodiment, can have guaranteed well to realize in veneer clock synchronous.Simultaneously this device is well suited for being arranged on many of FPGA and carries out stacking clock synchronous, below clock system of the FPGA prototype verification stack of plates of the embodiment of the present invention that realizes by this device is described in detail.
With reference to figure 2, be depicted as the clock system of a kind of FPGA prototype verification stack of plates of the embodiment of the present invention, the clock synchronization apparatus that comprises the FPGA prototype verification stack of plates in some above-described embodiments, wherein one be set on main FPGA prototype verification plate, being arranged on from FPGA prototype verification plate in addition, for simplied system structure, describe from the FPGA witness plate as example to technical scheme of the present invention to comprise a main FPGA prototype verification plate and one in diagram.Those skilled in the art are to be understood that it does not limit the number of the FPGA prototype verification plate that can comprise in the embodiment of the present invention.Main FPGA prototype verification plate with undertaken stacking from FPGA prototype verification plate by high-speed interface, the high-speed interface synchronizing clock signals of main FPGA prototype verification plate inputs to the stacking clock input pin from FPGA prototype verification plate, for main FPGA prototype verification plate, control the local crystal oscillator clock signal that is input as of the first data selector by the high-low level of selecting signal pins, for from FPGA prototype verification plate, control the stacking clock input signal that is input as of the first data selector by the high-low level of selecting signal pins.should satisfy simultaneously, the high-speed interface synchronizing clock signals output pin of the main control chip of main FPGA prototype verification plate is to the cabling time delay Tex_st of high-speed interface, the high-speed interface of main FPGA prototype verification plate is to the interface propagation delay Tex_j of the high-speed interface of slave plate, from the high-speed interface of FPGA prototype verification plate to from the cabling time delay Tex_st sum 2*Tex_st+Tex_j of the stacking clock input pin of FPGA prototype verification plate with equate Tex_fpga1 from FPGA clock synchronous clock signal output pin to the cabling time delay from fpga chip, namely satisfy Tex_fpga1=Tex_fpga2=Tex_fb=2*Tex_st+Tex_j.
Namely under the state of FPGA prototype verification stack of plates, satisfy simultaneously To_fpga1=To_fpga2=To_st=To_fb, Tex_fpga1=Tex_fpga2=T ex_fb=2*Tex_st+Tex_j, satisfy simultaneously above situation, can be so that the clock signal at the clock input pin place of the FPGA of main FPGA prototype verification plate and keep synchronous to the clock signal from the ST_CLK pin of FPGA prototype verification plate through stacking interface realizes the clock synchronous from fpga chip of polylith FPGA prototype verification stack of plates.
The above is only preferred embodiment of the present invention, not in order to limiting the present invention, all any modifications of doing within the spirit and principles in the present invention, is equal to and replaces and improvement etc., within all should being included in protection scope of the present invention.
Claims (4)
1. the clock synchronization apparatus of a FPGA prototype verification stack of plates, it is characterized in that, comprise clock chip, main control chip, at least one is from fpga chip and high-speed interface, wherein main control chip further comprises the first data selector, the second data selector, Clock Managing Unit and global clock impact damper, main control chip comprises the local clock input pin, stacking clock input pin, select the signal input pin, the feedback clock input pin, from FPGA clock synchronous clock signal output pin, feedback clock synchronizing clock signals output pin and high-speed interface synchronizing clock signals output pin,
Described clock chip is for generation of local crystal oscillator clock signal;
Two input ports of described the first data selector are respectively by the local crystal oscillator clock signal of local clock input pin input, by the stacking clock input signal of stacking clock input pin input, be local crystal oscillator clock signal or stacking clock input signal by the high-low level control inputs of selecting signal pins;
Two input ports of described the second data selector by feedback clock input pin input feedback clock input signal, are arbitrary feedback clock input signal by the high-low level control inputs of selecting the signal input pin;
The output signal of the output port of described the first data selector inputs to the input end of clock mouth of Clock Managing Unit, and the output signal of the output port of the second data selector inputs to the feedback clock input port of Clock Managing Unit;
the output signal of the output port of described Clock Managing Unit inputs to the global clock impact damper, again by global clock impact damper output multi-channel synchronizing clock signals, by exporting FPGA clock synchronous clock signal from FPGA clock synchronous clock signal output pin extremely from fpga chip, by high-speed interface synchronizing clock signals output pin output high-speed interface synchronizing clock signals, export the feedback clock synchronizing clock signals to the feedback clock input pin by feedback clock synchronizing clock signals output pin, the phaselocked loop of Clock Managing Unit is adjusted input end of clock mouth and the same homophase frequently of feedback clock input port of Clock Managing Unit.
2. the clock synchronization apparatus of FPGA prototype verification stack of plates according to claim 1, is characterized in that,
By the isometric method of chip internal cabling, the local clock input pin is to the cabling time delay of the first data selector, stacking clock input pin is to the cabling time delay of the first data selector, and the feedback clock input pin is equal to the cabling time delay of the second data selector;
The cabling time delay of the output port of the first data selector to the output port of the cabling time delay of the clock input signal port of clock administrative unit and the second data selector to the feedback clock input port of clock administrative unit equates;
Global clock buffer output end mouth divides and is clipped to from FPGA clock synchronous clock signal output pin, and the cabling time delay of feedback clock synchronizing clock signals output pin and high-speed interface synchronizing clock signals output pin equates;
By the isometric method of exterior PC B cabling, make from FPGA clock synchronous clock signal output pin equal to the cabling time delay of feedback clock input pin to cabling time delay and feedback clock synchronizing clock signals output pin from fpga chip.
According to claim 1 to 2 arbitrary described FPGA prototype verification stack of plates clock synchronization apparatus, it is characterized in that, the phaselocked loop of described Clock Managing Unit is digital phase-locked loop or analog phase-locked look.
4. the clock system of a FPGA prototype verification stack of plates, it is characterized in that, the clock synchronization apparatus that comprises some described FPGA prototype verification stack of plates as arbitrary as claims 1 to 3, wherein one be set on main FPGA prototype verification plate, being arranged on from FPGA prototype verification plate in addition, main FPGA prototype verification plate with from FPGA prototype verification plate, by high-speed interface, undertaken stacking, the high-speed interface synchronizing clock signals of main FPGA prototype verification plate inputs to the stacking clock input pin from FPGA prototype verification plate
For main FPGA prototype verification plate, control the local crystal oscillator clock signal that is input as of the first data selector by the high-low level of selecting signal pins,
For from FPGA prototype verification plate, control the stacking clock input signal that is input as of the first data selector by the high-low level of selecting signal pins,
The high-speed interface synchronizing clock signals output pin of the main control chip of main FPGA prototype verification plate is to the cabling time delay of high-speed interface, the high-speed interface of main FPGA prototype verification plate is to the interface propagation delay of the high-speed interface of slave plate, from the high-speed interface of FPGA prototype verification plate to from the cabling time delay sum of the stacking clock input pin of FPGA prototype verification plate with equate to the cabling time delay from fpga chip from FPGA clock synchronous clock signal output pin.
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| CN104731161A (en) * | 2013-12-20 | 2015-06-24 | 恩智浦有限公司 | Stacked Clock Distribution For Low Power Devices |
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| CN105306091B (en) * | 2015-11-13 | 2018-11-09 | 成都前锋电子仪器有限责任公司 | Crystal oscillation fractional frequency circuit for radio general measuring instrument RF local oscillator circuit |
| CN105653279A (en) * | 2015-12-29 | 2016-06-08 | 小米科技有限责任公司 | Clock system and wakeup method for mobile terminal and functional chip |
| CN107168458A (en) * | 2017-06-07 | 2017-09-15 | 苏州瑞迈斯医疗科技有限公司 | A kind of clock distributing equipment for being used to digitize pet detector |
| WO2018223778A1 (en) * | 2017-06-07 | 2018-12-13 | 苏州瑞迈斯医疗科技有限公司 | Clock distribution apparatus for digital pet detector |
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| CN109525381A (en) * | 2018-12-11 | 2019-03-26 | 中国电子科技集团公司第五十四研究所 | A kind of clock synchronization apparatus suitable for assisting multiplexer-demultiplexer |
| CN111579973B (en) * | 2019-02-19 | 2022-03-08 | 深圳市汇顶科技股份有限公司 | Chip synchronous testing method, chip, electronic equipment and storage medium |
| CN111579973A (en) * | 2019-02-19 | 2020-08-25 | 深圳市汇顶科技股份有限公司 | Chip synchronous testing method, chip, electronic equipment and storage medium |
| CN114115438B (en) * | 2020-08-31 | 2023-07-04 | 超聚变数字技术有限公司 | FPGA prototype verification clock device |
| CN114115438A (en) * | 2020-08-31 | 2022-03-01 | 超聚变数字技术有限公司 | FPGA prototype verification clock device |
| CN112291027A (en) * | 2020-10-27 | 2021-01-29 | 杭州迪普科技股份有限公司 | Clock selection method, device, equipment and computer readable storage medium |
| CN112486248A (en) * | 2020-11-20 | 2021-03-12 | 芯原微电子(上海)股份有限公司 | Transceiving signal recovery method, system and terminal based on multi-FPGA interconnection |
| CN112558684A (en) * | 2020-12-08 | 2021-03-26 | 芯原微电子(上海)股份有限公司 | DUT (device under test) clock signal recovery method and system based on multi-FPGA (field programmable Gate array) interconnection |
| CN112260684A (en) * | 2020-12-21 | 2021-01-22 | 上海国微思尔芯技术股份有限公司 | Clock alignment system and method for prototype verification system |
| CN113485523B (en) * | 2021-05-28 | 2024-03-08 | 新华三信息安全技术有限公司 | Clock compensation method and device |
| CN113485523A (en) * | 2021-05-28 | 2021-10-08 | 新华三信息安全技术有限公司 | Clock compensation method and device |
| CN113076710A (en) * | 2021-06-07 | 2021-07-06 | 上海国微思尔芯技术股份有限公司 | Clock signal global synchronization and division verification method and device, electronic equipment and storage medium |
| CN113468005A (en) * | 2021-06-29 | 2021-10-01 | 展讯通信（上海）有限公司 | Chip verification system and clock circuit thereof |
| CN113468005B (en) * | 2021-06-29 | 2023-02-24 | 展讯通信（上海）有限公司 | Chip verification system and clock circuit thereof |
| CN114063704A (en) * | 2021-08-30 | 2022-02-18 | 浪潮电子信息产业股份有限公司 | RTC clock circuit |
| CN114063704B (en) * | 2021-08-30 | 2023-11-03 | 浪潮电子信息产业股份有限公司 | RTC clock circuit |
| CN114443372A (en) * | 2021-12-21 | 2022-05-06 | 天津光电通信技术有限公司 | Method for realizing multipath backup homologous clock |
| CN114461010A (en) * | 2021-12-22 | 2022-05-10 | 天津光电通信技术有限公司 | Circuit for simultaneously accessing FPGA GTY bank to 4-path clock and implementation method |
| CN114461010B (en) * | 2021-12-22 | 2023-12-15 | 天津光电通信技术有限公司 | Circuit for enabling FPGA (field programmable gate array) GTY bank to be simultaneously connected with 4 paths of clocks and implementation method |
| CN115268568A (en) * | 2022-07-31 | 2022-11-01 | 北京汤谷软件技术有限公司 | Chip FPGA prototype verification clock system |
| CN115268568B (en) * | 2022-07-31 | 2024-06-28 | 北京汤谷软件技术有限公司 | Chip FPGA prototype verification clock system |
| CN117350210B (en) * | 2023-11-09 | 2024-03-01 | 上海合见工业软件集团有限公司 | Clock control system |
| CN117350210A (en) * | 2023-11-09 | 2024-01-05 | 上海合见工业软件集团有限公司 | Clock control system |
| CN117608951A (en) * | 2023-11-30 | 2024-02-27 | 中国人民解放军国防科技大学 | Clock domain-crossing sampling circuit and method for large-scale FPGA platform |
| CN117608951B (en) * | 2023-11-30 | 2024-05-10 | 中国人民解放军国防科技大学 | Clock domain-crossing sampling circuit and method for large-scale FPGA platform |
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