CN113484711A

CN113484711A - Multi-device parallel high-temperature grid bias test platform and test method thereof

Info

Publication number: CN113484711A
Application number: CN202110776550.2A
Authority: CN
Inventors: 蔡雨萌; 徐子珂; 许灏; 赵志斌; 马慧远
Original assignee: North China Electric Power University
Current assignee: North China Electric Power University
Priority date: 2021-07-09
Filing date: 2021-07-09
Publication date: 2021-10-08
Anticipated expiration: 2041-07-09
Also published as: CN113484711B

Abstract

The multi-device parallel high-temperature grid bias test platform comprises a grid bias voltage source, a power device analyzer, an NI digital IO, a computer host, an LED display screen, a heating device, a multi-device measurement main board and a relay power supply battery; the grid bias voltage source, the power device analyzer and the NI digital IO are respectively connected with the computer host through a USB transmission line, a GPIB transmission line and a network cable to realize communication connection and remote control; the NI digital IO is connected with a 9pin wiring terminal on the multi-device test mainboard, so that a corresponding action signal is provided for state switching of the relay; the relay power supply battery provides working voltage for the relay; the heating sheet in the heating device is attached to the tested device and used in cooperation with temperature control to heat the tested device and provide high-temperature conditions.

Description

Multi-device parallel high-temperature grid bias test platform and test method thereof

Technical Field

The invention relates to a test in the field of power semiconductor devices, in particular to a high-temperature grid bias test platform suitable for multi-device parallel and integrated experiment and measurement and a test method thereof.

Background

In recent years, with the development of power electronics technology, power electronics devices have been widely used in power systems. Silicon carbide based devices are gradually replacing silicon based devices in applications such as high power by virtue of high temperature, high voltage, high frequency, low loss, etc. However, silicon carbide based devices have interface state densities two to three orders of magnitude higher than silicon based devices, with the attendant problem of more severe gate oxide reliability. Therefore, more and more researchers are studying the reliability of the gate oxide, and one important and common method is a high-temperature gate bias experiment.

At present, the conditions of experiment and measurement are different aiming at a high-temperature grid bias experiment platform of multiple devices. When a high-temperature grid bias experiment is carried out, the device is under the conditions of high temperature and grid bias; when the parameters are measured, the device needs to be taken out of the high-temperature biased stress environment, then the parameters are measured by using instruments such as a power device analyzer, and the like, at the moment, the device is not in the high-temperature environment any more, and operations such as plugging and unplugging the device need to be performed manually in the process. In the process from high temperature to room temperature, the device can recover to a certain degree, so that certain errors exist between the measured parameter values and actual values in the experimental process, and the experimental result is inaccurate.

A power device analyzer in the prior art is a commonly used power device parameter measuring instrument, and includes a plurality of modules, including a high voltage module, a high power module, a GND module, a capacitance measuring module (CMU), and the like. When different parameters are measured, the grid drain source electrode of the device is connected with the module according to requirements, clicking starts after connection is completed, and the power device analyzer automatically realizes parameter measurement.

In addition, the parasitic inductance has a large influence on the capacitance measurement, and thus the parasitic inductance in the capacitance measurement circuit needs to be strictly controlled. In a multi-device parallel high-temperature grid bias experiment, a capacitance parameter measuring circuit needs to meet the requirements that a single device measures the shortest loop and the measurement loops of multiple devices are highly symmetrical. However, the existing high-temperature grid bias experimental platform does not relate to the circuit design of capacitance parameter measurement when multiple devices are in parallel.

The heating mode is an important part of a high-temperature grid deflection experiment, and the heating modes commonly adopted by the existing high-temperature grid deflection experiment platform mainly comprise a constant temperature box heating mode and a heating table heating mode. The incubator has larger weight and volume and is not easy to move, so that devices or a mainboard need to be placed in the incubator, and the operation is inconvenient; the volume of the heating table is much smaller than that of the thermostat, but the volume is still larger than that of the devices, so when multiple devices are parallel, the intervals among the devices need to be set larger, and all the devices can only be on the same plane, and the heating mode limits the layout and is extremely not beneficial to the control of parasitic inductance.

Disclosure of Invention

The invention aims at the technical problems to be solved by the prior art:

1. the experiment and the measurement are separated, and manpower and material resources are wasted. In order to solve the problem, the invention designs a program-controlled high-temperature grid deflection experiment platform integrating the experiment and the measurement. The multi-device parallel measurement main board comprises an experimental circuit and a measurement circuit, and the switching between the experimental circuit and the measurement circuit is realized by a relay. If the device parameters need to be measured, operations such as plugging and unplugging devices are not needed, and the switching from experimental conditions to measurement conditions can be completed only by modifying the command control relay action on the upper computer, so that the device parameters under the high-temperature environment can be measured. The defects of separation of experiment and measurement and excessive manual operation of devices in the prior art are overcome.

2. And controlling the parasitic inductance of the multi-device parallel capacitance measuring circuit. The measuring main board for the high-temperature grid bias experimental platform designed by the invention places the connecting terminal of the CMU module in the middle position, and 4 devices and circuits thereof are completely and symmetrically distributed in a square shape around the connecting terminal. Based on the distribution, the distances from the 4 devices to the CMU wiring terminal are shortest and equal, the parasitic inductance of the capacitance measuring circuit is greatly reduced, and the accuracy of capacitance measurement is improved.

3. Limitations of the heating means. The conventional heating method can limit the layout of the devices on the main board, thereby being unfavorable for the control of parasitic inductance. In order to overcome the defects of the existing heating mode, the high-temperature grid deflection experiment platform designed by the invention adopts a ceramic heating sheet to be attached to a device for heating, and is matched with temperature control for use. The heating plate is made of ceramic and has good heat-conducting property. In addition, the heating plate is small in size, simple and flexible to operate, and the space occupied by the heating plate attached to the device is small, so that more possibilities are provided for the layout of the device, and the device can not be placed on the same plane any more.

The technical scheme adopted by the invention is as follows:

the multi-device parallel high-temperature grid bias experiment platform comprises a grid bias voltage source, a power device analyzer, an NI digital IO, a computer host, an LED display screen, a heating device, a multi-device measurement main board and a relay power supply battery; it is characterized in that: the grid bias voltage source, the power device analyzer and the NI digital IO are respectively connected with the computer host through a USB transmission line, a GPIB transmission line and a network cable to realize communication connection and remote control; and the NI digital IO is connected with a 9pin wiring terminal on the multi-device test mainboard, so that a corresponding action signal is provided for the on-off of the relay. The switching between an experimental state and a measuring state in the high-temperature grid bias experimental process and the switching between each static characteristic parameter and each capacitance measurement are realized through the action of the relay; the relay power supply battery provides working voltage for the relay; the heating sheet in the heating device is attached to the tested device and used in cooperation with temperature control to heat the tested device and provide high-temperature conditions.

Preferably: the multi-device measurement main board includes: the device comprises a device socket, a BIAS + and a BIAS-two connecting terminals, three coaxial BNC terminals including HP1, HP2 and GND, and two coaxial BNC terminals including CMU-HIGH and CMU-LOW; each device corresponds to 8 relays and a 9pin wiring terminal for connecting NI digital IO control; the grid BIAS voltage source is connected to the BIAS + and BIAS-two connecting terminals through a positive lead and a negative lead;

the two high-power modules and the GND module of the power device analyzer are used for measuring static IV parameters of the device and are connected to HP1, HP2 and GND interfaces of three triaxial BNC terminals in a multi-device measuring mainboard through cables; and a capacitance measurement CMU module of the power device analyzer is connected to a CMU-HIGH and CMU-LOW interface of the multi-device measurement main board by a cable.

The invention also discloses a semiconductor parameter testing method which is realized by the semiconductor parameter testing platform with multiple parallel devices.

Has the advantages that:

the experimental measurement is integrated and automated.

Accuracy of multi-device parallel CV characteristic measurement.

Light and flexible heating mode.

Drawings

FIG. 1 is a schematic diagram of a high temperature grid bias experiment platform; wherein: 1: computer display screen, 2: computer host, 3: power device analyzer, 4: heating device, 5: multi-device measurement motherboard, 6: relay power supply battery, 7: NI digital IO, 8: a gate bias voltage source.

FIG. 2 is a schematic diagram of the control logic of the single device experimental and measurement circuit of the present invention.

Fig. 3 is a layout schematic diagram of a four-device measurement main board and a heating device of the invention, wherein 1 to 4 in the diagram are components of the heating device, and 5 to 11 are interfaces of the multi-device measurement main board, wherein reference numerals in the diagram are defined as: 1: heating plate supporting power supply, 2: temperature controller, 3: heating sheet, 4: thermocouple, 5: BIAS + interface, 6: BIAS-interface, 7: CMU-LOW interface, 8: CMU-HIGH interface, 9: HP1 interface, 10: HP2 interface, 11: and (4) GND interface.

FIG. 4 is a schematic diagram of the top layer wiring of the PCB of the multi-device measurement motherboard of the present invention.

FIG. 5 is a schematic diagram of the bottom layer wiring of the PCB of the multi-device measurement motherboard of the present invention.

Detailed Description

As shown in fig. 1. The multi-device parallel high-temperature grid bias experiment platform comprises a grid bias voltage source, a power device analyzer, an NI digital IO, a computer host, an LED display screen, a heating device, a multi-device measurement main board and a relay power supply battery; it is characterized in that: the grid bias voltage source, the power device analyzer and the NI digital IO are respectively connected with the computer host through a USB transmission line, a GPIB transmission line and a network cable to realize communication connection and remote control; and the NI digital IO is connected with a 9pin wiring terminal on the multi-device test mainboard, so that a corresponding action signal is provided for the on-off of the relay. The switching between an experimental state and a measuring state in the high-temperature grid bias experimental process and the switching between each static characteristic parameter and each capacitance measurement are realized through the action of the relay; the relay power supply battery provides working voltage for the relay; the heating sheet in the heating device is attached to the tested device and used in cooperation with temperature control to heat the tested device and provide high-temperature conditions.

The multi-device measurement main board is an important main body of the experimental platform and comprises a device socket, a BIAS + and a BIAS-two connecting terminal, three coaxial BNC terminals HP1, HP2 and GND, and two coaxial BNC terminals CMU-HIGH and CMU-LOW. Each device corresponds to 8 relays and is used for connecting a 9pin wiring terminal controlled by NI digital IO. The grid BIAS voltage source is connected to a BIAS + and BIAS-terminal interface of the multi-device measurement mainboard through a positive lead and a negative lead to provide grid BIAS for the devices; the heating plate is attached to the device and placed, and is matched with temperature control for use, so that the tested device is heated, and a high-temperature condition is provided. The two together provide experimental conditions for high temperature grid bias.

After the high-temperature grid bias stress is interrupted, IV and CV characteristic parameters of a device are measured by depending on a power device analyzer, two high-power modules and a GND module of the power device analyzer are used for measuring static IV parameters of the device, and cables are connected to HP1, HP2 and GND interfaces of a multi-device measuring mainboard; the CMU module is used for measuring the capacitance of a device, and is connected to a CMU-HIGH and CMU-LOW interface of a main board of the device measurement by a cable.

Example 1

As shown in fig. 2. The invention adopts 12 switches which are numbered as S1-12 in sequence. S1 connecting the BIAS + interface with the device grid; s2 connecting the HP1 interface with the device gate; s3, connecting the CMU-HIGH interface with the grid of the device; s4 connecting the drain electrode and the source electrode of the device; s5 connecting the HP2 interface and the device drain; s6 is connected with the GND interface and the source electrode of the device; s7 connecting switch S11 with the device drain; s8 connecting switch S12 with the source of the device; s9 connecting the BIAS-interface and the device source; s10 connecting the CMU-LOW interface and the device drain; s11 connecting switch S7 with CMU-LOW interface and AC guiding end; s12 connects switch S8 with CMU-LOW interface, AC keying terminal.

When a high-temperature grid BIAS experiment is carried out, the drain source of the device is in short circuit, a grid BIAS voltage source applies BIAS to the grid source of the device, namely the grid of the device is connected with the BIAS + terminal interface, and the source of the device is connected with the BIAS-terminal interface. The corresponding switch action conditions are as follows: switches S1, S4 and S9 are closed, and the remaining switches are open. The BIAS + terminal interface is connected to the device gate through switch S1, the BIAS-terminal interface is connected to the device source through switch S9, and the device drain is shorted to the device source through switch S4.

When proceeding with the threshold voltage V_THDuring measurement, a certain voltage is applied to the drain and the source of the device to provide a condition for conducting the device, the grid voltage of the device is increased to a value higher than the threshold voltage from a value lower than the threshold voltage by a certain step length, the drain current of the device is increased in the process, and when the leakage current is increased to a set value, the corresponding grid voltage is the threshold voltage. Taking a C2M0080120D device as an example, when the threshold voltage is measured, a voltage of 10V is applied to the drain and the source of the device, the gate voltage of the device is increased from 0V to 5V in steps of 100mV, and when the drain current reaches 5mA, the corresponding gate voltage is the threshold voltage. In order to realize the measurement of the threshold voltage, voltage needs to be applied to a gate source and a drain source of the device, namely the gate and the drain of the device are respectively connected with two high-power modules of a power device analyzer, the source of the device is connected with a GND (ground) module of the power device analyzer, after the connection is finished, a threshold voltage measurement window of the power device analyzer (for example, the power device analyzer with the model number of Agilent B1505A) is opened, and the threshold voltage can be automatically measured after clicking is started. Namely, the grid of the device is connected with the HP1 interface, the drain of the device is connected with the HP2 interface, and the source of the device is connected with the GND interface. The corresponding switch action conditions are as follows: switches S2, S5, and S6 are closed, and the remaining switches are open. The HP1 port communicates with the device gate through switch S2, the HP2 port communicates with the device drain through switch S5, and the GND port communicates with the device source through switch S6.

When gate leakage current I is performed_gssWhen the leakage source electrode of the semiconductor power device is in short circuit, the grid-source electrode voltage of the device is increased to a certain limit value from 0V in a certain step length, and the measured grid current is the grid leakage current Igss. Taking the C2M0080120D device as an example, when the gate leakage current is measured, the drain-source of the device is shorted, the gate voltage of the device is increased from 0V by steps of 100mV until the gate current reaches 250nA, and the corresponding gate current is the gate leakage current Igss when the gate voltage of the device is 20V. In order to measure the grid leakage current, a voltage is applied to the grid source electrode of the device, and the drain source electrode of the deviceAnd (3) the grid of the power device analyzer is in an extremely short circuit, namely the grid and the drain of the device are respectively connected with two high-power modules of the power device analyzer, the source of the device is connected with a GND module of the power device analyzer, after the connection is finished, a grid leakage current measurement window of the power device analyzer (such as the power device analyzer with the model number of Agilent B1505A) is opened, and the automatic measurement can be carried out after clicking is started. Namely, the grid of the device is connected with the HP1 interface, the drain of the device is connected with the HP2 interface, and the source of the device is connected with the GND interface. The corresponding switch action conditions are as follows: switches S2, S5, and S6 are closed, and the remaining switches are open. The HP1 port communicates with the device gate through switch S2, the HP2 port communicates with the device drain through switch S5, and the GND port communicates with the device source through switch S6.

When the gate drain parasitic capacitance C is performed_gdAnd gate-source parasitic capacitance C_gsIn measurement, the grid drain parasitic capacitance C is measured by adopting an AC calibration technology by a power device analyzer (such as a power device analyzer with the model number of Agilent B1505A)_gdWhen the connection is finished, a gate and a drain of the device are respectively connected with a HIGH end and a LOW end of the CMU module, a source of the device is connected with an AC (alternating Current) tuning end, and after the connection is finished, a gate-drain parasitic capacitance measuring window of a power device analyzer (such as a power device analyzer with the model number of Agilent B1505A) is opened, and automatic measurement can be carried out after clicking is started. The corresponding switch action conditions are as follows: switches S3, S7, and S8 are closed, switches S11 and S12 are open to the left contact, and the remaining switches are open; the device gate is connected to the CMU-HIGH interface via switch S3, the device drain is connected to the CMU-LOW interface via switches S7 and S11, and the device source is connected to the AC keying terminal via switches S8 and S12. Measuring gate source parasitic capacitance C_gsAnd when the connection is finished, a grid source electrode parasitic capacitance measuring window of a power device analyzer is opened, and automatic measurement can be carried out after clicking is started. The corresponding switch action conditions are as follows: switches S3, S7, and S8 are closed, switches S11 and S12 are opened to the right contact, and the remaining switches are opened; the device gate is connected to the CMU-HIGH interface via switch S3, the device drain is connected to the AC keying terminal via switches S7 and S11, and the device source is connected to the CMU-LOW interface via switches S8 and S12.

When measuring the input capacitance C_issWhen the device is connected, the grid electrode of the device is connected with the HIGH end of a CMU module (such as a power device analyzer with the model of Agilent B1505A), the drain-source electrode of the device is connected with the LOW end of the CMU module after being in short circuit, after the connection is completed, the input capacitance measuring window of the power device analyzer (such as the power device analyzer with the model of Agilent B1505A) is opened, and automatic measurement can be carried out after clicking is started. The corresponding switch states are: switches S3, S4, and S10 are closed, and the remaining switches are open. The device gate is connected to the CMU-HIGH interface via switch S3, the device drain is connected to the device source via switch S4, and the device drain is connected to the CMU-LOW interface via switch S10.

Example 2

See fig. 3 for a schematic illustration. The embodiment realizes the high-temperature gate bias experiment and parameter measurement of the four-device high-temperature gate bias experiment.

The interfaces CMU-HIGH and CMU-LOW of the capacitance measurement CMU module of the power device analyzer are connected, and the interfaces are positioned in the right center of the main board; the HP1 and the HP2 which are connected with the high-power module of the power device analyzer are connected with a GND interface, and the interfaces are positioned at one side edge of the mainboard; and the BIAS + and BIAS-interfaces are connected with the grid BIAS voltage source and are positioned on the same side of the mainboard.

Since the switches S1 and S9 operate simultaneously, they can share a single double-pole double-throw relay, similarly, the switches S5 and S6 share a single double-pole double-throw relay, the switches S7 and S8 share a single double-pole double-throw relay, the switches S11 and S12 share a single double-pole double-throw relay, and the switches S2, S3, S4 and S10 each individually use a single double-pole double-throw relay, and share 8 double-pole double-throw relays, which are sequentially numbered as J1-J8, and each double-pole double-throw relay is controlled by a single signal. The invention uses a mechanical relay, which has a positive control end and a negative control end, 6 contacts, wherein 2 public contacts, 2 normally open contacts and 2 normally closed contacts. When the control end does not apply voltage, the relay is in a default state, namely the common contact is connected with the normally closed contact, when the control end applies positive voltage, the relay is switched, and the common contact is connected with the normally open contact. A 9pin wiring terminal is arranged beside each device, wherein 8 pins are respectively connected to positive control ends of 8 relays, namely a transmission path of a control signal; the other pin is a common terminal and is connected to the negative control terminals of the 8 relays.

The corresponding relation between the switches S1-S12 and the relays J1-J8 is as follows: the switches S1 and S9 correspond to the relay J1, and the default state of the relay J1 corresponds to the disconnection of the switches S1 and S9; the switch S2 corresponds to the relay J2, and the default state of the relay J2 corresponds to the switch S2 being off; the switch S3 corresponds to the relay J3, and the default state of the relay J3 corresponds to the switch S3 being off; the switch S4 corresponds to the relay J4, and the default state of the relay J4 corresponds to the switch S4 being off; the switch S10 corresponds to the relay J5, and the default state of the relay J5 corresponds to the switch S10 being off; the switches S5 and S6 correspond to the relay J6, and the default state of the relay J6 corresponds to the disconnection of the switches S5 and S6; the switches S7 and S8 correspond to the relay J7, and the default state of the relay J7 corresponds to the disconnection of the switches S7 and S8; the switches S11 and S12 correspond to the relay J8, and the default state of the relay J8 corresponds to the switches S11 and S12 being opened to the left. According to the above, when the gate bias is applied in the high-temperature gate bias experiment, the switches S1, S4 and S9 are closed, i.e., the relays J1 and J4 switch states; measuring threshold voltage VTH and gate leakage current I_gssWhen the switches S2, S5 and S6 are closed, i.e., the relays J2 and J6 switch states; measuring gate drain parasitic capacitance C_gdWhen the relay is in the normal state, the switches S3, S7 and S8 are closed, the switches S11 and S12 are opened to the left contact, namely the relays J3 and J7 are in a switching state, and the relay J8 is in a default state; measuring gate source parasitic capacitance C_gsWhen the switches S3, S7 and S8 are closed, the switches S11 and S12 open to the right contact, i.e., the relays J3, J7 and J8 switch states; measuring input capacitance C_issWhen this happens, switches S3, S4, and S10 are closed, i.e., relays J3, J4, and J5 switch states.

Four power semiconductor tested devices and auxiliary relays thereof are distributed around the CMU-HIGH and CMU-LOW interfaces in a square symmetrical mode. The wiring relating to the capacitance measuring circuit also follows the principle of symmetry to the greatest extent.

See fig. 4. The upper left device, the upper right device, the lower left device and the lower right device are sequentially marked as I, II, III and IV, and the numbers 1 to 36 are line segment marks of wiring. I, II devices are closer to CMU-LOW interface than III, IV devices, so I, II devices are inconsistent with the linear distance between III, IV devices and CMU-LOW interface, and the linear distance between I, II devices and III, IV devices and CMU-HIGH interface is also inconsistent with the same reason, but the length of copper wires in the two devices is the same through the layout of the circuit in the actual PCB board, thus ensuring the consistency of parasitic inductance. Switches involved in capacitance measurement include switches S3, S4, S7, S8, S10, S11, and S12, all disposed near the CMU-HIGH and CMU-LOW interface, minimizing the copper wire length of the capacitance measurement circuit to ensure that parasitic inductance is minimized. How to ensure consistent copper wire lengths in the capacitance measuring circuit is explained in detail below.

The routing connecting the grid of the I-type device and the CMU-HIGH interface is No. 1, 2, 3, 4, 5, 11 and 12 line segments; the traces connecting the gate of the device II and the CMU-HIGH interface are No. 13, 14, 15, 16, 17, 18 and 19 line segments; the wire connecting the gate of the III device with the CMU-HIGH interface is 6, 7, 8, 9, 10, 11 and 12 wire segments; the traces connecting the gate of the device IV and the CMU-HIGH interface are line segments 13, 14, 20, 21, 22, 23 and 24. The wires connecting the grids of the I and III devices and the CMU-HIGH interface are completely symmetrical about the CMU-HIGH interface, and the wires connecting the grids of the II and IV devices and the CMU-HIGH interface are completely symmetrical about the CMU-HIGH interface. 1. The lengths of the

line sections

6, 19 and 24 are equal, the lengths of the line sections 2, 7, 18 and 23 are equal, the lengths of the line sections 3, 8, 17 and 22 are equal, the lengths of the

line sections

4, 9, 16 and 21 are equal, the lengths of the

line sections

5, 10, 15 and 10 are equal, the lengths of the line sections 11 and 14 are equal, and the lengths of the line sections 12 and 13 are equal, so that the consistency of the routing lengths from the CMU-HIGH interface to the gates of the four devices is ensured, namely, the consistency of parasitic inductances between the CMU-HIGH interface and the gates of the four devices is ensured.

The wires connecting the AC guarding end and the No. I device relay are No. 25, No. 26 and No. 27 wire segments, the wires connecting the AC guarding end and the No. II device relay are No. 28, No. 29 and No. 30 wire segments, the wires connecting the AC guarding end and the No. III device relay are No. 31, No. 32 and No. 33 wire segments, and the wires connecting the AC guarding end and the No. IV device relay are No. 34, No. 35 and No. 36 wire segments. The traces connecting the drain source electrodes of the I and III devices and the AC keying end and the traces connecting the drain source electrodes of the II and IV devices and the AC keying end are completely symmetrical about the CMU-HIGH interface. 25. The lengths of the line segments 28, 31 and 34 are equal, the lengths of the line segments 26, 29, 32 and 35 are equal, and the lengths of the line segments 27, 30, 33 and 36 are equal, so that the consistency of the lengths of the traces from the AC guarding end to the drain and source electrodes of the four devices is ensured, namely the consistency of parasitic inductances between the AC guarding end and the drain and source electrodes of the four devices is ensured.

Referring to fig. 5, the top left device, top right device, bottom left device, and bottom right device are labeled i, ii, iii, and iv in that order, and the numbers 1-19 are the line segment labels of the wiring.

The routing connecting the grid of the device I and the CMU-LOW interface is

line segments

1, 2, 3, 4 and 5; the routing for connecting the grid electrode of the device II with the CMU-LOW interface is line segments of No. 6, No. 7, No. 8, No. 9 and No. 10; the routing connecting the grid of the III device with the CMU-LOW interface is No. 11, 12, 13, 14 and 15 line segments; the traces connecting the gate of the device IV and the CMU-LOW interface are line segments of No. 11, No. 16, No. 17, No. 18 and No. 19. The routing connecting the grids of the I and III devices with the CMU-LOW interface and the routing connecting the grids of the II and IV devices with the CMU-LOW interface are completely symmetrical about the CMU-LOW interface. 1. The sum of the lengths of the

line sections

2, 3, 4 and 5, the sum of the lengths of the

line sections

6, 7, 8, 9 and 10, the sum of the lengths of the line sections 11, 12, 13, 14 and 15 and the sum of the lengths of the

line sections

11, 16, 17, 18 and 19 are equal, so that the lengths of the traces from the CMU-LOW interface to the drain and source electrodes of the four devices are consistent, namely the parasitic inductances between the CMU-LOW interface and the drain and source electrodes of the four devices are consistent.

The parasitic inductances among the CMU-HIGH interface, the CMU-LOW interface and the AC guiding end are all consistent, so that the consistency of the parasitic inductances during capacitance measurement of the four devices is ensured, and the accuracy of CV characteristic measurement is further ensured.

The whole heating part comprises four heating sheets, a power supply matched with the heating sheets, a thermocouple and a PID constant temperature accurate temperature control instrument (temperature controller). The heating plate is made of ceramic materials, has good heat transfer performance and is attached to a device for placement. The heating plate is matched with a power supply to convert 220V commercial power into 24V low voltage and then add the 24V low voltage to the heating plate, and the heating plate works normally. The thermocouple has the temperature measuring function, one end of the thermocouple is clamped between the ceramic heating plate and the tested device, the other end of the thermocouple is connected to the temperature controller, and a display screen of the temperature controller can display the measured temperatures of the heating plate and the tested device. The power supply matched with the heating sheet is a constant voltage source, and if the heating sheet is electrified all the time, the temperature of the heating sheet is continuously increased. Therefore, in order to realize temperature control, the temperature controller, the heating sheet and the power supply matched with the heating sheet are connected in series. A switch is arranged in the temperature controller, and when the measured temperature exceeds a preset value, the switch is switched off, namely, the voltage applied on the heating sheet is removed, so that the temperature of the heating sheet is reduced; conversely, when the measured temperature is lower than the preset value, the switch is closed, i.e., a voltage is applied to the heating plate, thereby increasing the temperature of the heating plate. During the continuous adjustment process, the temperature of the heating sheet is stabilized to be about the preset value. The relative position between the heating device fittings is not fixed, so the layout is flexible. And the heating plate has small volume and hardly occupies the space around the device. Under the condition of not influencing the heating performance, the heating mode is not only flexible and light, but also does not influence the layout among multiple devices.

And one end of the NI digital IO is connected to the upper computer to obtain an instruction, and the other end of the NI digital IO is connected to a wiring terminal led out by the relay to transmit a control signal to the relay so as to control the action of the relay. A9 pin binding post has all been placed by every device, totally 4 9pin binding posts, 4 NI digit IO of event sharing, and every NI digit IO controls one set of relay that a device used.

The relay power supply battery provides 24V direct current voltage to supply power for NI digital IO.

The grid BIAS voltage source is connected with two leads and connected with two terminal interfaces of BIAS + and BIAS-on the multi-device test mainboard, and the grid BIAS voltage source provides grid BIAS for the tested device. In the whole high-temperature grid bias experiment process, the grid bias voltage source is always in a working state. Because the power device analyzer cannot measure parameters of a plurality of devices at the same time, when one device is in a measuring state, the other three tested devices still need to be in a high-temperature grid bias environment, which requires that a grid bias voltage source is in a working state all the time. For example, measuring the parameters of device under test No. 1, the switches S1 and S9 connected to device under test No. 1 are opened, and the switches S1 and S9 connected to device under test No. 2, 3 and 4 are still closed and connected to the gate bias voltage source.

Power device analyzer for measuring device IV characteristic parameter-threshold voltage V_THGate leakage current I_gssAnd CV characteristic parameter-gate-source parasitic capacitance C_gsParasitic capacitance C of grid and drain_gdAn input capacitor C_issAnd the like. The high power module, the GND module and the CMU module are all provided by a power device analyzer. The power device analyzer is connected to the upper computer through a GPIB transmission line and transmits the measurement data to the upper computer.

Through the technical scheme of the invention, the following purposes are achieved:

1. automation of the experiment and measurement. The NI digital IO is connected with the upper computer and the relay control end, the upper computer is only required to be operated to control the relay to act in the experiment and measurement process, and operations such as plugging and unplugging of devices or rewiring are not required.

2. The experiment and the measurement are integrated. The switch is utilized to realize the switching between the experimental conditions and the measurement conditions, and the whole experimental platform realizes the integration.

3. And (4) measuring parameters in a high-temperature environment. When the experimental state is switched to the measuring state, the position and the temperature condition of the device are not changed, so that the device is still in the high-temperature condition when the parameters of the device are measured.

4. A square layout with the capacitance measurement terminals CMU-HIGH and CMU-LOW as the center, around which 4 devices are symmetrically distributed. The layout effectively reduces the parasitic inductance of the capacitance measuring loop and improves the accuracy of capacitance measurement.

The 5.4 device-to-capacitance measurement terminals CMU-HIGH are in line length with the CMU-LOW. The lengths of the wires are consistent, so that the consistency of parasitic inductance is guaranteed, the consistency of capacitance measuring conditions of 4 devices is guaranteed, and the effectiveness of measuring results is enhanced.

6. The ceramic heating plate is attached to the device and matched with a heating mode used for temperature control. The heating mode saves space, is flexible and portable, and eliminates the limitation on the layout of devices on the mainboard.

Claims

1. The multi-device parallel high-temperature grid bias test platform comprises a grid bias voltage source, a power device analyzer, an NI digital IO, a computer host, an LED display screen, a heating device, a multi-device measurement main board and a relay power supply battery; it is characterized in that: the grid bias voltage source, the power device analyzer and the NI digital IO are respectively connected with the computer host through a USB transmission line, a GPIB transmission line and a network cable to realize communication connection and remote control; the NI digital IO is connected with a 9pin wiring terminal on the multi-device test mainboard, so that a corresponding action signal is provided for the on-off of the relay; the relay power supply battery provides working voltage for the relay; the heating plate in the heating device is attached to the tested device and used in cooperation with temperature control.

2. The multi-device parallel high temperature gate bias test platform of claim 1, wherein: the multi-device measurement main board includes: the device comprises a device socket, a BIAS + and a BIAS-two connecting terminals, three coaxial BNC terminals including HP1, HP2 and GND, and two coaxial BNC terminals including CMU-HIGH and CMU-LOW; each device corresponds to 8 relays and a 9pin wiring terminal for connecting NI digital IO control; the grid BIAS voltage source is connected to the BIAS + and BIAS-two connecting terminals through a positive lead and a negative lead; the two high-power modules and the GND module of the power device analyzer are used for measuring static IV parameters of devices and are connected to HP1, HP2 and GND interfaces of three triaxial BNC terminals in a multi-device measuring mainboard through cables; the CMU module is connected to the CMU-HIGH and CMU-LOW interfaces of the multi-device measurement main board by cables.

3. A multi-device parallel high temperature gate bias test platform according to claim 2, wherein: the 8 relays are numbered sequentially from J1 to J8; the relay is in a default state when no input voltage exists and is in a switching state when the input voltage exists; j1 connecting the BIAS + terminal with the device gate, the BIAS-terminal with the device source; j2 connects HP1 interface with device gate; j3 connecting the CMU-HIGH interface with the device gate; j4 connecting drain and source of the device; j5 connecting the CMU-LOW interface and the device drain; j6 is connected with the HP2 interface and the device drain, and the GND interface and the device source; j7 is connected with the drain electrode and the source electrode of the device and a relay J8; j8 connects J7 with CMU-LOW interface, AC guiding end.

4. A semiconductor parameter testing method realized by the multi-device parallel high-temperature grid bias testing platform claimed in claim 2.

5. The semiconductor parameter testing method according to claim 4, wherein: the testing method comprises the steps of applying a grid bias testing method to a semiconductor device to be tested, measuring static parameters of threshold voltage and grid leakage current, and measuring grid source parasitic capacitance C_gsTest method_、Measuring gate drain parasitic capacitance C_gdTest method and measuring input capacitance C_issAnd (4) a test method.

6. The test method according to claim 5, characterized in that: the method for applying gate bias test to the semiconductor device under test further comprises: the grid electrode of the semiconductor device to be tested is connected with the positive end BIAS + terminal interface of the grid BIAS voltage source, and the drain-source electrode is in short connection with the negative end BIAS-terminal interface of the grid BIAS voltage source.

7. The test method according to claim 5, characterized in that: and when the static parameters of the threshold voltage and the grid leakage current are measured, the grid and the drain of the semiconductor device to be measured are connected with the high-power module, and the source is connected with the GND module.

8. The test method according to claim 5, characterized in that: measuring gate source parasitic capacitance C_gsAnd meanwhile, the grid electrode of the device is connected with the positive end of the CMU module of the power device analyzer, the source electrode of the device is connected with the negative end of the CMU module of the power device analyzer, and the drain electrode of the device is connected with the shielding end.

9. The test method according to claim 5, characterized in that: measuring gate drain parasitic capacitance C_gdAnd meanwhile, the grid electrode of the device is connected with the positive end of the CMU module of the power device analyzer, the drain electrode of the device is connected with the negative end of the CMU module of the power device analyzer, and the source electrode of the device is connected with the shielding end.

10. The test method according to claim 5, characterized in that: measuring input capacitance C_issAnd meanwhile, the grid electrode of the device is connected with the positive end of the CMU module, and the drain-source electrode of the device is connected with the negative end of the capacitance measurement CMU module of the power device analyzer after being in short circuit.