CN113471138A - Preparation method of semiconductor substrate and semiconductor device - Google Patents
Preparation method of semiconductor substrate and semiconductor device Download PDFInfo
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- CN113471138A CN113471138A CN202110757022.2A CN202110757022A CN113471138A CN 113471138 A CN113471138 A CN 113471138A CN 202110757022 A CN202110757022 A CN 202110757022A CN 113471138 A CN113471138 A CN 113471138A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 132
- 239000000758 substrate Substances 0.000 title claims abstract description 108
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 238000002955 isolation Methods 0.000 claims abstract description 142
- 238000000034 method Methods 0.000 claims abstract description 46
- 238000005530 etching Methods 0.000 claims abstract description 22
- 238000000151 deposition Methods 0.000 claims abstract description 15
- 238000005468 ion implantation Methods 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 238000001039 wet etching Methods 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 6
- 230000000903 blocking effect Effects 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 6
- 238000000231 atomic layer deposition Methods 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 5
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 3
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 5
- 239000000969 carrier Substances 0.000 abstract description 4
- 230000008021 deposition Effects 0.000 description 5
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N sulfuric acid Substances OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 108091006149 Electron carriers Proteins 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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Abstract
The invention provides a preparation method of a semiconductor substrate and a semiconductor device. The method comprises the following steps: forming an active region and an isolation trench on a semiconductor substrate; depositing insulating oxide in the isolation trench and on the surface of the active region, wherein the insulating oxide in the isolation trench is an isolation structure, and the insulating oxide on the surface of the isolation structure and the surface of the active region is an isolation layer; removing the isolation layer to enable the surface of the isolation structure to be flush with the surface of the active region; etching the active region to a preset depth to form an active groove; and epitaxially growing a semiconductor substrate in the active groove to enable the surface of the active region to be flush with the surface of the isolation structure. The preparation method can eliminate the stress of the isolation structure and the isolation groove, ensures that the active region is not damaged by the stress to generate defects or cracks, simultaneously avoids influencing the mobility of current carriers in the groove of the device to influence the performance of the device, and improves the yield of the semiconductor device.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a preparation method of a semiconductor substrate and a semiconductor device.
Background
In the manufacturing process of a semiconductor device, active regions and isolation regions located between the active regions are usually formed in a semiconductor substrate, the isolation regions are generally formed by adopting a shallow trench isolation process to form shallow trenches, and insulating materials are filled in the shallow trenches to form Shallow Trench Isolations (STI).
Because the shallow trench isolation is made of a different material than the semiconductor substrate and has a different thermal expansion coefficient, a certain stress is generated during the STI process. The stress may damage the structure of the semiconductor substrate, for example, a defect or a crack may be formed in the active region, or the mobility of carriers in the channel of the device may be affected, and thus the performance of the device may be affected, and the yield of the semiconductor device may be affected.
The above information disclosed in this background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not constitute prior art that is already known to a person of ordinary skill in the art.
Disclosure of Invention
It is a primary objective of the claimed invention to provide a method for fabricating a semiconductor substrate, which can eliminate stress after forming an isolation structure, thereby preventing the semiconductor substrate from being damaged and improving the yield of the semiconductor substrate.
Another objective of the present invention is to provide a semiconductor device, which can eliminate the stress of the isolation structure on the semiconductor device, improve the performance of the semiconductor device, and improve the yield of the semiconductor device.
In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor substrate, comprising: forming an active region and an isolation trench on a semiconductor substrate; depositing an insulating oxide in the isolation trench and on the surface of the active region, wherein the insulating oxide in the isolation trench is an isolation structure, and the insulating oxide on the surface of the isolation structure and the surface of the active region is an isolation layer; removing the isolation layer to enable the surface of the isolation structure to be flush with the surface of the active region; etching the active region to a preset depth to form an active groove; and epitaxially growing the semiconductor substrate in the active groove to enable the surface of the active region to be flush with the surface of the isolation structure.
According to an exemplary embodiment of the present invention, the predetermined depth is 0.03 to 0.3 μm.
According to an exemplary embodiment of the present invention, the predetermined depth is 0.15 μm.
According to an exemplary embodiment of the present invention, the insulating oxide is silicon oxide or silicon oxynitride.
According to an exemplary embodiment of the present invention, the insulating oxide is deposited by at least one of atomic layer deposition, chemical vapor deposition, and spin coating.
According to an exemplary embodiment of the present invention, the thickness of the isolation layer is 8 to 15 nm.
According to an exemplary embodiment of the present invention, the process for removing the isolation layer is chemical mechanical polishing or wet etching.
According to an exemplary embodiment of the present invention, the epitaxial growth is performed by molecular beam epitaxy or ultra-high vacuum chemical vapor deposition.
According to an exemplary embodiment of the present invention, the semiconductor substrate is single crystal silicon, and the single crystal silicon is epitaxially grown in the active recesses.
According to an exemplary embodiment of the present invention, a process for etching the active region to the predetermined depth is wet etching or dry etching.
According to an exemplary embodiment of the present invention, the forming of the active region and the isolation trench on the semiconductor substrate includes: forming a photoresist mask on the semiconductor substrate; etching the semiconductor substrate by using the photoresist mask to form the isolation trench and the active region; and removing the photoresist mask positioned above the active region.
According to an exemplary embodiment of the invention, the method further comprises: and depositing an ion implantation barrier layer on the surface of the semiconductor substrate after epitaxial growth.
According to an exemplary embodiment of the present invention, the thickness of the ion implantation blocking layer is 8 to 12 nm.
According to an exemplary embodiment of the present invention, the material of the ion implantation blocking layer is silicon dioxide or silicon nitride.
According to another aspect of the present invention, there is provided a semiconductor device comprising a semiconductor substrate and a functional device located in the semiconductor substrate, wherein the semiconductor substrate is prepared by the method of any of the above embodiments.
According to the technical scheme, the invention has at least one of the following advantages and positive effects:
after the isolation structures are formed on the semiconductor substrate, the active regions between the isolation structures are etched to a preset depth to form active grooves, the stress of the isolation structures and the isolation grooves can be removed, and the semiconductor substrate is epitaxially grown in the active grooves to enable the epitaxially grown semiconductor substrate to adapt to the isolation structures, so that the stress can be eliminated or reduced to the maximum extent in the semiconductor substrate with the isolation structures, the active regions are prevented from being damaged by the stress to generate defects or cracks, the influence on the performance of the device and the like caused by the influence on the mobility of current carriers in the channels of the device is avoided, and the yield of the semiconductor device is improved.
Drawings
The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.
Fig. 1 is a flowchart illustrating a method of manufacturing a semiconductor substrate according to an exemplary embodiment of the present invention;
fig. 2 is a schematic diagram illustrating the formation of an active region and an isolation trench on a semiconductor substrate using photolithography according to an exemplary embodiment of the present invention;
fig. 3 is a schematic view illustrating the formation of an active region and an isolation trench after removing a photoresist according to an exemplary embodiment of the present invention;
FIG. 4 is a schematic illustration of the deposition of an insulating oxide on a semiconductor substrate in accordance with an exemplary embodiment of the present invention;
FIG. 5 is a schematic view of a semiconductor substrate with an isolation layer removed, in accordance with an exemplary embodiment of the present invention;
fig. 6 is a schematic view of a semiconductor substrate having an active recess formed therein according to an exemplary embodiment of the present invention;
fig. 7 is a schematic view illustrating an epitaxial growth of a semiconductor substrate in an edge groove according to an exemplary embodiment of the present invention;
fig. 8 is a schematic structural view of a semiconductor substrate on which an ion implantation blocking layer is formed according to an exemplary embodiment of the present invention;
fig. 9 is a one-dimensional stress distribution diagram of a channel surface of a semiconductor device according to an exemplary embodiment of the present invention.
Description of reference numerals:
1. a semiconductor substrate; 2. an active region; 3. isolating the trench; 4. an isolation structure; 5. an isolation layer; 6. an active groove; 7. a photoresist mask; 8. an ion implantation barrier layer; d. the depth is preset.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.
In the following description of various exemplary embodiments of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration various exemplary structures in which aspects of the disclosure may be practiced. It is to be understood that other specific arrangements of parts, structures, example devices, systems, and steps may be utilized, and structural and functional modifications may be made without departing from the scope of the present disclosure. Moreover, although the terms "over," "between," "within," and the like may be used in this specification to describe various example features and elements of the disclosure, these terms are used herein for convenience only, e.g., in accordance with the orientation of the examples in the figures. Nothing in this specification should be construed as requiring a specific three dimensional orientation of structures in order to fall within the scope of this disclosure. Furthermore, the terms "first," "second," and the like in the claims are used merely as labels, and are not numerical limitations of their objects.
The flow charts shown in the drawings are merely illustrative and do not necessarily include all of the contents and operations/steps, nor do they necessarily have to be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the actual execution sequence may be changed according to the actual situation.
In addition, in the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
The semiconductor substrate includes a semiconductor substrate 1, isolation structures 4 (shallow trench isolation STI) are generally formed on the semiconductor substrate 1, and active regions 2 are disposed between the isolation structures 4, that is, adjacent active regions 2 are insulatively separated by the isolation structures 4 (refer to fig. 5).
The shallow trench isolation is generally made of an insulating material such as silicon dioxide or silicon oxynitride, and the semiconductor substrate 1 for forming the shallow trench may be made of silicon, silicon carbide, silicon-on-insulator-germanium, or germanium-on-insulator. Before forming the isolation structure 4, an isolation trench 3 (shallow trench) is formed on the semiconductor substrate 1, and then an insulating material is deposited into the isolation trench 3 to form the isolation structure 4. However, since the material of the isolation structure 4 is different from the material of the semiconductor substrate 1, and the thermal expansion coefficient and the lattice constant of the isolation structure 4 are different from each other, a certain stress may exist between the isolation structure 4 and the isolation trench 3 during the deposition of the isolation structure 4.
The stresses can be divided into two types, namely tensile stresses and compressive stresses. In the manufacturing process of a semiconductor device, some functional devices may be formed in a semiconductor substrate, for example, an MOS (field effect transistor) device may be formed in the substrate, and a conductive channel may be formed between a source region and a drain region of the MOS device. For different types of MOS devices, the stress can affect the stress distribution on the surface of a conducting channel of the MOS device, and further can generate a bad effect on the performance of the semiconductor device, for example, for PMOS, the tensile stress can affect and reduce the mobility of hole carriers, and further reduce the on-state current of the device; for NMOS, the compressive stress affects and reduces the mobility of electron carriers, thereby reducing the on-state current of the device. Meanwhile, the stress may also affect the structure of the semiconductor substrate, and when the stress is large enough, cracks and deformation may occur in the active region 2 of the semiconductor substrate 1, which may eventually cause performance degradation of the semiconductor device and affect the yield of the semiconductor device. Therefore, in the design of integrated circuit structures, it is necessary to effectively remove the influence of the stress.
In order to effectively remove the stress, according to an aspect of the present invention, a method of manufacturing a semiconductor substrate is provided. As shown in fig. 1 to 8, wherein fig. 1 shows a flow chart of a method for manufacturing a semiconductor substrate of the present invention; fig. 2 to 8 are schematic cross-sectional views of a semiconductor substrate at respective steps of a method for manufacturing the semiconductor substrate. As shown in fig. 1, the method for manufacturing a semiconductor substrate of the present invention includes:
step S200: an active region 2 and an isolation trench 3 are formed on a semiconductor substrate 1.
Step S400: and depositing an insulating oxide in the isolation trench 3 and on the surface of the active region 2, wherein the insulating oxide in the isolation trench 3 is an isolation structure 4, and the insulating oxide on the surface of the isolation structure 4 and the surface of the active region 2 is an isolation layer 5.
Step S600: the isolation layer 5 is removed so that the surface of the isolation structure 4 is flush with the surface of the active region 2.
Step S800: the active region 2 is etched to a predetermined depth d to form an active recess 6.
Step S1000: the semiconductor substrate 1 is epitaxially grown in the active recesses 6 so that the surface of the active region 2 is flush with the surface of the isolation structure 4.
According to the preparation method of the semiconductor substrate, after the isolation structures 4 are formed, the active grooves 6 are formed by etching the active regions 2 between the isolation structures 4 to a preset depth d, the semiconductor substrate part affected by the stress between the isolation structures 4 and the isolation grooves 3 can be removed, and the semiconductor substrate 1 epitaxially grown in the active grooves 6 is further used for enabling the semiconductor substrate 1 epitaxially grown to adapt to the isolation structures 4, so that the stress can be eliminated or reduced to the maximum extent in the semiconductor substrate 1 with the isolation structures 4, defects or cracks caused by the fact that the active regions 2 are damaged by the stress are avoided, the electrical performance of devices is prevented from being affected by the stress, and the yield of semiconductor devices is improved.
The method for manufacturing the semiconductor substrate of the present invention will be described in detail below.
Step S200: an active region 2 and an isolation trench 3 are formed on a semiconductor substrate 1.
A semiconductor substrate 1 is provided, isolation trenches 3 are etched in the semiconductor substrate 1, and active regions 2 are formed in regions between the isolation trenches 3 in the semiconductor substrate 1.
As shown in fig. 2, forming an active region 2 and an isolation trench 3 on a semiconductor substrate 1 specifically includes: a photoresist mask 7 is formed on a semiconductor substrate 1, the semiconductor substrate 1 is etched by using the photoresist mask 7, after the etching is finished, an active region 2 is formed on the semiconductor substrate 1 at a part shielded by the photoresist mask 7, and an unshielded part is etched to be an isolation trench 3. Thereafter, as shown in fig. 3, the photoresist mask 7 located above the active region 2 is removed, and the semiconductor substrate 1 having the isolation trench 3 is formed.
Wherein, dry etching or wet etching process may be employed to etch the semiconductor substrate 1 to form the isolation trench 3. The dry etching can be plasma etching, the etching gas adopted by the plasma process can be chlorine, and the etching degree can be controlled by controlling the using amount of the etching gas. The wet etching can use concentrated sulfuric acid and hydrogen peroxide as an etchant, and the etching degree can be controlled by adjusting the concentration of the etchant, so that the depth of the isolation trench 3 is controlled. In some embodiments, the depth of the isolation trench 3 may be 0.2 to 0.3 μm, for example, 0.22 μm, 0.25 μm or 0.28 μm, and a person skilled in the art can control the etching degree according to practical situations, so as to control the depth of the isolation trench 3, which is not limited herein.
Step S400: and depositing an insulating oxide in the isolation trench 3 and on the surface of the active region 2, wherein the insulating oxide in the isolation trench 3 is an isolation structure 4, and the insulating oxide on the surface of the isolation structure 4 and the surface of the active region 2 is an isolation layer 5.
Wherein the insulating oxide may be silicon oxide (SiO)2) Or silicon oxynitride (SiON), the process of depositing the insulating oxide may be at least one of atomic layer deposition, chemical vapor deposition, and spin coating. In one embodiment, the deposition may be performed using both atomic layer deposition and spin-on processes to make the insulating oxide deposition more uniform.
As shown in fig. 4, the isolation structure 4 is a Shallow Trench Isolation (STI) located in the isolation trench 3, and in order to enable the isolation structure 4 to fill the isolation trench 3, the deposition is continued while depositing the insulating oxide to the top of the isolation trench 3, and an isolation layer 5 is formed on the top of the active region 2 and the isolation structure 4. The thickness of the isolation layer 5 may be 8 to 15nm, specifically, 10nm, 12nm or 13nm, and is not particularly limited herein.
Step S600: the isolation layer 5 is removed so that the surface of the isolation structure 4 is flush with the surface of the active region 2.
As shown in fig. 5, the isolation layer 5 is removed to expose the active region 2 and the isolation structure 4, and the semiconductor substrate 1 having the isolation structure 4 is formed. The process for removing the isolation layer 5 may be Chemical Mechanical Polishing (CMP) or wet etching. When chemical mechanical polishing is used, the semiconductor substrate 1 can be used as a stop layer, and in one embodiment, the semiconductor substrate 1 is silicon and the silicon is used as a stop layer, so that the polishing can be controlled to stop in time and a smooth surface can be formed in the active region 2. When wet etching is used, the etching solution can be mixed in a ratio to adjust the selectivity of the semiconductor substrate 1 to the isolation structure 4, and the isolation layer 5 can be removed by etching.
Step S800: the active region 2 is etched to a predetermined depth d to form an active recess 6.
As shown in fig. 6, after the isolation layer 5 is removed from the semiconductor substrate 1, the active region 2 is etched. The etching process can adopt wet etching or dry etching. The etching gas used in the dry etching can be chlorine, and the etching degree can be controlled by controlling the dosage and concentration of the etching gas. The wet etching can use concentrated sulfuric acid and hydrogen peroxide as an etchant, and the etchant has a very high selectivity ratio to the semiconductor substrate 1 by controlling the proportion and concentration of the etchant, for example, if the semiconductor substrate 1 uses silicon, the etchant can be adjusted to have a high selectivity ratio to the silicon, and further, the active region 2 can be etched quickly during etching.
As shown in FIG. 6, the predetermined depth d is the depth of the active groove 6, and the predetermined depth d may be 0.03 μm to 0.3 μm, for example, 0.05 μm, 0.1 μm, 0.15 μm, 0.2 μm, 0.25 μm. In one embodiment, the predetermined depth d is preferably 0.15 μm. The value of the predetermined depth d may be set according to the depth of the isolation trench 3 and the stress condition, for example, if the stress is mainly present on the bottom of the isolation trench 3 and the depth of the active groove 6 is smaller than the depth of the isolation trench 3, the depth of the active groove 6 formed by etching the active region 2 may be controlled to be the same as the depth of the isolation trench 3 if the stress is present on the bottom of the isolation trench 3 or the entire isolation trench 3. I.e. the predetermined depth d is not greater than the depth of the isolation trench 3.
Step S1000: the semiconductor substrate 1 is epitaxially grown in the active recesses 6 so that the surface of the active region 2 is flush with the surface of the isolation structure 4.
After the formation of the active recess 6 with the predetermined depth d, the stress of this part is relieved, as the material of the semiconductor substrate 1 has here been separated from the isolation structure 4, as shown in fig. 7. Then, the semiconductor substrate 1 is epitaxially grown in the active groove 6, and in the process of epitaxial growth, the material of the part of the semiconductor substrate 1 can adapt to the growth of the isolation structure 4, and no new stress is generated, so that no stress exists between the semiconductor substrate 1 and the isolation structure 4 formed after epitaxial growth or only a very small stress exists at a contact interface, thereby ensuring that the active region 2 is not damaged by the stress to generate defects or cracks, and simultaneously avoiding the generation of gaps between the isolation structure 4 and the isolation trench 3. In addition, the epitaxial growth process is controlled so that the surface of the active region 2 is flush with the surface of the isolation structure 4, and thus, the semiconductor substrate 1 having the isolation structure 4 is formed with stress being relieved.
The epitaxial growth process may be molecular beam epitaxy or ultrahigh vacuum chemical vapor deposition. In some embodiments, the material of the semiconductor substrate 1 may be selected to be monocrystalline silicon, and the monocrystalline silicon is epitaxially grown in the active groove 6, that is, homoepitaxial growth is adopted, so that uniformity of the semiconductor substrate 1 can be ensured, generation of new stress is avoided, and stability of the semiconductor substrate 1 is improved.
The specific parameters of the epitaxial growth process can be adjusted by those skilled in the art according to the actual situation, and are not described herein again.
In some embodiments, as shown in fig. 8, the method for manufacturing a semiconductor substrate according to an embodiment of the present invention further includes: an ion implantation barrier layer 8 is deposited on the surface of the semiconductor substrate 1 after epitaxial growth.
The ion implantation blocking layer 8 is an insulating dielectric layer to block ion implantation in a subsequent process. In some embodiments, the thickness of the ion implantation blocking layer 8 may be 8 to 12nm, for example, 9nm, 10nm or 11nm, and those skilled in the art can adjust the thickness according to the process conditions and the actual conditions, which is not limited herein. The material of the ion implantation barrier layer 8 can be silicon dioxide or silicon nitride, and the deposition process can adopt atomic layer deposition or chemical vapor deposition.
To sum up, according to the method for manufacturing a semiconductor substrate of the present invention, after the isolation structures 4 are formed in the semiconductor substrate 1, the active grooves 6 are formed by etching the active regions 2 between the isolation structures 4 to a predetermined depth d, so that the stress of the isolation structures 4 and the isolation trenches 3 can be removed, and further, the semiconductor substrate 1 epitaxially grown in the active grooves 6 is adapted to the isolation structures 4, so that the above stress can be eliminated or minimized in the semiconductor substrate 1 on which the isolation structures 4 are formed, thereby ensuring that the electrical performance of the device is not affected by the existence of the stress in the active regions 2, and simultaneously avoiding the generation of gaps between the isolation structures 4 and the isolation trenches 3, and improving the yield of the semiconductor device.
According to another aspect of the present invention, embodiments of the present invention provide a semiconductor device including a semiconductor substrate and a functional device, such as a MOS device, formed in the semiconductor substrate. The semiconductor substrate is prepared by the method described in any of the above embodiments, and is not described herein again.
As shown in fig. 9, which shows a one-dimensional stress distribution of the surface of a conductive channel at the bottom of a functional device in a semiconductor device, the abscissa in fig. 9 represents the distance from the center of the channel of the functional device formed on a semiconductor substrate to the left and right side isolation structures, the center of the channel is located at X of 0 μm, and the ordinate represents the stress value. As can be seen from fig. 9, in the semiconductor substrate manufactured by the method of the present invention, since the stress between the isolation structure and the semiconductor substrate is eliminated or greatly weakened, the stress on the surface of the channel of the semiconductor device finally formed on the substrate is greatly improved compared to the prior art, and the stress on the surface of the channel is greatly reduced, so that the stability of the semiconductor device according to the embodiment of the present invention is improved, and the yield of the product is greatly improved.
It is to be understood that the invention is not limited in its application to the details of construction and the arrangement of components set forth in the description. The invention is capable of other embodiments and of being practiced and carried out in various ways. The foregoing variations and modifications fall within the scope of the present invention. It will be understood that the invention disclosed and defined in this specification extends to all alternative combinations of two or more of the individual features mentioned or evident from the text and/or drawings. All of these different combinations constitute alternative aspects of the present invention. The embodiments described in this specification illustrate the best mode known for carrying out the invention and will enable those skilled in the art to utilize the invention.
Claims (15)
1. A method of fabricating a semiconductor substrate, comprising:
forming an active region and an isolation trench on a semiconductor substrate;
depositing an insulating oxide in the isolation trench and on the surface of the active region, wherein the insulating oxide in the isolation trench is an isolation structure, and the insulating oxide on the surface of the isolation structure and the surface of the active region is an isolation layer;
removing the isolation layer to enable the surface of the isolation structure to be flush with the surface of the active region;
etching the active region to a preset depth to form an active groove;
and epitaxially growing the semiconductor substrate in the active groove to enable the surface of the active region to be flush with the surface of the isolation structure.
2. The method of claim 1, wherein the predetermined depth is 0.03-0.3 μm.
3. The method of claim 2, wherein the predetermined depth is 0.15 μm.
4. The method of claim 1, wherein the insulating oxide is silicon oxide or silicon oxynitride.
5. The method of claim 1, wherein depositing the insulating oxide is performed by at least one of atomic layer deposition, chemical vapor deposition, and spin coating.
6. The method of claim 1, wherein the thickness of the isolation layer is 8 to 15 nm.
7. The method of claim 1, wherein the isolation layer is removed by a chemical mechanical polishing or wet etching process.
8. The method of claim 1, wherein the epitaxial growth is performed by molecular beam epitaxy or ultra-high vacuum chemical vapor deposition.
9. The method of claim 1 wherein the semiconductor substrate is monocrystalline silicon, the monocrystalline silicon being epitaxially grown in the active recesses.
10. The method of claim 1, wherein the active region is etched to the predetermined depth by a wet etching process or a dry etching process.
11. The method of claim 1, wherein forming an active region and an isolation trench on the semiconductor substrate comprises:
forming a photoresist mask on the semiconductor substrate;
etching the semiconductor substrate by using the photoresist mask to form the isolation trench and the active region;
and removing the photoresist mask positioned above the active region.
12. The method of claim 1, further comprising:
and depositing an ion implantation barrier layer on the surface of the semiconductor substrate after epitaxial growth.
13. The method of claim 12, wherein the thickness of the ion implantation blocking layer is 8-12 nm.
14. The method of claim 1, wherein the material of the ion implantation barrier layer is silicon dioxide or silicon nitride.
15. A semiconductor device, comprising: a semiconductor substrate and a functional device located in the semiconductor substrate, wherein the semiconductor substrate is prepared by the method of any one of claims 1 to 14.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116314005A (en) * | 2023-05-16 | 2023-06-23 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and preparation method thereof |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5851899A (en) * | 1996-08-08 | 1998-12-22 | Siemens Aktiengesellschaft | Gapfill and planarization process for shallow trench isolation |
| US6413836B1 (en) * | 2000-09-20 | 2002-07-02 | Vanguard International Semiconductor Corporation | Method of making isolation trench |
| US20060223277A1 (en) * | 2005-04-01 | 2006-10-05 | Hynix Semiconductor Inc. | Method of manufacturing a semiconductor memory device |
| US20090140330A1 (en) * | 2007-12-04 | 2009-06-04 | Rohm Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
| CN102456579A (en) * | 2010-10-27 | 2012-05-16 | 国际商业机器公司 | Semiconductor device having localized extremely thin silicon on insulator channel region |
| US20130119405A1 (en) * | 2011-11-14 | 2013-05-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with enhanced strain |
| CN103594412A (en) * | 2012-08-13 | 2014-02-19 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of shallow trench isolation structure and shallow trench isolation structure |
| CN110970346A (en) * | 2018-09-29 | 2020-04-07 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method |
-
2021
- 2021-07-05 CN CN202110757022.2A patent/CN113471138B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5851899A (en) * | 1996-08-08 | 1998-12-22 | Siemens Aktiengesellschaft | Gapfill and planarization process for shallow trench isolation |
| US6413836B1 (en) * | 2000-09-20 | 2002-07-02 | Vanguard International Semiconductor Corporation | Method of making isolation trench |
| US20060223277A1 (en) * | 2005-04-01 | 2006-10-05 | Hynix Semiconductor Inc. | Method of manufacturing a semiconductor memory device |
| US20090140330A1 (en) * | 2007-12-04 | 2009-06-04 | Rohm Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
| CN102456579A (en) * | 2010-10-27 | 2012-05-16 | 国际商业机器公司 | Semiconductor device having localized extremely thin silicon on insulator channel region |
| US20130119405A1 (en) * | 2011-11-14 | 2013-05-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with enhanced strain |
| CN103594412A (en) * | 2012-08-13 | 2014-02-19 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of shallow trench isolation structure and shallow trench isolation structure |
| CN110970346A (en) * | 2018-09-29 | 2020-04-07 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116314005A (en) * | 2023-05-16 | 2023-06-23 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and preparation method thereof |
| CN116314005B (en) * | 2023-05-16 | 2023-09-12 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and preparation method thereof |
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