CN116314005A - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
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- CN116314005A CN116314005A CN202310544767.XA CN202310544767A CN116314005A CN 116314005 A CN116314005 A CN 116314005A CN 202310544767 A CN202310544767 A CN 202310544767A CN 116314005 A CN116314005 A CN 116314005A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 239000000463 material Substances 0.000 claims abstract description 108
- 239000000758 substrate Substances 0.000 claims abstract description 94
- 238000002955 isolation Methods 0.000 claims abstract description 57
- 239000007789 gas Substances 0.000 claims description 53
- 238000005530 etching Methods 0.000 claims description 39
- 238000000034 method Methods 0.000 claims description 37
- 238000006243 chemical reaction Methods 0.000 claims description 35
- 239000001301 oxygen Substances 0.000 claims description 34
- 229910052760 oxygen Inorganic materials 0.000 claims description 34
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 33
- 238000000151 deposition Methods 0.000 claims description 33
- 230000008021 deposition Effects 0.000 claims description 30
- 238000010884 ion-beam technique Methods 0.000 claims description 14
- 238000005468 ion implantation Methods 0.000 claims description 13
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 claims description 12
- 238000002513 implantation Methods 0.000 claims description 12
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 11
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 11
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 claims description 10
- 229910000077 silane Inorganic materials 0.000 claims description 10
- 230000001133 acceleration Effects 0.000 claims description 6
- 230000035484 reaction time Effects 0.000 claims description 6
- 238000005137 deposition process Methods 0.000 claims description 5
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 4
- 229910000041 hydrogen chloride Inorganic materials 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 229920005591 polysilicon Polymers 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 9
- 150000002500 ions Chemical class 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- -1 oxygen ions Chemical class 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76267—Vertical isolation by silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
The invention provides a semiconductor structure and a preparation method thereof, comprising the following steps: a substrate; an oxide layer deposited on the surface of the substrate, wherein a plurality of active grooves are formed on the oxide layer; a plurality of isolation trenches formed in the substrate, the isolation trenches corresponding to the active trenches; and an active region material formed in the active trench and contiguous with the substrate, with complete isolation between adjacent active region materials; the area of the side surface of the active area material, which is close to the substrate, is represented as a first area, the area of the side surface of the active area material, which is far away from the substrate, is represented as a second area, and the first area is smaller than the second area. According to the semiconductor structure and the preparation method thereof disclosed by the invention, the situation of electric leakage of the active region material can be prevented.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof.
Background
The active region material refers to the region of the semiconductor chip where active devices are to be made. An active device is a device that must be properly operated with the application of an appropriate bias voltage. Since the active region materials of various devices are integrated on the same semiconductor chip, various parasitic effects exist between the active region materials of adjacent devices, and a leakage channel may be formed, resulting in leakage of the active region materials of the devices. Latch-up may occur in extreme cases, resulting in material failure of the active region of the device and even damage to the semiconductor chip in severe cases.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a semiconductor structure and a method for manufacturing the same, which can prevent leakage of active region materials.
To achieve the above and other related objects, the present invention provides a semiconductor structure comprising:
a substrate;
an oxide layer deposited on the surface of the substrate, wherein a plurality of active grooves are formed on the oxide layer;
a plurality of isolation trenches formed in the substrate, the isolation trenches corresponding to the active trenches; and
an active region material formed in the active slot and connected with the substrate, wherein adjacent active region materials are completely isolated;
the area of the side surface of the active area material, which is close to the substrate, is represented as a first area, the area of the side surface of the active area material, which is far away from the substrate, is represented as a second area, and the first area is smaller than the second area.
In an embodiment of the present invention, a section of the isolation groove in a vertical direction is concave.
In an embodiment of the present invention, a central axis of the active slot and a central axis of the corresponding isolation slot are located on the same line.
The invention also provides a preparation method of the semiconductor structure, which comprises the following steps:
obtaining a substrate;
performing deposition treatment on the surface of the substrate to deposit an oxide layer on the substrate;
etching the oxide layer to form a plurality of active grooves on the oxide layer;
performing self-aligned oxygen ion implantation reaction treatment on the substrate in the active groove to form a plurality of isolation grooves in the substrate, wherein the isolation grooves correspond to the active groove;
and carrying out epitaxial treatment on the active groove to form an active area material in the active groove, wherein the active area material is connected with the substrate, the area of the side surface of the active area material, which is close to the substrate, is expressed as a first area, the area of the side surface of the active area material, which is far away from the substrate, is expressed as a second area, and the first area is smaller than the second area.
In an embodiment of the present invention, a section of the isolation groove in a vertical direction is concave, and a central axis of the active groove and a central axis of the corresponding isolation groove are located on the same line.
In an embodiment of the present invention, in the step of performing a deposition process on the surface of the substrate to deposit an oxide layer on the substrate, a deposition gas includes oxygen and silane, a deposition condition includes a gas flow rate of the oxygen being in a range of 20sccm to 40sccm, a gas flow rate of the silane being in a range of 10sccm to 30sccm, a gas pressure being in a range of 90kpa to 110kpa, a reaction temperature being in a range of 400 ℃ to 800 ℃, and a reaction time being in a range of 10min to 30min.
In one embodiment of the present invention, the step of etching the oxide layer to form a plurality of active trenches on the oxide layer includes:
carrying out deposition treatment on the surface of the oxide layer so as to deposit a mask layer on the oxide layer;
etching the mask layer and the oxide layer to form a plurality of active grooves on the oxide layer;
and cleaning the mask layer to remove the rest mask layer on the surface of the oxide layer.
In an embodiment of the present invention, in the step of etching the mask layer and the oxide layer to form a plurality of active trenches on the oxide layer, the etching gas is carbon tetrafluoride, and the etching condition is that the gas flow of the carbon tetrafluoride is within a range of 100sccm to 500sccm, the gas pressure is within a range of 1 torr to 5 torr, and the input power is within a range of 200w to 500w.
In one embodiment of the invention, in the pair ofIn the step of forming a plurality of isolation grooves in the substrate, the substrate in the active groove is subjected to self-aligned oxygen ion implantation reaction treatment, wherein the implantation condition is represented by ion acceleration energy within 50 KeV-100 KeV, an included angle between an oxygen ion beam and a vertical direction is within a range of 10 degrees-20 degrees, and the implantation dosage of the oxygen ion beam is 5 x 10 15 cm -2 ~1*10 16 cm -2 Within a range of (2).
In an embodiment of the present invention, in the step of performing epitaxial treatment on the active tank to form an active region material in the active tank, epitaxial gases are dichlorosilane and hydrogen chloride, and an epitaxial condition is represented by that a gas flow rate of the dichlorosilane is in a range of 200sccm to 400sccm, a gas flow rate of the hydrogen chloride is in a range of 300sccm to 400sccm, a gas pressure is in a range of 10torr to 30torr, and a reaction temperature is in a range of 750 ℃ to 950 ℃.
As described above, the present invention provides a semiconductor structure and a method for fabricating the same, in which an active region material is optimized from a shape with a narrow upper portion to a shape with a narrow lower portion, and an unexpected effect is that the volume of the active region material can be reduced and the space between the upper and lower surfaces of two adjacent active region materials can be increased while maintaining the area of a single active region material on the surface of the semiconductor structure unchanged. Since the minimum isolation distance between adjacent active region materials is determined by the distance between the upper and lower surfaces of the active region materials, the device integration can be improved. The adjacent active region materials are completely isolated from each other by an insulating medium, so that leakage current between the active region materials can be eliminated, and isolation breakdown voltage is improved. Meanwhile, by arranging the isolation groove, a leakage channel can be further prevented from being formed between active region materials, and then the semiconductor structure can be protected.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a process for fabricating a semiconductor structure according to the present invention;
FIG. 2 is a flow chart of a method for fabricating a semiconductor structure according to the present invention;
fig. 3 is a flowchart of step S30 in fig. 2.
Description of element numbers:
10. a substrate; 20. an oxide layer; 30. a mask layer; 40. an active slot; 50. an isolation groove; 60. an active region material.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, a semiconductor chip is a semiconductor device that is fabricated by etching, wiring, and the like on a semiconductor sheet to perform a certain function. A larger amount of active area material 60 may be integrated on the semiconductor chip, and the desired functions may be further achieved by the cooperation between the active area materials 60. The semiconductor structure provided by the invention can integrate a plurality of active region materials 60 thereon, and the adjacent active region materials 60 can be completely isolated, so that parasitic effects between the adjacent active region materials 60 are avoided. During formation of active region material 60, substrate 10 may be first harvested and oxide layer 20 deposited on substrate 10 by chemical vapor deposition. After the deposition of the oxide layer 20 is completed, a mask layer 30 may be deposited on the surface of the oxide layer 20 for subsequent etching treatment. After the deposition of the mask layer 30 is completed, it may be subjected to an etching process to form the active trenches 40 on the oxide layer 20. After the active trenches 40 are formed, the remaining mask layer 30 on the surface of the oxide layer 20 may be removed to prevent the excessive mask layer 30 from affecting the subsequent process. After the mask layer 30 is removed, the substrate 10 is subjected to a self-aligned oxygen ion implantation reaction process so that a plurality of isolation trenches 50 are formed on the substrate 10, each of the active trenches 40 corresponding to one of the isolation trenches 50. After isolation trenches 50 are formed, active area material 60 may be grown in active trenches 40 by a selective epitaxial growth apparatus (Selective Epitaxial Growth, SEG) and the desired semiconductor structure may be obtained when all active area material 60 has been grown.
Referring to fig. 1, in one embodiment of the present invention, in depositing an oxide layer 20 on a substrate 10 by a chemical vapor deposition method, the oxide layer may be deposited by a chemical vapor deposition apparatus using a chemical vapor deposition method. The material of the oxide layer 20 is not limited, and in this embodiment, the material of the oxide layer 20 is exemplified by silicon oxide. During deposition, the substrate 10 may be placed in a reaction chamber of a chemical vapor deposition apparatus, and a deposition gas may be introduced into the reaction chamber and reacted under deposition conditions to complete the deposition of the oxide layer 20. Wherein the deposition gas may be oxygen O 2 And silane SiH 4 . The deposition conditions can be expressed as oxygen O 2 The gas flow rate of (2) is 20 sccm-40 sccm, and silane SiH 4 The gas flow is within the range of 10sccm to 30sccm, the gas pressure is within the range of 90kPa to 110kPa, the reaction temperature is within the range of 400 ℃ to 800 ℃, and the reaction time is within the range of 10min to 30min. For example, oxygen O 2 The gas flow rate of (2) may be 20sccm, 30sccm, or 40sccm. The flow rate of silane SiH4 may be 10sccm, 20sccm, or 30sccm. The air pressure may be 90kPa, 101kPa, or 110kPa. The reaction temperature may be 400 ℃, 600 ℃, or 800 ℃. The reaction time may be 10min, 20min or 30min. When the deposition condition is satisfied, an oxide layer 20 may be formed on the surface of the substrate 10 at this time.
Referring to fig. 1, in one embodiment of the present invention, after the deposition of the oxide layer 20 is completed, a mask layer 30 may be deposited on the surface of the oxide layer 20, where the substrate 10, the oxide layer 20, and the mask layer 30 may be sequentially arranged. The mask layer 30 may be Photoresist (Photoresist), which is a resist etching film material whose solubility is changed by irradiation or radiation of ultraviolet light, electron beam, ion beam, X-ray, etc. The photoresist is a light-sensitive mixed liquid composed of three main components of photosensitive resin, sensitizer and solvent.
Referring to fig. 1, in one embodiment of the present invention, during the formation of the active trenches 40 on the oxide layer 20, a plasma etching process may be performed by an etcher. During the etching process, the substrate 10 may be placed in a reaction chamber of an etcher, and an etching gas is introduced into the reaction chamber and reacts under etching conditions to complete the etching of the oxide layer 20, thereby forming a plurality of active trenches 40. Wherein the etching gas may be carbon tetrafluoride CF 4 . The etching conditions can be expressed as carbon tetrafluoride CF 4 The gas flow rate is within the range of 100sccm to 500sccm, the gas pressure is within the range of 1 to 5 Torr, and the input power is within the range of 200 to 500w. For example, the gas flow rate of the carbon tetrafluoride CF4 may be 100sccm, 300sccm, or 500sccm. The air pressure can be 1mtorr, 3mtorr or 5mtorr. The input power may be 200W, or 350W, or 500W.
Referring to fig. 1, in an embodiment of the present invention, in the process of removing the remaining mask layer 30 on the surface of the oxide layer 20, an etching machine may be used to etch the mask layer, or other methods may be used to clean the mask layer, so long as the removal of the remaining mask layer 30 is ensured.
Referring to fig. 1, in one embodiment of the present invention, in forming a plurality of isolation trenches 50 on a substrate 10, a self-aligned oxygen ion implantation reaction may be performed on the substrate 10 by an ion implanter to generate corresponding isolation trenches 50. During the self-aligned oxygen ion implantation reaction, the input parameters of the ion implanter may be adjusted to bring the reaction conditions to implantation conditions. The implantation condition may be expressed as that the ion acceleration energy is within 50 KeV-100 KeV, the angle between the oxygen ion beam and the vertical direction is within 10-20 DEG, and the implantation dose of the oxygen ion beam is 5 x 10 15 cm -2 ~1*10 16 cm -2 Within a range of (2). For example, the ion acceleration energy may be 50KeV, 75KeV, or 100KeV. The angle between the oxygen ion beam and the vertical direction can be 10 degrees, 15 degrees or 20 degrees. The implantation dose of the oxygen ion beam may be 5×10 15 cm -2 May also be 7.5 x 10 15 cm -2 May also be 1 x 10 16 cm -2 . In the oxygen ion implantation process, a mask is not needed, so that the self-aligned ion implantation is realized, the cost of one photomask can be saved, the process accuracy is improved, and oxygen ions are simultaneously implanted to the bottom surface and the side surface of the substrate, so that adjacent isolation grooves can be completely isolated.
Referring to fig. 1, in one embodiment of the present invention, active region material 60 may be grown by a selective epitaxial growth apparatus using an epitaxial process during the growth of active region material 60. The material of the active region material 60 may be, but not limited to, si, siGe, siC, etc. In this embodiment, the material of the active region material 60 is silicon Si. During epitaxy, epitaxial gases may be introduced into the reaction chamber of the selective epitaxial growth apparatus and reacted under epitaxial conditions to complete the growth of the active region material 60. Wherein the epitaxial gas may be dichlorosilane SiH 2 Cl 2 And hydrogen chloride HCl. The epitaxial conditions can be expressed as dichlorosilane SiH 2 Cl 2 The gas flow rate of the hydrogen chloride HCl is in the range of 200sccm to 400sccm, the gas flow rate of the hydrogen chloride HCl is in the range of 300sccm to 400sccm, the gas pressure is in the range of 10Torr to 30Torr, and the reaction temperature is in the range of 750 ℃ to 950 ℃. During the reaction of the epitaxial process, dichlorosilane SiH 2 Cl 2 Silicon Si is decomposed and formed, and single crystal silicon can be formed in the active trenches 40, and polycrystalline silicon can be formed on the oxide layer 20. The hydrogen chloride HCl etches silicon Si and the etch rate of polysilicon is higher than that of monocrystalline silicon. Therefore, the polysilicon on the oxide layer 20 is etched while being deposited, the etching rate of the polysilicon is the same as that of the polysilicon, and finally the polysilicon is not remained on the oxide layer 20. For single crystal silicon in the active trenches 40, due to the single crystal siliconThe etch rate of the single crystal silicon is lower than the deposition rate of the single crystal silicon, so that the single crystal silicon is continuously deposited and grown in the active trenches 40, and the corresponding active area material 60 is finally formed.
Referring now to fig. 1, in one embodiment of the present invention, a desired semiconductor structure may be created after formation of the corresponding active area material 60. The semiconductor structure may include a substrate 10, an oxide layer 20, a mask layer 30, an active trench 40, an isolation trench 50, and an active region material 60. Wherein an oxide layer 20 may be deposited on the substrate 10, and a plurality of active trenches 40 may be etched in the oxide layer 20. A corresponding isolation trench 50 may be provided on the substrate 10 on one side of the active trenches 40, and each active trench 40 may then correspond to a corresponding isolation trench 50. The shape of the active groove 40 is not limited, and may be a truncated cone shape, a quadrangular prism shape, or the like. Taking the shape of the active groove 40 as a quadrangular prism as an example, the active groove 40 may be in contact with the substrate 10, the area of the side of the active groove 40 close to the substrate 10 may be represented as a first area, the area of the side of the active groove 40 away from the substrate 10 may be represented as a second area, and the first area is smaller than the second area, that is, the section of the active groove 40 in the vertical direction is an inverted trapezoid, and the upper base of the inverted trapezoid is in contact with the substrate 10. The shape of the isolation trench 50 may be not limited, the cross section of the isolation trench 50 in the vertical direction is concave, and the length of the upper bottom edge of the cross section of the active trench 40 is smaller than the length of the cross section of the isolation trench 50 in the vertical direction. The central axis of the active trenches 40 and the central axis of the corresponding isolation trenches 50 may be on the same line, and the active area material 60 may be deposited in the active trenches 40, with the active area material 60 in contact with the substrate 10. The shape of the active region material 60 is the same as the active trenches 40, i.e. the area of the side of the active region material 60 close to the substrate 10 is smaller than the area of the side of the active region material 60 remote from the substrate 10.
It can be seen that in the above scheme, the active region material is optimized from the shape with the upper part being narrow and the lower part being wide to the shape with the upper part being wide and the lower part being narrow, the unexpected effect is that the volume of the active region material can be reduced and the interval between the upper bottom surfaces of two adjacent active region materials can be increased under the condition that the area of the single active region material on the surface of the semiconductor structure is kept unchanged. Since the minimum isolation distance between adjacent active region materials is determined by the distance between the upper and lower surfaces of the active region materials, the device integration can be improved. The adjacent active region materials are completely isolated from each other by an insulating medium, so that leakage current between the active region materials can be eliminated, and isolation breakdown voltage is improved. Meanwhile, by arranging the isolation groove, a leakage channel can be further prevented from being formed between active region materials, and then the semiconductor structure can be protected.
Referring to fig. 2, the present invention further provides a method for preparing a semiconductor structure, where the method may prepare the semiconductor structure, and the method may include the following steps:
s10, acquiring a substrate;
step S20, carrying out deposition treatment on the surface of the substrate to deposit an oxide layer on the substrate;
step S30, etching treatment is carried out on the oxide layer so as to form a plurality of active grooves on the oxide layer;
step S40, performing self-aligned oxygen ion implantation reaction treatment on the substrate in the active groove to form a plurality of isolation grooves in the substrate, wherein the isolation grooves correspond to the active groove;
and S50, carrying out epitaxial treatment on the active groove to carry out epitaxial treatment on the active area material in the active groove, wherein the tangent plane of the active area material in the vertical direction is in an inverted trapezoid shape, and the upper bottom edge of the inverted trapezoid is connected with the substrate.
Referring to fig. 2, in one embodiment of the present invention, when step S10 and step S20 are performed, a substrate is obtained, and a deposition process is performed on a surface of the substrate to deposit an oxide layer on the substrate. Specifically, in depositing the oxide layer 20 on the substrate 10 by the chemical vapor deposition method, it may be subjected to a deposition process by the chemical vapor deposition method by a chemical vapor deposition apparatus. The material of the oxide layer 20 is not limited, and in this embodiment, the material of the oxide layer 20 is exemplified by silicon oxide. During deposition, the substrate 10 may be placed in a reaction chamber of a chemical vapor deposition apparatus, and a deposition gas may be introduced into the reaction chamber and reacted under deposition conditions to complete the deposition of the oxide layer 20. Wherein the deposition gas may be oxygenGas O 2 And silane SiH 4 . The deposition conditions can be expressed as oxygen O 2 The gas flow rate of (2) is 20 sccm-40 sccm, and silane SiH 4 The gas flow is within the range of 10sccm to 30sccm, the gas pressure is within the range of 90kPa to 110kPa, the reaction temperature is within the range of 400 ℃ to 800 ℃, and the reaction time is within the range of 10min to 30min. For example, oxygen O 2 The gas flow rate of (2) may be 20sccm, 30sccm, or 40sccm. Silane SiH 4 The gas flow rate of (2) may be 10sccm, 20sccm, or 30sccm. The air pressure may be 90kPa, 101kPa, or 110kPa. The reaction temperature may be 400 ℃, 600 ℃, or 800 ℃. The reaction time may be 10min, 20min or 30min. When the deposition condition is satisfied, an oxide layer 20 may be formed on the surface of the substrate 10 at this time.
Referring to fig. 3, in one embodiment of the present invention, when step S30 is performed, an etching process is performed on the oxide layer to form a plurality of active trenches on the oxide layer. Specifically, step S30 may include the following steps:
step S31, carrying out deposition treatment on the surface of the oxide layer so as to deposit a mask layer on the oxide layer;
step S32, etching the mask layer and the oxide layer to form a plurality of active grooves on the oxide layer;
and step S33, cleaning the mask layer to remove the rest mask layer on the surface of the oxide layer.
Referring to fig. 3, in one embodiment of the present invention, when step S31 is performed, a deposition process is performed on the surface of the oxide layer to deposit a mask layer on the oxide layer. Specifically, after the deposition of the oxide layer 20 is completed, a mask layer 30 may be deposited on the surface of the oxide layer 20, and the substrate 10, the oxide layer 20, and the mask layer 30 may be sequentially arranged. The mask layer 30 may be Photoresist (Photoresist), which is a resist etching film material whose solubility is changed by irradiation or radiation of ultraviolet light, electron beam, ion beam, X-ray, etc. The photoresist is a light-sensitive mixed liquid composed of three main components of photosensitive resin, sensitizer and solvent.
Referring to fig. 3, in one embodiment of the present invention, when step S32 is performed, etching is performed on the mask layer and the oxide layer to form a plurality of active trenches on the oxide layer. Specifically, in the process of forming the active trenches 40 on the oxide layer 20, it may be etched by using a plasma etching method by an etcher. During the etching process, the substrate 10 may be placed in a reaction chamber of an etcher, and an etching gas is introduced into the reaction chamber and reacts under etching conditions to complete the etching of the oxide layer 20, thereby forming a plurality of active trenches 40. Wherein the etching gas may be carbon tetrafluoride CF 4 . The etching conditions can be expressed as carbon tetrafluoride CF 4 The gas flow rate is within the range of 100sccm to 500sccm, the gas pressure is within the range of 1 to 5 Torr, and the input power is within the range of 200 to 500w. For example, carbon tetrafluoride CF 4 The gas flow rate of (2) may be 100sccm, 300sccm, or 500sccm. The air pressure can be 1mtorr, 3mtorr or 5mtorr. The input power may be 200W, or 350W, or 500W.
Referring to fig. 3, in one embodiment of the present invention, when step S33 is performed, the mask layer is cleaned to remove the remaining mask layer on the surface of the oxide layer. Specifically, in the process of removing the residual mask layer 30 on the surface of the oxide layer 20, an etching machine may be used to etch the mask layer, or other manners may be used to clean the mask layer, so long as the removal of the residual mask layer 30 can be ensured.
Referring to fig. 2, in one embodiment of the present invention, when step S40 is performed, a self-aligned oxygen ion implantation reaction process is performed on the substrate in the active trench, so as to form a plurality of isolation trenches in the substrate, where the isolation trenches correspond to the active trenches. Specifically, in the process of forming the plurality of isolation trenches 50 on the substrate 10, the self-aligned oxygen ion implantation reaction may be performed on the substrate 10 by the ion implanter, thereby generating the corresponding isolation trenches 50. During the self-aligned oxygen ion implantation reaction, the input parameters of the ion implanter can be adjusted to achieve the reaction conditionsTo implantation conditions. The implantation condition may be expressed as that the ion acceleration energy is within 50 KeV-100 KeV, the angle between the oxygen ion beam and the vertical direction is within 10-20 DEG, and the implantation dose of the oxygen ion beam is 5 x 10 15 cm -2 ~1*10 16 cm -2 Within a range of (2). For example, the ion acceleration energy may be 50KeV, 75KeV, or 100KeV. The angle between the oxygen ion beam and the vertical direction can be 10 degrees, 15 degrees or 20 degrees. The implantation dose of the oxygen ion beam may be 5×10 15 cm -2 May also be 7.5 x 10 15 cm -2 May also be 1 x 10 16 cm -2 。
Referring to fig. 2, in one embodiment of the present invention, when step S50 is performed, an epitaxial process is performed on the active trench to expose an active region material in the active trench, wherein a vertical section of the active region material is an inverted trapezoid, and an upper base of the inverted trapezoid is connected to the substrate. Specifically, during the growth of the active region material 60, the active region material 60 may be grown by a selective epitaxial growth apparatus using an epitaxial process. The material of the active region material 60 may be, but not limited to, si, siGe, siC, etc. In this embodiment, the material of the active region material 60 is silicon Si. During epitaxy, epitaxial gases may be introduced into the reaction chamber of the selective epitaxial growth apparatus and reacted under epitaxial conditions to complete the growth of the active region material 60. Wherein the epitaxial gas may be dichlorosilane SiH 2 Cl 2 And hydrogen chloride HCl. The epitaxial conditions can be expressed as dichlorosilane SiH 2 Cl 2 The gas flow rate of the hydrogen chloride HCl is in the range of 200sccm to 400sccm, the gas flow rate of the hydrogen chloride HCl is in the range of 300sccm to 400sccm, the gas pressure is in the range of 10Torr to 30Torr, and the reaction temperature is in the range of 750 ℃ to 950 ℃. During the reaction of the epitaxial process, dichlorosilane SiH 2 Cl 2 Silicon Si is decomposed and formed, and single crystal silicon can be formed in the active trenches 40, and polycrystalline silicon can be formed on the oxide layer 20. The hydrogen chloride HCl etches silicon Si and the etch rate of polysilicon is higher than that of monocrystalline silicon. Thus for oxide layer 20, the polysilicon is etched while being deposited, the etching rate of the polysilicon is the same as that of the polysilicon, and the polysilicon is not remained on the final oxide layer 20. For the monocrystalline silicon in the active trenches 40, since the etching rate of the monocrystalline silicon is lower, the etching rate of the monocrystalline silicon is smaller than the deposition rate of the monocrystalline silicon, the monocrystalline silicon is continuously deposited and grown in the active trenches 40, and the corresponding active region material 60 is finally formed.
Referring now to fig. 1, in one embodiment of the present invention, a desired semiconductor structure may be created after formation of the corresponding active area material 60. The semiconductor structure may include a substrate 10, an oxide layer 20, a mask layer 30, an active trench 40, an isolation trench 50, and an active region material 60. Wherein an oxide layer 20 may be deposited on the substrate 10, and a plurality of active trenches 40 may be etched in the oxide layer 20. A corresponding isolation trench 50 may be provided on the substrate 10 on one side of the active trenches 40, and each active trench 40 may then correspond to a corresponding isolation trench 50. The shape of the active groove 40 is not limited, and may be a truncated cone shape, a quadrangular prism shape, or the like. Taking the shape of the active groove 40 as a quadrangular prism as an example, the active groove 40 may be in contact with the substrate 10, the area of the side of the active groove 40 close to the substrate 10 may be represented as a first area, the area of the side of the active groove 40 away from the substrate 10 may be represented as a second area, and the first area is smaller than the second area, that is, the section of the active groove 40 in the vertical direction is an inverted trapezoid, and the upper base of the inverted trapezoid is in contact with the substrate 10. The shape of the isolation trench 50 may be not limited, the cross section of the isolation trench 50 in the vertical direction is concave, and the length of the upper bottom edge of the cross section of the active trench 40 is smaller than the length of the cross section of the isolation trench 50 in the vertical direction. The central axis of the active trenches 40 and the central axis of the corresponding isolation trenches 50 may be on the same line, and the active area material 60 may be deposited in the active trenches 40, with the active area material 60 in contact with the substrate 10. The shape of the active region material 60 is the same as the active trenches 40, i.e. the area of the side of the active region material 60 close to the substrate 10 is smaller than the area of the side of the active region material 60 remote from the substrate 10.
In summary, by the method for manufacturing the semiconductor structure, the shape of the active region material is optimized from the shape with the upper part being narrow and the lower part being wide to the shape with the upper part being wide and the lower part being narrow, and the unexpected effect is that the volume of the active region material can be reduced and the interval between the upper bottom surfaces of two adjacent active region materials can be increased under the condition that the area of a single active region material on the surface of the semiconductor structure is kept unchanged. Since the minimum isolation distance between adjacent active region materials is determined by the distance between the upper and lower surfaces of the active region materials, the device integration can be improved. The adjacent active region materials are completely isolated from each other by an insulating medium, so that leakage current between the active region materials can be eliminated, and isolation breakdown voltage is improved. Meanwhile, by arranging the isolation groove, a leakage channel can be further prevented from being formed between active region materials, and then the semiconductor structure can be protected.
In the description of the present specification, the descriptions of the terms "present embodiment," "example," "specific example," and the like, mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The embodiments of the invention disclosed above are intended only to help illustrate the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (10)
1. A semiconductor structure, comprising:
a substrate;
an oxide layer deposited on the surface of the substrate, wherein a plurality of active grooves are formed on the oxide layer;
a plurality of isolation trenches formed in the substrate, the isolation trenches corresponding to the active trenches; and
an active region material formed in the active slot and connected with the substrate, wherein adjacent active region materials are completely isolated;
the area of the side surface of the active area material, which is close to the substrate, is represented as a first area, the area of the side surface of the active area material, which is far away from the substrate, is represented as a second area, and the first area is smaller than the second area.
2. The semiconductor structure of claim 1, wherein the isolation trench has a vertically cut surface that is concave.
3. The semiconductor structure of claim 1, wherein a central axis of the active trench is co-linear with a central axis of the corresponding isolation trench.
4. A method of fabricating a semiconductor structure, comprising:
obtaining a substrate;
performing deposition treatment on the surface of the substrate to deposit an oxide layer on the substrate;
etching the oxide layer to form a plurality of active grooves on the oxide layer;
performing self-aligned oxygen ion implantation reaction treatment on the substrate in the active groove to form a plurality of isolation grooves in the substrate, wherein the isolation grooves correspond to the active groove;
and carrying out epitaxial treatment on the active groove to form an active area material in the active groove, wherein the active area material is connected with the substrate, the area of the side surface of the active area material, which is close to the substrate, is expressed as a first area, the area of the side surface of the active area material, which is far away from the substrate, is expressed as a second area, the first area is smaller than the second area, and adjacent active area materials are completely isolated.
5. The method for manufacturing a semiconductor structure according to claim 4, wherein the cross section of the isolation groove in the vertical direction is concave, and the central axis of the active groove and the central axis of the corresponding isolation groove are located on the same straight line.
6. The method according to claim 4, wherein in the step of depositing an oxide layer on the substrate by performing a deposition process on the surface of the substrate, the deposition gas includes oxygen and silane, the deposition condition includes a gas flow rate of the oxygen being 20sccm to 40sccm, a gas flow rate of the silane being 10sccm to 30sccm, a gas pressure being 90kpa to 110kpa, a reaction temperature being 400 ℃ to 800 ℃, and a reaction time being 10min to 30min.
7. The method of claim 4, wherein the step of etching the oxide layer to form a plurality of active trenches on the oxide layer comprises:
carrying out deposition treatment on the surface of the oxide layer so as to deposit a mask layer on the oxide layer;
etching the mask layer and the oxide layer to form a plurality of active grooves on the oxide layer;
and cleaning the mask layer to remove the rest mask layer on the surface of the oxide layer.
8. The method of claim 7, wherein in the step of etching the mask layer and the oxide layer to form a plurality of active trenches on the oxide layer, the etching gas is carbon tetrafluoride, and the etching condition is represented by a gas flow rate of the carbon tetrafluoride in a range of 100sccm to 500sccm, a gas pressure in a range of 1 torr to 5 torr, and an input power in a range of 200w to 500w.
9. The method of claim 4, wherein in the step of forming a plurality of isolation trenches in the substrate by performing a self-aligned oxygen ion implantation reaction on the substrate in the active trench, the implantation condition is expressed as an ion acceleration energy in a range of 50kev to 100kev, an angle between an oxygen ion beam and a vertical direction is in a range of 10 ° to 20 °, and an implantation dose of the oxygen ion beam is 5 x 10 15 cm -2 ~1*10 16 cm -2 Within a range of (2).
10. The method according to claim 4, wherein in the step of performing epitaxial treatment on the active cell to form an active region material in the active cell, epitaxial gas is dichlorosilane and hydrogen chloride, and the epitaxial condition is that the flow rate of the dichlorosilane is in the range of 200sccm to 400sccm, the flow rate of the hydrogen chloride is in the range of 300sccm to 400sccm, the gas pressure is in the range of 10torr to 30torr, and the reaction temperature is in the range of 750 ℃ to 950 ℃.
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20060078854A (en) * | 2004-12-30 | 2006-07-05 | 동부일렉트로닉스 주식회사 | Isolation in semiconductor and manufacturing method therof |
| US20100258858A1 (en) * | 2009-04-10 | 2010-10-14 | Hynix Semiconductor Inc. | Method of fabricating semiconductor device |
| CN101908507A (en) * | 2009-06-05 | 2010-12-08 | 中芯国际集成电路制造(上海)有限公司 | Making method of NROM (Nonvolatile Read Only Memory) device |
| CN103390574A (en) * | 2012-05-11 | 2013-11-13 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for shallow trench isolation and manufacturing method for complementary metal-oxide-semiconductor transistor (CMOS) |
| US20140264567A1 (en) * | 2013-03-14 | 2014-09-18 | Fairchild Semiconductor Corporation | Direct-drain trench fet with source and drain isolation |
| CN104319256A (en) * | 2014-09-24 | 2015-01-28 | 上海华虹宏力半导体制造有限公司 | Isolation structure of narrow active region and manufacturing method thereof |
| US20190206904A1 (en) * | 2017-12-28 | 2019-07-04 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Thin film transistor and method of making the same, and array substrate |
| CN110120364A (en) * | 2018-02-07 | 2019-08-13 | 无锡华润上华科技有限公司 | The preparation method of fleet plough groove isolation structure |
| CN113471138A (en) * | 2021-07-05 | 2021-10-01 | 长鑫存储技术有限公司 | Preparation method of semiconductor substrate and semiconductor device |
| CN114121818A (en) * | 2021-11-15 | 2022-03-01 | 长鑫存储技术有限公司 | Semiconductor device and method of forming the same |
-
2023
- 2023-05-16 CN CN202310544767.XA patent/CN116314005B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20060078854A (en) * | 2004-12-30 | 2006-07-05 | 동부일렉트로닉스 주식회사 | Isolation in semiconductor and manufacturing method therof |
| US20100258858A1 (en) * | 2009-04-10 | 2010-10-14 | Hynix Semiconductor Inc. | Method of fabricating semiconductor device |
| CN101908507A (en) * | 2009-06-05 | 2010-12-08 | 中芯国际集成电路制造(上海)有限公司 | Making method of NROM (Nonvolatile Read Only Memory) device |
| CN103390574A (en) * | 2012-05-11 | 2013-11-13 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for shallow trench isolation and manufacturing method for complementary metal-oxide-semiconductor transistor (CMOS) |
| US20140264567A1 (en) * | 2013-03-14 | 2014-09-18 | Fairchild Semiconductor Corporation | Direct-drain trench fet with source and drain isolation |
| CN104319256A (en) * | 2014-09-24 | 2015-01-28 | 上海华虹宏力半导体制造有限公司 | Isolation structure of narrow active region and manufacturing method thereof |
| US20190206904A1 (en) * | 2017-12-28 | 2019-07-04 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Thin film transistor and method of making the same, and array substrate |
| CN110120364A (en) * | 2018-02-07 | 2019-08-13 | 无锡华润上华科技有限公司 | The preparation method of fleet plough groove isolation structure |
| CN113471138A (en) * | 2021-07-05 | 2021-10-01 | 长鑫存储技术有限公司 | Preparation method of semiconductor substrate and semiconductor device |
| CN114121818A (en) * | 2021-11-15 | 2022-03-01 | 长鑫存储技术有限公司 | Semiconductor device and method of forming the same |
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