CN110797335A - 异质集成芯片的***级封装结构 - Google Patents

异质集成芯片的***级封装结构 Download PDF

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CN110797335A
CN110797335A CN201911188487.XA CN201911188487A CN110797335A CN 110797335 A CN110797335 A CN 110797335A CN 201911188487 A CN201911188487 A CN 201911188487A CN 110797335 A CN110797335 A CN 110797335A
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chip
silicon
adapter plate
hole adapter
packaging
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朱文辉
史益典
刘振
石磊
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Changsha Anmuquan Intelligent Technology Co ltd
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Changsha Anmuquan Intelligent Technology Co Ltd
Central South University
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Abstract

本发明提供了一种异质集成芯片的***级封装结构，包括：封装基板；硅通孔转接板，所述硅通孔转接板上开设有多个硅通孔，所述硅通孔转接板的底部设置有与多个凸点，所述硅通孔转接板通过所述凸点固定安装在所述封装基板上，所述硅通孔转接板通过所述凸点与所述封装基板电连接；凸点芯片，所述凸点芯片的底部设置有多个小微凸点，所述凸点芯片通过所述小微凸点固定安装在所述硅通孔转接板上，所述凸点芯片通过所述小微凸点与所述硅通孔转接板电连接；本封装结构有效的提高功能的集成度，同时减小了芯片在PCB板上占用空间，同时统一封装不同芯片有利于节省加工工序，使得封装效率得到了提高。

Description

异质集成芯片的***级封装结构
技术领域
本发明涉及芯片封装技术，特别涉及一种异质集成芯片的***级封装结构。
背景技术
随着5G、人工智能(AI)、车用电子、物联网(IoT)、高效运算(HPC)等半导体新应用领域百花齐放，晶圆制造先进制程走向7、5、3nm，但随着摩尔定律逐渐逼近物理极限，让摩尔定律延寿的良方之一为先进封装技术，包括扇出型晶圆级封装(FOWLP)、2.5D/3D IC封装，更进一步进入能够异质集成的3D晶圆堆叠封装。因应异质集成需求的SiP封装模块势必有更大量能需求。
硅通孔技术(TSV)实现Die与Die间的垂直互连，通过在Si上打通孔进行芯片间的互连，无需引线键合，有效缩短互连线长度，减少信号传输延迟和损失，提高信号速度和带宽，降低功耗和封装体积，是实现多功能、高性能、高可靠性且更轻、更薄、更小的芯片***级封装。由于3D TSV封装工艺在设计、量产、测试及供应链等方面还不成熟，且工艺成本较高，目前业界采用介于2D和3D之前的2.5D连接层封装形式，通过在Die和基板间添加一层连接层，大幅度提高封装的输入输出(I/O)信号密度。
在2.5D封装上，台积电已经投产COWOS工艺数年，这种工艺能够提供优化的***效能(提升3到6倍)、更小的产品外观尺寸，并且明显改善芯片之间的传输带宽。因应人工智慧(AI)世代高效运算(HPC)芯片需求，台积电第五代COWOS封装制程也将于2020年问世。
在焊点尺寸逐渐向3-5μm的小尺寸下，异质芯片，包括不同功能、不同代次、不同封装形式等芯片的***级集成封装成为新兴半导体产业应用问题的有效解决途径。传统的集成形式不能将多种异质概念的芯片统一于同一封装体中，其往往通过PCB电路板实现不同功能或代次芯片的联合应用，这一途径对于封装体的空间占用及集成度的提高有明显的限制作用，并且容易在封装中出现寄生电容、电感等影响芯片性能发挥的诸多因素，不利于信号传输。台积电的COWOS封装技术成为2.5D封装的关键解决方式，然而其封装的芯片多为FC-BGA形式，不能够实现对于所有封装形式芯片的异质集成。
发明内容
本发明提供了一种异质集成芯片的***级封装结构，其目的是为了解决现有技术芯片集成程度不高、占用空间过大的问题。
为了达到上述目的，本发明的实施例提供了一种异质集成芯片的***级封装结构，包括：
封装基板；
硅通孔转接板，所述硅通孔转接板上开设有多个硅通孔，所述硅通孔转接板的底部设置有与多个凸点，所述硅通孔转接板通过所述凸点固定安装在所述封装基板上，所述硅通孔转接板通过所述凸点与所述封装基板电连接；
凸点芯片，所述凸点芯片的底部设置有多个小微凸点，所述凸点芯片通过所述小微凸点固定安装在所述硅通孔转接板上，所述凸点芯片通过所述小微凸点与所述硅通孔转接板电连接；
3D-IC芯片，所述3D-IC芯片通过微凸点和所述硅通孔以倒装焊接在所述硅通孔转接板上，所述3D-IC芯片通过所述微凸点和硅通孔与所述硅通孔转接板电连接。
其中，所述封装基板上设置有引线键合芯片，所述引线键合芯片的底部涂设有TIM材料，所述引线键合芯片通过所述TIM材料与所述封装基板粘接安装。
其中，所述引线键合芯片上设置有引线键合线，所述引线键合芯片通过所述引线键合线与所述封装基板电连接。
其中，所述封装基板上设置有倒装芯片，所述倒装芯片通过所述微凸点以倒装键合的形式安装在所述封装基板上，所述倒装芯片通过所述微凸点与所述封装基板电连接。
其中，所述封装基板上安装有无源器件，所述无源器件与所述封装基板电连接。
其中，所述封装基板底部设置有焊球，所述封装基板通过所述焊球安装在一PCB板上。
本发明的上述方案有如下的有益效果：
本发明的上述实施例所述的异质集成芯片的***级封装结构，利用所述凸点、硅通孔以及硅通孔转接板将将不同功能芯片、不同代次芯片、不同封装类型芯片、不同维度芯片实现统一封装，有效的提高功能的集成度，同时减小了芯片在PCB板上占用空间，同时统一封装不同芯片有利于节省加工工序，使得封装效率得到了提高。
附图说明
图1是本发明的异质集成芯片的***级封装结构的结构示意图。
【附图标记说明】
1-封装基板；2-硅通孔转接板；3-硅通孔；4-凸点；5-凸点芯片；6-小微凸点；7-3D-IC芯片；8-微凸点；9-引线键合芯片；10-TIM材料；11-引线键合线；12-倒装芯片；13-无源器件；14-焊球。
具体实施方式
为使本发明要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
本发明针对现有的各芯片集成程度不高、占用空间过大问题，提供了一种异质集成芯片的***级封装结构。
如图1所示，本发明的实施例提供了一种异质集成芯片的***级封装结构，包括：封装基板1；硅通孔转接板2，所述硅通孔转接板2上开设有多个硅通孔3，所述硅通孔转接板2的底部设置有与多个凸点4，所述硅通孔转接板2通过所述凸点4固定安装在所述封装基板1上，所述硅通孔转接板2通过所述凸点4与所述封装基板1电连接；凸点芯片5，所述凸点芯片5的底部设置有多个小微凸点6，所述凸点芯片5通过所述小微凸点6固定安装在所述硅通孔转接板2上，所述凸点芯片5通过所述小微凸点6与所述硅通孔转接板2电连接；3D-IC芯片7，所述3D-IC芯片7通过微凸点8和所述硅通孔3以倒装焊接在所述硅通孔转接板2上，所述3D-IC芯片7通过所述微凸点8和硅通孔3与所述硅通孔转接板2电连接。
本发明的上述实施例所述的异质集成芯片的***级封装结构，所述封装基板1用于承载各种芯片，并且所述封装基板1上设置有导电线路供每个芯片实现相互间的电连接；所述封装基板1上通过所述凸点4粘接安装有所述硅通孔转接板2，所述硅通孔转接板2上设置有多个所述硅通孔3，所述硅通孔3由所述硅通孔转接板2的上表面至下表面穿透设置，并且所述硅通孔3能够导电，因此利用所述小微凸点6以倒装焊的形式安装在所述硅通孔转接板2上的所述凸点芯片5能够通过所述小微凸点6和所述硅通孔3的导电性实现与所述硅通孔转接板2的电连接，同时所述凸点芯片5为更为先进的3-5μm的凸点芯片；所述3D-IC芯片7通过所述微凸点8和硅通孔3与所述硅通孔转接板2实现电气连接与机械连接；此部分可视为COWOS封装体，其区别在于，内部的所述3D-IC芯片7与代次更为先进的3-5μm的所述凸点芯片5共同封装到所述硅通孔转接板2上。
其中，所述封装基板1上设置有引线键合芯片9，所述引线键合芯片9的底部涂设有TIM材料10，所述引线键合芯片9通过所述TIM材料10与所述封装基板1粘接安装。
其中，所述引线键合芯片9上设置有引线键合线11，所述引线键合芯片9通过所述引线键合线11与所述封装基板1电连接。
本发明的上述实施例所述的异质集成芯片的***级封装结构，所述引线键合芯片9的底部通过所述TIM材料10粘接在所述封装基板1上，所述引线键合线11连接所述引线键合芯片9与所述封装基板1，使得所述引线键合芯片9能够与所述封装基板1进行电连接；同时所述引线键合芯片9的底部设置有所述TIM材料10，因此所述引线键合芯片9的底部具有较好的散热性能。
其中，所述封装基板上设置有倒装芯片12，所述倒装芯片12通过所述微凸点8以倒装键合的形式安装在所述封装基板1上，所述倒装芯片12通过所述微凸点8与所述封装基板1电连接。
本发明的上述实施例所述的异质集成芯片的***级封装结构，所述封装基板上还能够安装所述倒装芯片12，所述倒装芯片12即为较低代次芯片如MEMS、RF IC等类型芯片；所述倒装芯片12通过所述微凸点8与所述封装基板1电连接，因此所述倒装芯片12能够通过所述微凸点8和封装基板1与其他芯片进行互相间的电连接。
其中，所述封装基板1上安装有无源器件13，所述无源器件13与所述封装基板1电连接。
本发明的上述实施例所述的异质集成芯片的***级封装结构，所述封装基板上安装有所述无源器件13，因此所述封装基板上实现了各种不同元器件的有效集成，提升了功能的集成度。
其中，所述封装基板1底部设置有焊球14，所述封装基板1通过所述焊球14安装在一PCB板上。
本发明的上述实施例所述的异质集成芯片的***级封装结构，所述封装基板的底部通过所述焊球14与所述PCB板焊接固定，所述PCB板用于承载整个封装结构体。
本发明的上述实施例所述的异质集成芯片的***级封装结构，利用所述凸点4、微凸点8、小微凸点6、硅通孔3以及硅通孔转接板2将不同功能芯片、不同代次芯片、不同封装类型芯片和不同维度芯片实现统一封装，同时所述封装基板1上还安装有其他所述无源器件13，有效的提高功能的集成度，同时减小了芯片在PCB板上占用空间，同时统一封装不同芯片有利于节省加工工序，使得封装效率得到了提高。
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (6)

1.一种异质集成芯片的***级封装结构，其特征在于，包括：
封装基板；
硅通孔转接板，所述硅通孔转接板上开设有多个硅通孔，所述硅通孔转接板的底部设置有与多个凸点，所述硅通孔转接板通过所述凸点固定安装在所述封装基板上，所述硅通孔转接板通过所述凸点与所述封装基板电连接；
凸点芯片，所述凸点芯片的底部设置有多个小微凸点，所述凸点芯片通过所述小微凸点固定安装在所述硅通孔转接板上，所述凸点芯片通过所述小微凸点与所述硅通孔转接板电连接；
3D-IC芯片，所述3D-IC芯片通过微凸点和所述硅通孔以倒装焊接在所述硅通孔转接板上，所述3D-IC芯片通过所述微凸点和硅通孔与所述硅通孔转接板电连接。
2.根据权利要求1所述的异质集成芯片的***级封装结构，其特征在于，所述封装基板上设置有引线键合芯片，所述引线键合芯片的底部涂设有TIM材料，所述引线键合芯片通过所述TIM材料与所述封装基板粘接安装。
3.根据权利要求2所述的异质集成芯片的***级封装结构，其特征在于，所述引线键合芯片上设置有引线键合线，所述引线键合芯片通过所述引线键合线与所述封装基板电连接。
4.根据权利要求1所述的异质集成芯片的***级封装结构，其特征在于，所述封装基板上设置有倒装芯片，所述倒装芯片通过所述微凸点以倒装键合的形式安装在所述封装基板上，所述倒装芯片通过所述微凸点与所述封装基板电连接。
5.根据权利要求1所述的异质集成芯片的***级封装结构，其特征在于，所述封装基板上安装有无源器件，所述无源器件与所述封装基板电连接。
6.根据权利要求1所述的异质集成芯片的***级封装结构，其特征在于，所述封装基板底部设置有焊球，所述封装基板通过所述焊球安装在一PCB板上。
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