CN113435149B - Test case automatic generation method for optimizing FPGA comprehensive effect - Google Patents

Test case automatic generation method for optimizing FPGA comprehensive effect Download PDF

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CN113435149B
CN113435149B CN202110714274.7A CN202110714274A CN113435149B CN 113435149 B CN113435149 B CN 113435149B CN 202110714274 A CN202110714274 A CN 202110714274A CN 113435149 B CN113435149 B CN 113435149B
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CN113435149A (en
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单悦尔
徐彦峰
范继聪
季振凯
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Wuxi Zhongwei Yixin Co Ltd
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    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
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    • G06—COMPUTING; CALCULATING OR COUNTING
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    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
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Abstract

The application discloses a test case automatic generation method for optimizing the comprehensive effect of an FPGA (field programmable gate array), which relates to the technical field of the FPGA.

Description

Test case automatic generation method for optimizing FPGA comprehensive effect
Technical Field
The application relates to the technical field of FPGA (field programmable gate array), in particular to an automatic test case generation method for optimizing the comprehensive effect of an FPGA.
Background
The FPGA design flow comprises synthesis, boxing, layout, wiring, code stream generation and the like, and the whole flow is an important index: delay, area, power consumption, turn-on rate and running time, wherein FPGA synthesis is an important ring in the FPGA design flow, and the main function of FPGA synthesis is to convert a circuit design described by HDL language into a logic netlist and optimize the logic netlist, which is an important ring in the FPGA flow, so that the circuit conversion aiming at the FPGA is realized on the general logic netlist. The FPGA synthesis mainly comprises four parts of analysis, RTL conversion, logic optimization and target mapping on hardware description languages such as Verilog. The most important part of FPGA synthesis is logic optimization, and the main function of the logic optimization is to decompose a circuit to enable the circuit to meet the requirement of K-input in the FPGA, and the method comprises the steps of deleting redundant nodes, deleting invalid nodes, decomposing nodes and the like.
Any gate-level netlist can be realized by using traditional Boolean logic (traditional Boolean, TB) based on AND/OR/NOT, most of the existing EDA tools are used for realizing logic optimization based on the TB logic, and the gate-level netlist realized by the TB logic is processed through multi-level logic optimization to obtain an optimal circuit meeting the target. The development of the driving software can be effectively driven by effective test in the development process of the FPGA design platform, the quality of the software is improved, and the effect of the software is optimized. Therefore, for the logic optimization process, if the corresponding test cases can be generated to test whether various strategies used for logic optimization in the FPGA synthesis reach the expected targets, the method is favorable for assisting in optimizing the FPGA synthesis effect, but no good implementation mode exists at present, and the FPGA tool has many characteristics, such as large and complex input data, so that a great deal of time, manpower and material resources are consumed for manually generating the test cases required for the logic optimization process, and a great deal of difficulty is brought to the test.
Disclosure of Invention
The inventor provides a test case automatic generation method for optimizing the comprehensive effect of an FPGA aiming at the problems and the technical requirements, and the technical scheme of the application is as follows:
a test case automatic generation method for optimizing FPGA comprehensive effect includes:
generating PI_cnt input variables and PO_cnt output variables, wherein PI_cnt is the number of input signals, and PO_cnt is the number of output signals;
selecting an N of an mth layer from a list of selectable variables of the mth layer m The candidate variable, m is a parameter and the initial value is 1, when m is more than or equal to 2, N of the m-th layer m The candidate variables at least comprise a logic expression generated in the m-1 layer, and the selectable variable list of the first layer is formed by PI_cnt input variables;
n based on selected mth layer m Generating an R of an mth layer based on Boolean logic according to a predetermined rule m The logic expression is R when m=LgLv_cnt LgLv_cnt =po_cnt, lglv_cnt is the number of logical layer stages;
if m is<LgLv_cnt, R of the mth layer m The optional variable list of the (m+1) -th layer is updated by adding the logic expression to the optional variable list of the (m) -th layer, and m=m+1 is made and the selection of the (N) -th layer from the optional variable list of the (m) -th layer is performed again m A step of candidate variables;
if m=lglv_cnt, then R will be m The logic expressions are correspondingly output to the PO_cnt output variables, and a combinational logic block containing logic expressions of the LgLv_cnt level logic level is generated;
and constructing the test case based on the generated combinational logic block.
The beneficial technical effects of the application are as follows:
the application discloses a test case automatic generation method for optimizing the comprehensive effect of an FPGA, which can provide test cases with different area sizes and complexity degrees according to preset rules by controlling the number of input signals, the number of output signals and the number of logic layer grades, and the generated test cases can be used for testing whether various strategies used for logic optimization in the FPGA synthesis obtain expected results or not, and the optimal strategy is selected to optimize the circuit area according to the expected results so as to assist in the development of FPGA comprehensive tools, thereby assisting in optimizing the comprehensive effect of the FPGA.
The test cases generated by the method provided by the application can be pure combination logic test cases, and can also be provided with the Boolean space which can be optimized in different scales by injecting irrelevant items and redundant items which can be controlled in scale and are formed by the Boolean space which can be optimized, so that the purpose of testing Boolean optimization is achieved.
Drawings
FIG. 1 is a flow chart of a test case automatic generation method according to an embodiment of the present application.
FIG. 2 is a logical schematic of generating a logical expression of the mth layer in one embodiment of the application.
FIG. 3 is a flow chart of a method for automatically generating test cases according to another embodiment of the present application.
FIG. 4 is a schematic diagram of a test case according to an embodiment of the present application.
FIG. 5 is a comparison of the number of LUTs after the test cases are combined under algebraic optimization strategy in one test experiment.
Fig. 6 is a comparison of LUT numbers after different strategies are integrated in the same test case in different scale boolean spaces injected in another test experiment.
FIG. 7 is a comparison of LUT numbers for a larger area combinational logic test case of another test case after integration under different strategies.
Detailed Description
The following describes the embodiments of the present application further with reference to the drawings.
The application discloses a test case automatic generation method for optimizing the comprehensive effect of an FPGA, which can automatically generate test cases for testing whether various strategies used for logic optimization in the FPGA synthesis reach the expected targets, thereby assisting in optimizing the comprehensive effect of the FPGA. In the process of generating the test case, the more core part is to generate the combinational logic block, and the method of the application comprises the following steps, as shown in fig. 1:
step 1, generating pi_cnt input variables and po_cnt output variables, where pi_cnt is the number of input signals, po_cnt is the number of output signals, and pi_cnt and po_cnt are parameters that can be configured in a self-defined manner.
Step 2, selecting the N of the mth layer from the variable list VarList (m) of the mth layer m The candidate variables, m, are parameters and the starting value is 1, typically chosen randomly. Wherein when m=1, the first layer of the variable list is formed by pi_cnt input variables, i.e. in the first cycle pi_cnt input variables are all put into the first layer of the variable list VarList (1), from which N of the first layer is then selected 1 Candidate variables, thus N of the first layer 1 The candidate variables are all input variables.
When m is more than or equal to 2, the optional variable list VarList (m) of the m-th layer comprises PI_cnt input variables andincluding the logical expressions generated at the previous m-1 layer, from which N is then selected m Candidate variables, and N of the mth layer m The candidate variables include at least one logical expression generated at layer m-1, so that layer N m The candidate variables at least include the logic expressions generated by the previous one or more logic levels, and may further include input variables, which will be described later herein.
For any mth layer, the number N of candidate variables selected by the mth layer m Can be configured in a self-defined way, and the number N of candidate variables selected by each logic level m May be equal or different. But most basically, the number N of candidate variables of any mth layer m Not exceeding the total number of variables in the corresponding selectable variable list VarList (m), e.g. N for the case of m=1 1 PI_cnt is not more than, and for the case that m is not less than 2, the total number of the actual VarList (m) is determined.
In another embodiment, a parameter exprv_max (m) may be further configured for the mth layer, where the parameter exprv_max (m) defines the number of maximum variables performing logical and operation in the logical expression generated by the mth layer, and then the number N of candidate variables of the mth layer m Not exceeding the corresponding ExprV_max (m), i.e. N m And less than or equal to ExprV_max (m). The exprv_max (m) of different logic levels may be the same or different.
In another embodiment, the highest fanout_max of the configuration variables may be customized, where the variables include the input variables and the logic expressions generated by the respective logic levels, and the highest fanout_max of each variable may be the same or different. The number of fan-outs of a variable indicates the number of times a variable is used to generate a logical expression, which is the number of times it is actually used, i.e. if a variable is repeated multiple times in a logical hierarchy/in a logical expression, the number of fan-outs of the variable is also successively increased, and N of the mth layer is selected from the mth layer's list of selectable variables m And when the candidate variables are selected, any one candidate variable does not reach the corresponding highest fan-out number.
Step 3, based onN of the selected mth layer m Generating an R of an mth layer based on Boolean logic according to a predetermined rule m And logic expressions. Optionally, the boolean logic used includes at least a logical or operation and a logical and operation, and optionally also a logical not operation.
Number R of logical expressions of any mth layer m Can be configured in a customized manner or randomly generated, and particularly, R is arranged when m=LgLv_cnt LgLv_cnt The number of logic expressions of the last layer is equal to the number of output signals, the number of logic expressions of the other layers is not limited, the number of logic expressions of the other layers is equal, or the number of logic expressions of at least two layers is unequal.
Step 4, if m<LgLv_cnt, R of the mth layer m The optional variable list VarList (m) of the m-th layer is updated by adding the logic expression to the optional variable list VarList (m) of the m-th layer to obtain an optional variable list VarList (m+1) of the m+1-th layer, and m=m+1 is caused to be executed again, and the N of the m-th layer is selected from the optional variable list of the m-th layer m The step of candidate variables, i.e. returning to step 2, goes to the next cycle, so in the next cycle, N of layer m+1 m+1 The candidate variables include the m-th layer generated R m At least one of the logic expressions.
Step 5, if m=lglv_cnt, R will be m The logic expressions are correspondingly output to the PO_cnt output variables, and a combinational logic block containing logic expressions of the LgLv_cnt level logic hierarchy is generated.
And 6, constructing and obtaining the test case based on the generated combinational logic block.
To more clearly illustrate the method of the present application for loop generating logic expressions of the LgLv cnt level logic hierarchy, the present application uses the following embodiment to develop the loop process:
(1) Generating pi_cnt input variables and po_cnt output variables, initializing a parameter m=1 of a logic level, and putting all pi_cnt input variables into a selectable variable list VarList (1) of the first layer.
(2) Selecting N of mth layer from VarList (m) m Candidate variables.
(3) N based on selected mth layer m Generating an R of an mth layer based on Boolean logic according to a predetermined rule m The logical expression, i.e., m=1.
(4) When m is<LgLv_cnt will R m The variable list VarList (m) with the logic expression added to the mth layer is updated to obtain the variable list VarList (m+1) with the mth layer and the variable list VarList (m+1) with the logic expression added to the mth layer and the variable list VarList (m) with the logic expression added to the mth layer is updated to obtain the variable list VarList (m+1) with the mth layer and the variable list VarList (m) with the logic expression added to the mth layer<Step (5) is performed when lglv_cnt-1, and step (6) is performed when m=lglv_cnt-1. The cycle ends when m=lglv_cnt.
(5) Let m=m+1, increasing the selection condition "including the R generated by the mth layer when selecting the candidate variable m At least one of the logic expressions, and then re-executing (2) - (4), the logic expressions of each logic level of m=2-m=lglv_cnt-1 are circularly generated.
(6) Let m=m+1, increasing the selection condition "including the R generated by the mth layer when selecting the candidate variable m At least one of the "and" the number of generated logical expressions is po_cnt ", and then (2) to (4) are re-executed, cyclically generating a logical expression of m=lglv_cnt.
1. A method of generating a logical expression.
In the above-described process of generating a combinational logic block containing logic expressions of lglv_cnt level logic levels, it is necessary to generate corresponding R for any mth level m The manner of generating each logic expression of the mth layer may be the same or different, and there are various manners of performing Boolean logic synthesis on candidate variables in practice, so that the forms of the logic expressions formed are also different, and in one embodiment of the present application, each logic expression is a logic function in the form of an SOP (Sum of product form, boolean and) form, where the logic function in the form of an SOP is expressed by a plurality of logical and terms (called products) through a Boolean sum, and each logical and term is obtained by performing a logical and operation on a plurality of literals. A neutral is a candidate variable variaNormal or reverse phase of ble.
In one embodiment, the R logical expression of any mth layer is generated according to the same predetermined rule, 1.ltoreq.r.ltoreq.R m The generation method includes, please combine fig. 2:
1. n based on selected mth layer m Candidate variable generationEach logical AND term is obtained by performing logical AND operation on a plurality of candidate variables, and each candidate variable is in positive phase or in negative phase.
In the generation ofWhen logic AND terms are used, all N can be used m Only some candidate variables may be used. At least two logical AND terms exist in each logical expression and are obtained by carrying out logical AND operation on different candidate variables, or K logical AND terms are obtained by carrying out logical AND operation on the same candidate variables, wherein the different candidate variables comprise different numbers and/or types of the candidate variables. A specific method is as follows:
a. from N m Random selection among candidate variablesCandidate variables->k is a parameter and the start value is 1.
b. For the selectedThe k logical AND terms are generated by performing logical AND operation on the candidate variables, and each candidate variable is in positive phase or in negative phase.
c. If it isLet k=k+1 and execute steps a-c again to generate the k+1th logical and term.
d. If it isAll->Logic and terms.
For example, in one example, N m Included among the candidate variables are a, b, c, d,3. k=1, select from a, b, c, dThe candidate variables are a, b and form the first logical AND term ab. k=2, from a, b, c, d +.>The candidate variables are a, b and form a second logical AND term ab ', b' representing the inverse of variable b. k=3, select from a, b, c, dThe candidate variables are a, b, c and form a third logical AND term, abc. It follows that in this embodiment, the candidate variable d is not used to generate a logical AND term, the first logical AND term and the second logical AND term generated using the same number and type of two candidate variables, but the phases of the variables are different, the third logical AND term generated using a different number and type of candidate variables with the remaining two logical AND terms.
The number of logical AND terms contained in the mth logical expression of the mth layerCan be custom configured or randomly generated, and in one embodiment, can also be custom configuredSetting a parameter Expterm_max (m, r), wherein the parameter Expterm_max (m, r) defines the maximum variable number for performing logical OR operation in the mth logic expression of the mth layer, and then the number of logical AND items in the mth logic expression of the mth layer is equal to the maximum variable number>Not exceeding the corresponding Expderm_max (m, r), i.eWhen at least one parameter of m and r is different, the corresponding Expterm_max (m, r) may be the same or different.
2. For a pair ofThe logical AND terms are logically ORed to generate an mth logical expression of the mth layer. For example, in the above example, the generated three logical AND terms are logically or-ed, and the generated mth logical expression of the mth layer is thatWhere + represents a logical or operation, i.e. a Boolean sum.
Other respective logical expressions of the mth layer may then be generated in the same manner as described above. Alternatively, the m-th layer has at least two logical expressions containing different numbers of logical AND terms, or, all R m Each logic expression contains the same number of logical and terms. For example, in the above example, one logic expression includes three logical and terms, and another logic expression may be different from the one logic expression, and includes four logical and terms, and the number and types of logic variables used in different logic expressions may be the same or different.
In one embodiment, when m=lglv_cnt, it is also detected whether there is an unused input variable, which is an input variable that was not used in generating the logic expression of the lglv_cnt level logic hierarchy. If there is no unused input variable, R is m The logic expressions are correspondingly output to the PO_cnt output variables. If there are unused input variables, the unused input variables are added to the logical expression of the lglv_cnt layer, thereby ensuring that all input variables are used, as shown in fig. 3. The adding mode can be various, in one embodiment, a plurality of logical AND terms are generated by all unused input variables, each logical AND term is obtained by performing logical AND operation on the plurality of unused input variables, and each unused input variable is in positive phase or in negative phase. Logical AND terms generated by all unused input variables are added to any one or more logical expressions of the L-th layer.
2. The injection may be boolean optimized by boolean space.
There are three basic approaches to multi-level logic optimization, namely algebraic logic optimization (algebraic logic optimization), boolean logic optimization (boolean logic optimization), and decomposition of Boolean functions (boolean function decomposition), algebraic logic optimization refers to performing algebraic operations on logic expressions, including decomposition, extraction, factorization, permutation, and elimination, and boolean logic optimization and boolean function decomposition refer to processing related output-independent terms composed of boolean space to achieve the goal of simplifying logic expressions. The scholars propose algorithms for four aspects of multi-level logic optimization, respectively: factoring logic function (decomposition logic function), simplification of logic functions (simplified logic function), global phase assignment (global phase allocation) and timing optimization (timing optimization), there are also some derived various methods proposed based on these basic methods, such as network reconstruction, node minimization method, etc. The above methods are all important ways of logic optimization, and various ways can exist simultaneously or at various stages in the optimization process, and sometimes better effects can be achieved.
The method provided by the application can achieve the purpose of estimating the scale of the test case by controlling the number PI_cnt of the input signals, the number PO_cnt of the output signals and the number LgLv_cnt of the logic layers, can obviously compare algebraic optimization effects, and can better drive the optimization effects on algebraic optimization strategies. In the method provided by another embodiment, the boolean space which can be optimized by the boolean can be injected to achieve the purpose of testing the boolean optimization, and in this embodiment, the related content of the boolean space is first described as follows:
a min term is a logical and term that contains all the candidate variables that make up the corresponding logical expression, each candidate variable being present in either normal or inverted form in the logical and term. For example, for a logical expression having three candidate variables a, b, c:
F＝abc+abc′+ab′c+ab′c′+a′bc+a′bc′+a′b′c+a′b′c′
the above logical expression contains 8 logical and terms, which are the smallest terms. Assuming that the above logical expression is f=ab+ab 'c+ab' c '+a' bc+a 'bc' +a 'b' c+a 'b' c ', the logical and term ab is not a minimum term because it includes two minimum terms abc, abc'. The N Boolean variables define an N-dimensional Boolean Space (Boolean Space). The N-dimensional Boolean space has 2 N And a minimum term. If a logic expression contains 2 N And a min term, this logic function contains 100% of the N-dimensional boolean space. For example, f=abc+abc '+ab' c+ab 'c' +a 'bc+a' bc '+a' b 'c+a' b 'c' contains all 8 min terms in the three-dimensional boolean space, which is a logical expression containing 100% of the three-dimensional boolean space. The embodiment can be based on the principle, and the Boolean space which can be optimized by the Boolean type with controllable scale is injected, so that the purpose of testing the Boolean type optimization is achieved.
The method for testing the Boolean-type optimized combined logic block and the algebraic-type optimization mode can be regarded as that the method for testing the algebraic-type optimization mode is additionally added with a logic part for injecting Boolean optimization. As shown in fig. 3, in the embodiment of the execution method for generating the mth logical expression of any mth layer, if the mth logical expression of the mth layer does not contain a redundancy item, K is generated m r After each logical AND term, directly to K m r The logical AND terms are subjected to logical OR operation to generate an mth logical expression of the mth layer, namely, the test algebraic optimized logical expression is formed. If the mth logical expression of the mth layer contains redundancy, then based on the generated K m r The logical AND terms constitute at least one group of Boolean space optimized logical AND terms, and all the logical AND terms are subjected to logical OR operation to generate an mth logical expression of an mth layer, wherein the logical AND terms participating in the logical OR operation comprise both the constructed Boolean space optimized logical AND terms and the logical AND terms which are initially generated without parameter construction redundancy terms, namely purposefully create a combined logical expression of an output 'irrelevant term' or 'redundancy term' formed by Boolean space. That is, whether or not to inject the redundancy item that can be optimized in the boolean space is self-configurable, one or more logic levels may have the redundancy item that can be optimized in the boolean space injected into one or more logic expressions, and one or more logic levels may have the redundancy item that can be optimized in the boolean space injected into the entire combinational logic block.
Specifically, T input variables are selected for at least one logical and term, the selected T input variables are logically and operated with a corresponding logical and term according to a plurality of different normal phase and reverse phase combination modes, a group of logic and terms capable of being optimized in boolean space is constructed, and at least one input variable in the formed group of logic and terms capable of being optimized in boolean space has a normal phase form and a reverse phase form. Wherein the selected T input variables may be coincident with or completely different from the input variables contained in the logical AND term. Alternatively, the configuration parameter dim_max may be customized, where dim_max represents the maximum dimension of the injected boolean space, and when the boolean space is injected, the total number of boolean space variables, i.e. the sum of T selected each time, does not exceed dim_max.
Alternatively, a boolean space may be injected according to the above method, or the step of selecting T input variables for at least one logical and term may be re-performed to continue to cycle to generate a plurality of boolean spaces until a logical and term forming a b_cnt group of boolean space optimizations is constructed, where b_cnt is a custom configured parameter.
For example, the logical AND terms included in the first logical expression of the third layer generated according to the method provided in the first partial embodiment include abc, adF 1 2 、Wherein a, b, c, d is an input variable, F 1 2 A second logic expression representing the first level logic hierarchy generation,/->Representing the first logical expression generated by the second level of logical hierarchy. If no redundancy is included, the first logical expression directly generating the third layer can be noted +.>When redundancy items are to be included, the procedure is as follows:
for one of the logical AND termsSelecting corresponding T=2 input variables as e and f respectively, and combining the two input variables e and f with ∈according to a plurality of different normal-phase and reverse-phase combination modes>And performing logical AND operation to construct a group of logical AND terms capable of being optimized in Boolean space. For example, one way is to construct a set of Boolean space-optimized logical AND terms comprising +.>At this time, all logical AND terms include abc and adF 1 2 、/>If only one Boolean space needs to be generated, the first logical expression generating the third layer can be written as +.>As another example, a set of Boolean space-optimized logical AND terms formed by construction may includeAt this time, if only one Boolean space needs to be generated, the first logic expression for generating the third layer can be marked as +.>The loop may then continue to generate b_cnt boolean spaces. Therefore, a test case in which B_cnt are injected into the Boolean space which can be optimized, the maximum dimension of the injected Boolean space is not more than Dim_max can be generated, the Boolean optimization effect can be obviously compared, and the optimization effect on the Boolean optimization strategy can be better driven.
3. Other functions are added.
As shown in FIG. 4, a test case is formed to include two parts, an optional module and an optional module, wherein the optional module includes a module declaration module, a variable instantiation module and a module ending module. The module declaration module is mainly used for declaring a module name, and the format is as follows: "module moduleName". The variable instantiation module is mainly used for declaring input and output variables, and the format is as follows: "input A, B, C; output F1, F2; the specific format here depends on Verilog version, with some differences between 1995 and 2001 versions. The module end module is then only "endmodule".
The optional modules include a variable declaration module and a statement execution block, the variable declaration module serving to declare intermediate variables as the name implies. The sentence execution block is a main body of the entire generation method, and in the present application, mainly includes the combinational logic block formed by the above-described method. Therefore, when the test case is constructed based on the generated combination logic blocks, statement execution blocks are formed based on the combination logic blocks, then the statement execution blocks and variable declaration modules form optional modules, and finally the optional modules are combined to form the finished test case.
The pure combination logic block is mainly used for testing the Boolean type effect and algebraic type optimization effect, namely the area optimization effect, and of course, only using the pure area optimization can affect the performance, wherein a balance needs to be obtained between the area and the performance, the balance is determined by the optimization driven by the time sequence, and factors affecting the time sequence comprise logic levels and the number of fan-outs, and too high logic levels and too many fan-outs can greatly affect the time sequence effect. When the effect of time sequence driving needs to be tested, registers need to exist, therefore, in the method of an embodiment, registers are optionally added before the input and after the output of the generated combination logic block respectively, so that the combination logic block can be placed between the registers, the area optimization can be driven through time sequence, the balance is found, or the registers are added in the generated combination logic block, the output of the registers is used as boundary division, and the optimization is carried out, so that the test case can be close to the actual situation, and the test case added with time sequence logic can be constructed and obtained for testing of the time sequence driving optimization strategy.
In addition to adding sequential logic, optionally, when forming statement execution blocks based on the combinational logic blocks, the generated combinational logic blocks and other execution blocks form statement execution blocks, and the statement execution blocks form and build test cases, and the other execution blocks comprise at least one of predetermined statement blocks and other functional modules. Wherein the predetermined sentence blocks are determined according to Verilog grammar, such as common if/case sentence blocks and always sentence blocks. Other functional modules may add other additional functionality to the test case. Optionally, other functional modules include an arithmetic operation unit, and accordingly, a data bus structure needs to be added in the variable declaration module and the variable instantiation module, so that the test of the comprehensive and optimization strategy of the arithmetic unit can be provided.
To illustrate the effectiveness of the methods provided by the present application, comparisons are made through the following example data:
in order to test the effect of different algebraic optimization strategies, a first part of method is utilized to generate test cases without injecting pure combination logic blocks capable of optimizing Boolean space, then the test cases are used for synthesis under different strategies, the number of the LUTs after synthesis is compared, the algebraic optimization strategies are chosen according to the result, and a test set 1, which is called as set 1 for short, is created according to the result. The test results are shown in table 1 and fig. 5.
TABLE 1 number of LUTs after test cases are integrated under algebraic optimization strategy
Test case PI_cnt PO_cnt LgLv_cnt Strategy 1 Policy 2 Strategy 3
Set 1 test example 1 10 10 5 131 87 109
Set 1 test example 2 10 10 7 280 277 250
Set 1 test example 3 15 10 7 2627 1541 1575
Set 1 test example 4 15 15 7 2861 2185 1713
Set 1 test example 5 20 5 5 1338 566 548
Set 1 test example 6 20 10 5 2486 1339 1408
Set 1 test example 7 20 10 7 5527 3794 3678
Set 1 test example 8 20 15 5 1723 1608 1688
Set 1 test example 9 20 20 5 4579 2362 2597
Set 1 test case 10 20 20 7 6358 6152 6189
As can be seen from Table 1, as PI_cnt, PO_cnt, lgLv_cnt increase, the number of LUTs obtained by integrating the test cases increases, i.e. it is shown that the method of the present application can provide pure combinational logic test cases with different area sizes and complexity levels through controllable PI_cnt, PO_cnt, lgLv_cnt. Policy 1 in table 1 is the result of directly mapping the logic expression to a 6-LUT, and policy 2 adopts algebraic optimization policy, namely decomposition (decomposition) of the algebraic logic netlist and extraction (factorization) of the common expression. Policy 3 based on policy 2, algebraic network reconstruction (re-composition) and re-extraction of common expression (re-factorization) are added. Corresponding to table 1 is fig. 5, and it can be seen from fig. 5 that policy 2 and policy 3 significantly reduce the number of LUTs after synthesis relative to policy 1.
In order to test the effect of the Boolean optimization strategy, a combination logic test case is selected, different numbers of Boolean spaces which can be optimized are injected, the Boolean spaces are formed into different scales by different numbers of variables, and finally a new test case set 2, namely set 2, is generated. For example, test example 3 in table 2 is to inject 1 boolean space consisting of 9 variables into the test example, and test example 12 is to inject 6 boolean spaces into the test example, which total 41 variables. And integrating the test cases under different strategies, adding Boolean logic optimization to the selected strategy besides algebraic optimization, and finally comparing the number of integrated LUTs to find a better optimization strategy. The test results are shown in table 2 and fig. 6.
TABLE 2 number of LUTs after the same test case is injected into different scale Boolean spaces and synthesized under different strategies
Test case B_cnt Total number of boolean space variables Strategy 1 Policy 2 Strategy 3 Strategy 4
Set 2 test example 1 0 0 1021 823 595 474
Set 2 test example 2 1 3 1271 1291 637 615
Set 2 test example 3 1 9 1381 1314 695 603
Set 2 test example 4 2 7 1557 2083 621 648
Set 2 test example 5 2 12 1886 1992 728 703
Set 2 test example 6 3 13 6170 2595 1184 698
Set 2 test example 7 3 17 6900 2872 1054 673
Set 2 test example 8 4 10 7978 5856 1285 819
Set 2 test example 9 4 17 7986 5778 1442 664
Set 2 test case 10 5 17 10828 8375 2382 994
Set 2 test example 11 5 22 10848 8132 2462 924
Set 2 test case 12 6 41 15504 12135 3837 773
Strategy 1 and strategy 2 in table 2 are the same as those used in table 1. Besides algebraic optimization, the policies 3 and 4 are added with Boolean logic optimization policies. Policy 4 differs from policy 3 in that policy 4 enhances the search and identification of boolean spaces, enabling more efficient discovery and optimization of boolean spaces that may be optimized. Corresponding to table 2 is fig. 6, and as can be seen from fig. 6, the optimization effect of the policy 3 is obviously better than that of the policies 1 and 2, and the policy 4 can better identify boolean optimization and algebraic optimization, so that the optimization effect is better than that of the policy 3. As can be seen from fig. 6, as the number of the injected boolean spaces b_cnt increases, the number of variables constituting the boolean space increases, and more redundancy is generated, which is specifically reflected by that as the number of the injected boolean spaces increases and the number of LUTs constituting the boolean space variables increases, the number of LUTs after the synthesis of strategies 1, 2 and 3 also increases, and the curves in the graph are in an ascending trend, and correspondingly, the number of LUTs after the synthesis under strategy 4 basically tends to be stable. In this case, if there is no boolean optimization or boolean optimization is not good, the overall result will be greatly affected.
Based on the characteristic of large capacity of the FPGA, the test of a large-capacity test case is necessary, and algebraic optimization and Boolean optimization are simultaneously present to meet the better aim. According to the method, a group of test cases with larger capacity is generated, the PI_cnt is 30, the PO_cnt is 15, the LgLv_cnt is 7, pure combination logics with larger areas of different logics are randomly generated on the basis, various scale Boolean spaces which can be optimized are added, the group of test cases are synthesized under algebraic optimization and Boolean optimization combination optimization strategies, the number of the synthesized LUTs is compared, and a better combination optimization strategy can be selected, so that a test set 3, simply called set 3, is created. The test results are shown in table 3 and fig. 7.
TABLE 3 LUT number after combining larger area combinational logic test cases under different strategies
Test case B_cnt Total number of boolean space variables Strategy 1 Policy 2 Strategy 3 Strategy 4
Set 3 test example 1 1 3 18107 12355 3106 1387
Set 3 test example 2 1 9 17574 9486 4372 213
Set 3 test example 3 2 13 17905 12125 5483 1331
Set 3 test example 4 3 28 19507 9914 2918 396
Set 3 test example 5 5 24 13393 9622 1410 784
Set 3 test example 6 5 33 19631 9701 5057 720
Set 3 test example 7 6 40 15504 12135 3837 773
The strategy in table 3 is the same as that used in table 2. As can be seen from FIG. 7, the trend of the comprehensive results of the test cases of the four policy test sets 3 is similar to that of FIG. 6, that is, the optimization effect of the policy 3 is obviously better than that of the policies 1 and 2, and the optimization effect of the policy 4 is better than that of the policy 3, that is, the generated large-capacity test case can meet the purpose of verifying the optimization policy effect, and the quality of the optimization policy can be judged accordingly.
The table and the graph show that the optimization effect is continuously improved in the process of continuously adjusting the optimization strategy, which means that the method provided by the application can effectively test and judge the advantages and disadvantages of the optimization strategy in the development process of the FPGA comprehensive tool, can provide effective drive for the development of the logic optimization effect of the comprehensive tool, and helps to improve the quality of the FPGA design tool.

Claims (13)

1. The automatic test case generation method for optimizing the comprehensive effect of the FPGA is characterized by comprising the following steps of:
generating PI_cnt input variables and PO_cnt output variables, wherein PI_cnt is the number of input signals, and PO_cnt is the number of output signals;
selecting an N of an mth layer from a list of selectable variables of the mth layer m The candidate variable, m is a parameter and the initial value is 1, when m is more than or equal to 2, N of the m-th layer m The candidate variables at least comprise a logic expression generated in the m-1 layer, and the selectable variable list of the first layer is formed by PI_cnt input variables;
n based on selected mth layer m Generating an R of an mth layer based on Boolean logic according to a predetermined rule m The logic expression is R when m=LgLv_cnt LgLv_cnt =po_cnt, lglv_cnt is the number of logical layer stages;
if m is<LgLv_cnt, R of the mth layer m The optional variable list of the (m+1) -th layer is updated by adding the logic expression to the optional variable list of the (m) -th layer, and m=m+1 is made and the selection of the (N) -th layer from the optional variable list of the (m) -th layer is executed again m A step of candidate variables;
if m=lglv_cnt, then R will be m The logic expressions are correspondingly output to the PO_cnt output variables, and a combinational logic block containing logic expressions of the LgLv_cnt level logic level is generated;
and constructing and obtaining the test case based on the generated combinational logic block.
2. The method of claim 1, wherein the selected mth layer based N m Generating an R of an mth layer based on Boolean logic according to a predetermined rule m A logic expression including 1. Ltoreq.r.ltoreq.R when generating the mth logic expression of the mth layer m ：
Selection based firstN of m layers m Candidate variable generationEach logical AND term is obtained by performing logical AND operation on a plurality of candidate variables, and each candidate variable is in positive phase or in negative phase;
for a pair ofThe logical AND terms are logically ORed to generate an mth logical expression of the mth layer.
3. The method of claim 2, wherein the presence of at least two logical expressions at the mth layer comprises a different number of logical and entries, or, all R m Each logic expression contains the same number of logical and terms; at least two logical AND terms exist in each logical expression and are obtained by carrying out logical AND operation on different candidate variables, or K logical AND terms are obtained by carrying out logical AND operation on the same candidate variables.
4. The method of claim 1, wherein R is generated except for the lglv_cnt layer LgLv_cnt Except for the po_cnt logical expressions, the number of logical expressions of the remaining layers is equal, or the number of logical expressions of at least two layers is not equal.
5. The method according to claim 2, wherein the method further comprises:
if the mth logical expression of the mth layer does not contain redundancy items, generatingAfter the logical AND terms, directly corresponding to->The individual logical AND terms are logically OR-edCalculating and generating an mth logic expression of an mth layer;
if the mth logical expression of the mth layer contains redundancy, then based on the generatedThe logical AND terms construct at least one group of logical AND terms capable of being optimized in Boolean space, and all the logical AND terms are subjected to logical OR operation to generate an mth logical expression of the mth layer.
6. The method of claim 5, wherein the generating is based onThe logical AND terms construct at least one set of Boolean space-optimized logical AND terms, comprising:
t input variables are selected for at least one logical AND term, and the selected T input variables and a corresponding logical AND term are respectively subjected to logical AND operation according to a plurality of different normal phase and reverse phase combination modes, so that a group of logical AND terms capable of being optimized in Boolean space is formed.
7. The method of claim 6, wherein the method further comprises:
and re-executing the step of selecting T input variables for at least one logical AND term until the logical AND term forming the B_cnt group of Boolean space optimizations is constructed.
8. The method according to any one of claims 1-7, further comprising:
when m=lglv_cnt, detecting whether there is an unused input variable, which is an input variable that is unused in generating a logic expression of an lglv_cnt level logic hierarchy;
if there is no unused input variable, R is m The logic expressions are correspondingly output to the PO_cnt output variables;
if there is an unused input variable, the unused input variable is added to the logical expression of the lglv_cnt layer.
9. The method of claim 8, wherein adding unused input variables to the logical expression of layer L comprises:
generating a plurality of logical AND terms by all unused input variables, wherein each logical AND term is obtained by performing logical AND operation on the plurality of unused input variables, and each unused input variable is in positive phase or in negative phase;
logical AND terms generated by all unused input variables are added to any one or more logical expressions of the L-th layer.
10. The method according to any one of claims 1 to 7, wherein,
selecting an N of an mth layer from a list of selectable variables of the mth layer m And each candidate variable does not reach the corresponding highest fan-out number.
11. The method according to any one of claims 1-7, further comprising:
and adding registers before and after the input and output of the generated combination logic block respectively, or adding registers in the generated combination logic block, and constructing a test case added with sequential logic.
12. The method of any of claims 1-7, wherein the constructing the resulting test case based on the generated combinatorial logic block comprises:
and constructing statement execution blocks by the generated combination logic blocks and other execution blocks, wherein the statement execution blocks form and construct test cases, and the other execution blocks comprise at least one of predetermined statement blocks and other functional modules.
13. The method of claim 12, wherein the step of determining the position of the probe is performed,
the other functional modules include an arithmetic operation unit.
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CN105868114A (en) * 2016-03-31 2016-08-17 复旦大学 FPGA software system and all module testing system and method thereof

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