CN113435149A

CN113435149A - Test case automatic generation method for optimizing FPGA comprehensive effect

Info

Publication number: CN113435149A
Application number: CN202110714274.7A
Authority: CN
Inventors: 单悦尔; 徐彦峰; 范继聪; 季振凯
Original assignee: Wuxi Zhongwei Yixin Co Ltd
Current assignee: Wuxi Zhongwei Yixin Co Ltd
Priority date: 2021-06-25
Filing date: 2021-06-25
Publication date: 2021-09-24
Anticipated expiration: 2041-06-25
Also published as: CN113435149B

Abstract

The invention discloses a test case automatic generation method for optimizing FPGA comprehensive effect, relating to the FPGA technical field, the method forms a selectable variable list of the current layer by the input variables and the logic expressions generated by the previous layers, selecting candidate variables containing the logic expression generated by the previous layer from the candidate variables, generating the logic expression of the current layer based on Boolean logic according to a preset rule, sequentially circulating until generating the logic expressions of all logic levels to form a combinational logic block, and constructing to obtain a test case, the method can provide test cases with different area sizes and complexity degrees by controlling the number of input signals, the number of output signals and the number of logic levels, the generated test cases can be used for testing whether various strategies used for logic optimization in FPGA synthesis obtain expected results, and accordingly, the optimal strategy is selected to optimize the circuit area so as to assist the development of an FPGA synthesis tool and assist in optimizing the FPGA synthesis effect.

Description

Test case automatic generation method for optimizing FPGA comprehensive effect

Technical Field

The invention relates to the technical field of FPGA, in particular to an automatic test case generation method for optimizing the comprehensive effect of FPGA.

Background

The FPGA design flow comprises synthesis, boxing, layout, wiring, code stream generation and the like, and important indexes of the whole flow are as follows: the FPGA synthesis is an important ring in the FPGA design flow, the main function of the FPGA synthesis is to convert the circuit design described by the HDL language into a logic netlist and optimize the logic netlist, and the circuit synthesis is an important ring in the FPGA flow, so that the circuit conversion aiming at the FPGA is realized for the general logic netlist. The FPGA synthesis mainly comprises four parts of analyzing a hardware description language such as Verilog, RTL conversion, logic optimization and target mapping. The most important part of FPGA synthesis is logic optimization, the main function of the logic optimization is to decompose a circuit, so that the circuit meets the requirement of k-input inside the FPGA, the steps of redundant node deletion, invalid node deletion, node decomposition and the like are included, and the aim is to balance the area, the time sequence and the power consumption according to the actual requirement on the premise of keeping the circuit function unchanged.

Any gate-level netlist can be realized by using and/or non-based traditional Boolean logic (TB), most of existing EDA tools realize logic optimization based on TB logic, and the gate-level netlist realized by the TB logic is processed by multi-level logic optimization to obtain an optimal circuit meeting the target. The effective test is carried out in the development process of the FPGA design platform, so that the software development can be effectively driven, the software quality is improved, and the software effect is optimized. Therefore, for the logic optimization process, it is necessary to generate corresponding test cases to test whether various strategies used for logic optimization in FPGA synthesis achieve the expected targets, which is beneficial to assisting in optimizing the FPGA synthesis effect, but there is no good implementation manner at present, and the FPGA tool has many characteristics, such as large and complex input data, so that the test cases required for manually generating the logic optimization process will consume a lot of time, manpower and material resources, which brings many difficulties to the test.

Disclosure of Invention

The invention provides an automatic test case generation method for optimizing FPGA comprehensive effect aiming at the problems and technical requirements, and the technical scheme of the invention is as follows:

a test case automatic generation method for optimizing FPGA comprehensive effect comprises the following steps:

generating PI _ cnt input variables and PO _ cnt output variables, wherein PI _ cnt is the number of input signals, and PO _ cnt is the number of output signals;

selecting N of mth layer from selectable variable list of mth layer_mA candidate variable, m is a parameter and the initial value is 1, when m is more than or equal to 2, the N of the mth layer_mThe candidate variables at least comprise a logic expression generated by the m-1 level, and the selectable variable list of the first level is formed by PI _ cnt input variables;

n based on selected mth layer_mGenerating R of mth layer based on Boolean logic according to predetermined rule by using candidate variables_mA logic expression, when m is LgLv _ cnt, R is_{LgLv_cnt}PO _ cnt, LgLv _ cnt is a logical layer progression;

if m<LgLv _ cnt, then R of the m-th layer_mAdding the logic expression into the optional variable list of the mth layer, updating to obtain an optional variable list of the (m +1) th layer, enabling m to be m +1, and selecting the N of the mth layer from the optional variable list of the mth layer again_mA step of selecting a candidate variable;

if m is LgLv _ cnt, then R is added_mThe logic expressions are correspondingly output to PO _ cnt output variables, and a combinational logic block containing logic expressions of LgLv _ cnt level logic hierarchy is generated;

and constructing a test case based on the generated combinational logic block.

The beneficial technical effects of the invention are as follows:

the method can provide test cases with different areas and complexity degrees according to a preset rule by controlling the number of input signals, the number of output signals and the logic layer number, and the generated test cases can be used for testing whether various strategies used for logic optimization in FPGA synthesis obtain expected results or not, so that the area of an optimal strategy optimization circuit is selected accordingly to assist the development of an FPGA synthesis tool, and the FPGA synthesis effect is assisted to be optimized.

The test cases generated by the method provided by the application can be pure combinational logic test cases, and test cases with Boolean spaces with different scales and capable of being optimized can be provided by injecting irrelevant items and redundant items with controllable scales and composed of Boolean spaces capable of being optimized, so that the purpose of testing Boolean type optimization is achieved.

Drawings

Fig. 1 is a flowchart of an automatic test case generation method according to an embodiment of the present application.

FIG. 2 is a logic diagram of generating a logic expression for layer m in one embodiment of the present application.

Fig. 3 is a flowchart of an automatic test case generation method according to another embodiment of the present application.

Fig. 4 is a schematic diagram of the structure of a test example in one embodiment of the present application.

FIG. 5 is a comparison of the number of LUTs of test cases synthesized under an algebraic optimization strategy in a test experiment.

Fig. 6 is a comparison of the number of LUTs synthesized under different strategies in the same test case injected into different scale boolean spaces in another test experiment.

FIG. 7 is a comparison of the LUT numbers of the larger area combinational logic test cases synthesized under different strategies in another test example.

Detailed Description

The following further describes the embodiments of the present invention with reference to the drawings.

The application discloses a test case automatic generation method for optimizing FPGA comprehensive effect, which can automatically generate a test case for testing whether various strategies used by logic optimization in FPGA synthesis reach the expected target or not, thereby assisting in optimizing the FPGA comprehensive effect. In the process of generating the test case, the core part is to generate the combinational logic block, and the method of the present application includes the following steps, as shown in fig. 1:

step 1, generating PI _ cnt input variables and PO _ cnt output variables, wherein PI _ cnt is the number of input signals, PO _ cnt is the number of output signals, and PI _ cnt and PO _ cnt are parameters which can be configured in a self-defined mode.

Step 2, selecting N of mth layer from optional variable list VarList (m) of mth layer_mThe candidate variables, m being a parameter and starting with a value of 1, are typically chosen randomly. When m is 1, the variable list of the first layer is formed by PI _ cnt input variables, that is, in the first loop, the PI _ cnt input variables are all put into the variable list VarList (1) of the first layer, and then N of the first layer is selected from the variable list VarList (1)₁A candidate variable, thus N of the first layer₁Each candidate variable is an input variable.

When m is more than or equal to 2, the optional variable list VarList (m) of the m-th layer comprises the logic expressions generated by the previous m-1 layer in addition to the PI _ cnt input variables, and then N is selected from the logic expressions_mA candidate variable, and N of the mth layer_mThe candidate variables include at least one logical expression generated at level m-1, so that N at level m_mThe candidate variables at least include the logic expression generated by the previous one-stage or multi-stage logic hierarchy, and may also include input variables, which will be introduced later in this application and will not be described herein.

For any mth layer, the number N of candidate variables selected by the mth layer_mThe number N of candidate variables selected by each logic level can be configured in a self-defining way_mMay or may not be equal. But most basically, the number N of candidate variables of any mth layer_mNot exceeding the total number of variables in the corresponding list of selectable variables varlist (m), e.g. N for m ═ 1₁Less than or equal to PI _ cnt, and for the case that m is more than or equal to 2, the total number of the actual VarList (m) is determined.

In another embodiment, a parameter ExprV _ max (m) may be further configured for the mth layer, where the parameter ExprV _ max (m) defines a maximum variable for performing a logical and operation in a logical expression generated by the mth layerThe number of (2) is the number N of candidate variables of the mth layer_mNot exceeding the corresponding ExprV _ max (m), i.e. N_mExprV _ max (m) or less. ExprV _ max (m) may be the same or different for different logical levels.

In another embodiment, the highest fan-out number Fanout _ max of configuration variables can be customized, the variables include input variables and logic expressions generated by various logic levels, and the highest fan-out number Fanout _ max of each variable can be the same or different. The fan-out number of a variable represents the number of times a variable is used to generate a logic expression, which is the number of times of actual use, i.e. if a variable is repeatedly used in a logic hierarchy/in a logic expression, the fan-out number of the variable is gradually increased, and N of the mth layer is selected from the selectable variable list of the mth layer_mAnd when the candidate variables are multiple, any one candidate variable does not reach the corresponding highest fan-out number.

Step 3, based on the selected N of the mth layer_mGenerating R of mth layer based on Boolean logic according to predetermined rule by using candidate variables_mAnd (4) logic expressions. Optionally, the boolean logic used at least includes a logical or operation and a logical and operation, and optionally also includes a logical not operation.

Number R of logical expressions of arbitrary mth layer_mCan be custom configured or randomly generated, particularly when m ═ LgLv _ cnt, with R_{LgLv_cnt}The number of logic expressions in the last layer is equal to the number of output signals, the number of logic expressions in the other layers is not limited, the number of logic expressions in the other layers is equal, or the number of logic expressions in at least two layers is not equal.

Step 4, if m<LgLv _ cnt, then R of the m-th layer_mAdding a logic expression to the optional variable list VarList (m) of the mth layer, updating to obtain an optional variable list VarList (m +1) of the (m +1) th layer, making m equal to m +1, and executing the step of selecting N of the mth layer from the optional variable list of the mth layer again_mA candidate changeQuantitative step, i.e. back to step 2 into the next cycle, so that in the next cycle, N of the m +1 th layer_m+1The candidate variables include R generated at the m-th layer_mAt least one of the logical expressions.

And 5, if m is equal to LgLv _ cnt, R is added_mAnd correspondingly outputting the logic expressions to PO _ cnt output variables to generate a combinational logic block containing logic expressions of LgLv _ cnt level logic hierarchy.

And 6, constructing a test case based on the generated combinational logic block.

In order to more clearly illustrate the method for generating logic expressions of logic levels of the LgLv _ cnt level in a loop, the following embodiment is adopted by the application to describe the loop process:

(1) and generating PI _ cnt input variables and PO _ cnt output variables, initializing a parameter m of a logic level to be 1, and putting all the PI _ cnt input variables into a selectable variable list VarList (1) of a first layer.

(2) Selecting N of the mth layer from VarList (m)_mAnd (6) candidate variables.

(3) N based on the selected mth layer_mGenerating R of mth layer based on Boolean logic according to predetermined rule by using candidate variables_mA logic expression, that is, a logic expression where m is 1.

(4) When m is<LgLv _ cnt, R_mAdding the logic expression to the optional variable list VarList (m) of the mth layer, updating the optional variable list VarList (m +1) of the mth +1 layer, and adding the logic expression to the optional variable list VarList (m) of the mth layer<Step (5) is executed when LgLv _ cnt-1 is executed, and step (6) is executed when m ═ LgLv _ cnt-1. The loop ends when m ═ LgLv _ cnt.

(5) Let m be m +1, and increase the selection condition "include R generated in the mth layer when selecting the candidate variable_mAnd (2) to (4) are re-executed, and logic expressions of each logic level of m-2-m-LgLv _ cnt-1 are generated in a loop mode.

(6) Let m be m +1, and increase the selection condition "include R generated in the mth layer when selecting the candidate variable_mLogical expression generated by at least one 'and' of logical expressionsThe number of the formula is PO _ cnt ", then (2) to (4) are executed again, and a logical expression of m ═ LgLv _ cnt is generated in a loop.

Firstly, a method for generating a logic expression.

In the process of generating the combinational logic block containing the logic expression of the logic hierarchy of the LgLv _ cnt level, it is necessary to generate the corresponding R for any mth layer_mIn an embodiment of the present application, each logic expression is a logic function in an SOP form (Sum of product form), the logic function in the SOP form is expressed by a plurality of logic and terms (called cube, or called product term) through a Boolean Sum, and each logic and term is obtained by performing a logic and operation on a plurality of literals. A literal is the positive or negative phase of a candidate variable.

In one embodiment, the R-th logic expression of any m-th layer is generated according to the same predetermined rule, and R is more than or equal to 1 and less than or equal to R_mThe generation method includes, please refer to fig. 2:

1. n based on selected mth layer_mCandidate variable generation

Each logic and item is obtained by carrying out logic and operation on a plurality of candidate variables, and each candidate variable is in a positive phase or a reverse phase.

In generating

When there are logical AND entries, all N can be used_mThe candidate variables may be used only in part. At least two logic and items exist in each logic expression and are obtained by carrying out logic and operation on a plurality of different candidate variables, or K logic and items are obtained by carrying out logic and operation on a plurality of same candidate variables, wherein the K logic and items are differentIncluding the number and/or types of candidate variables. One specific method is as follows:

a. from N_mRandom selection among candidate variables

A number of candidate variables that are,

k is a parameter and the starting value is 1.

b. To selected

And carrying out logical AND operation on the candidate variables to generate a kth logical AND item, wherein each candidate variable is positive-phase or negative-phase.

c. If it is

Let k be k +1 and perform steps a-c again to generate the (k +1) th logical and term.

d. If it is

Then all are generated

A logical AND term.

Such as in one example, N_mThe candidate variables include a, b, c, d,

is 3. When k is 1, it is selected from a, b, c and d

The candidate variables are a, b and form the first logical and term ab. When k is 2, it is selected from a, b, c and d

A candidate variable is a, b and forms the secondThe logical AND term is ab ', and b' represents the inverse of the variable b. When k is 3, it is selected from a, b, c and d

The candidate variables are a, b, c and form the third logical and term abc. It can be seen that in this embodiment, the candidate variable d is not used to generate the logical and terms, the first and second generated logical and terms use the same number and type of two candidate variables, but the phases of the variables are different, and the third generated logical and term uses a different number and type of candidate variables than the remaining two logical and terms.

The number of logical AND items contained in the mth logical expression of the mth layer

The configuration or random generation can be customized, and in one embodiment, the parameter experm _ max (m, r) can also be customized, and defines the maximum number of variables for performing logic or operation in the r-th logic expression of the m-th layer, so that the number of logic and terms in the r-th logic expression of the m-th layer

Not exceeding the corresponding ExpTerm _ max (m, r), i.e.

When at least one of m and r is different, the corresponding experm _ max (m, r) may be the same or different.

2. To pair

And carrying out logical OR operation on the logical AND items to generate an r-th logical expression of the m-th layer. For example, in the above example, the logical or operation is performed on the generated three logical and terms, and the generated mth logical expression of the mth layer is

Wherein + represents a logical or operation, also known as Boolean sum.

Then, other logic expressions of the mth layer may be generated in the same manner as described above. Optionally, at least two logic expressions in the mth layer contain different numbers of logic AND terms, or all R_mEach logic expression contains the same number of logical and terms. For example, in the above example, one logic expression includes three logic and terms, another logic expression may be different from the three logic and terms, and the other logic expression includes four logic and terms, and the number and the type of the logic variables used in the different logic expressions may be the same or different.

In one embodiment, it is also detected whether there are unused input variables that are unused in generating a logic expression of the LgLv _ cnt level logic hierarchy when m ═ LgLv _ cnt. If there is no unused input variable, then R is set_mThe logic expressions are correspondingly output to PO _ cnt output variables. If there are unused input variables, the unused input variables are added to the logical expression at the LgLv _ cnt level, thereby ensuring that all input variables are used, as shown in fig. 3. The manner of addition may be varied, and in one embodiment, a number of logical and terms are generated from all the unused input variables, each logical and term is derived from a logical and operation of a number of unused input variables, each of which is either positive or negative. And adding the logical AND terms generated by all the unused input variables into any one or more logical expressions of the L-th layer.

And secondly, injecting a Boolean space which can be optimized by a Boolean type to realize the Boolean type optimization.

There are three basic methods for multilevel logic optimization, namely algebra logic optimization, Boolean logic optimization and composition of Boolean functions, the algebraic logic optimization refers to performing algebraic operations on a logic expression, including decomposition, extraction, factorization, replacement and elimination, and the Boolean logic optimization and Boolean function decomposition refer to processing relevant output independent items formed by Boolean space, so as to achieve the purpose of simplifying the logic expression. The scholars propose algorithms of four aspects related to multilevel logic optimization, which are respectively as follows: the method includes a factoring logic function, a simple logic function of a logic function, a global phase assignment and a timing optimization, and also includes various derived methods based on these basic methods, such as a network reconstruction method and a node minimization method. The above methods are all important ways of logic optimization, and various ways may exist simultaneously or at various stages in the optimization process, sometimes achieving better effects.

By using the method provided by the application, the purpose of predicting the scale of the test case can be achieved by controlling the number PI _ cnt of the input signals, the number PO _ cnt of the output signals and the number LgLv _ cnt of the logic levels, the algebraic optimization effect can be compared obviously, and the optimization effect on the algebraic optimization strategy can be better driven. While also regarding area optimization, there is boolean optimization, i.e. processing output "irrelevant item" or "redundant item" composed of boolean space to achieve the effect of optimizing the area, therefore, in another embodiment, a method is provided, which can also inject boolean space capable of being boolean optimized in controllable scale to achieve the purpose of testing boolean optimization, in this embodiment, the relevant content of boolean space is first described as follows:

a min term (minterm) is a logical AND term that contains all of the candidate variables that make up the corresponding logical expression, each candidate variable existing in the logical AND term in either a positive or negative phase. For example, for a logic expression with three candidate variables a, b, and c:

F＝abc+abc′+ab′c+ab′c′+a′bc+a′bc′+a′b′c+a′b′c′

the logic expression includes 8 logic and terms, which are all min terms. Assuming that the above logical expression is F ═ ab + ab 'c + ab' c '+ a' bc + a 'bc' + a 'b' c + a 'b' c ', the logical and term ab is not a min term, since it includes both min terms abc, abc'. N Boolean variables define an N-dimensional Boolean spaceBooth (Boolean Space). The N-dimensional Boolean space has 2^NThe min terms. If a logic expression contains 2^NThe min terms, the logic function contains 100% of the N-dimensional Boolean space. For example, F ═ abc + abc '+ ab' c + ab 'c' + a 'bc + a' bc '+ a' b 'c + a' b 'c' includes all 8 minterms in the three-dimensional boolean space, which is a logical expression including 100% of the three-dimensional boolean space. The embodiment can inject Boolean space which can be optimized by Boolean type and can be controlled in scale based on the principle, thereby achieving the purpose of testing the Boolean type optimization.

The method for testing the boolean-optimized combinational logic block and the testing algebraic optimization method can be regarded as the implementation of additionally adding a logic part capable of boolean optimization in the method for testing algebraic optimization. As shown in fig. 3, in the above embodiment of the execution method for generating the r-th logic expression of any m-th layer, if the r-th logic expression of the m-th layer does not contain a redundant item, K is generated_m ^rAfter a logical AND term, directly to K_m ^rAnd carrying out logical OR operation on the logical AND items to generate an r-th logical expression of the m-th layer, namely forming a logical expression for testing algebraic optimization. If the r logic expression of the m layer contains redundant items, based on the generated K_m ^rThe logic and items construct at least one group of logic and items which can be optimized by Boolean space, and all the logic and items are subjected to logic OR operation to generate the r-th logic expression of the m-th layer, at the moment, the logic and items which participate in the logic OR operation comprise the constructed logic and items which can be optimized by Boolean space and the logic and items which are initially generated and have no parameter to construct redundant items, namely, the combinational logic expression of output 'irrelevant items' or 'redundant items' formed by Boolean space is purposefully created. That is, whether to inject the boolean-space-optimized redundancy item or not is self-configurable, one logic level may have one or more logic expressions into which the boolean-space-optimized redundancy item is injected, and one or more logic levels may have the boolean-space-optimized redundancy item injected into them in the entire combinational logic block.

Specifically, T input variables are selected for at least one logic and item, the selected T input variables and the corresponding one logic and item are subjected to logic and operation respectively according to a plurality of different normal phase and reverse phase combination modes, a group of logic and items capable of being optimized in a Boolean space is constructed, and at least one input variable in the formed group of logic and items capable of being optimized in the Boolean space has both a normal phase form and a reverse phase form. Wherein, the selected T input variables can be coincided with or completely different from the input variables contained in the logic and items. Optionally, the configuration parameter Dim _ max may be customized, where Dim _ max represents the maximum dimension of the injection boolean space, and when the boolean space is injected, the total number of boolean space variables, that is, the sum of T selected each time, does not exceed Dim _ max.

Optionally, a boolean space may be injected according to the above method, or the step of selecting T input variables for at least one logical and item is executed again to continue to generate a plurality of boolean spaces in a loop until a logical and item that can be boolean-space optimized for the B _ cnt group is constructed, where the B _ cnt is a parameter configured by a user.

For example, the logical and items included in the first logical expression of the third layer generated according to the method provided in the first partial embodiment include abc and adF₁ ²、

Wherein a, b, c, d are input variables, F₁ ²Representing a second logical expression generated at the first level of the logical hierarchy,

representing the first logical expression generated by the second level logical hierarchy. If no redundant item is contained, the first logic expression for directly generating the third layer can be recorded as

When the redundancy item is to be included, the method is as follows:

for one of the logical AND items

Selecting corresponding T-2 input variables as e and f, combining the two input variables e and f according to a plurality of different normal phase and reverse phase combination modes

And carrying out logical AND operation to construct a group of logical AND terms which can be optimized by Boolean space. For example, one approach is to construct a set of Boolean-space-optimized logical AND terms that includes

All the logical AND items include abc and adF₁ ²、

If only one Boolean space needs to be generated, the first logic expression for generating the third layer can be recorded as

As another example, constructing a formed set of Boolean-space-optimized logical AND terms includes

At this time, if only one boolean space needs to be generated, the first logic expression for generating the third layer may be recorded as

The loop may then continue to generate B _ cnt boolean spaces. Therefore, a test case which is injected with B _ cnt number of Boolean spaces which can be optimized and the maximum dimension of the injected Boolean spaces does not exceed Dim _ max can be generated, the Boolean optimization effect can be obviously compared, and the optimization effect on the Boolean optimization strategy can be better driven.

And thirdly, adding other functions.

As shown in fig. 4, the formed test case includes two parts, namely a mandatory module and an optional module, wherein the mandatory module includes a module declaration module, a variable instantiation module, and a module termination module. The module declaring module is mainly used for declaring a module name, and the format is as follows: "module Module eName". The variable instantiation module is mainly used for declaring input and output variables, and the format is as follows: "input A, B, C; output F1, F2; ", the specific format here is somewhat different depending on Verilog version, 1995 version and 2001 version. The module end module has only "endmodule".

The selectable modules comprise a variable declaration module and a statement execution block, and the variable declaration module is used for declaring intermediate variables as the name implies. The sentence execution block is a main body of the entire generation method, and in the present application, mainly includes a combinational logic block formed by the above method. Therefore, when the test case is constructed and obtained based on the generated combinational logic block, firstly, a statement execution block is formed based on the combinational logic block, then, the statement execution block and the variable declaration module form an optional module, and finally, the optional module and the optional module are combined to form the finished test case.

The pure combinational logic block is mainly used for testing the Boolean type effect and the effect of algebraic type optimization, namely the effect of area optimization, of course, the performance may be influenced by only using pure area optimization, and in this case, a balance needs to be obtained between the area and the performance, and the balance is determined by timing-driven optimization, and the factors influencing the timing include the number of logic levels and fan-outs, and the effect of the timing is greatly influenced by too high logic levels and too many fan-outs. When the effect of the sequential driving needs to be tested, registers need to exist, so that optionally in the method of an embodiment, registers are added before and after the input and the output of the generated combinational logic block respectively, so that the combinational logic block can be placed between the registers, the area optimization can be driven through the sequential driving, and the balance is found, or the registers are added in the generated combinational logic block, the output of the registers is used as the boundary for dividing, and then the optimization is performed, so that the test case can be close to the actual situation, and thus the test case added with the sequential logic can be constructed and obtained for testing the sequential driving optimization strategy.

In addition to adding sequential logic, optionally, when forming a statement execution block based on the combinational logic block, the statement execution block is formed by the generated combinational logic block and other execution blocks, the test case is formed and constructed by the statement execution block, and the other execution blocks include at least one of a predetermined statement block and other functional modules. Wherein the predetermined statement block is determined according to Verilog syntax, such as common if/case statement block and always statement block. Other functional modules may add other additional functionality to the test case. Optionally, the other functional modules include an arithmetic operation unit, and a data bus structure is correspondingly added in the variable declaration module and the variable instantiation module, so that the test of the comprehensive and optimization strategies of the arithmetic unit can be performed.

To illustrate the effectiveness of the methods provided herein, a comparison is made by the following example data:

in order to test the effect of different algebraic optimization strategies, a first part of methods is used for generating test cases of pure combinational logic blocks without injection of an optimizable Boolean space, then the test cases are integrated under different strategies, the obtained integrated LUT numbers are compared, the algebraic optimization strategies are selected accordingly, and a test set 1, namely set 1 for short, is created accordingly. The test results are shown in table 1 and fig. 5.

TABLE 1 test cases the number of LUTs after synthesis under algebraic optimization strategy

Test example	PI_cnt	PO_cnt	LgLv_cnt	Strategy	1	Strategy 2	Strategy 3
								Test example 1 set 1	10	10	5	131	87	109
Test example 2 set 1	10	10	7	280	277	250
							Test example 3 set 1	15	10	7	2627	1541	1575
Test example 4 set 1	15	15	7	2861	2185	1713
							Test example 5 set 1	20	5	5	1338	566	548
Test example 6 set 1	20	10	5	2486	1339	1408
							Test example 7 set 1	20	10	7	5527	3794	3678
Test example 8 set 1	20	15	5	1723	1608	1688
							Test example 9 set 1	20	20	5	4579	2362	2597
Test example 10 set 1	20	20	7	6358	6152	6189

As can be seen from table 1, as the number of the test cases in set 1 increases with the increase of the PI _ cnt, the PO _ cnt, and the LgLv _ cnt, the number of the LUTs obtained by the test cases in combination also increases, which means that the method provided by the present application can provide pure combinational logic test cases with different area sizes and complexity levels through the controllable PI _ cnt, the PO _ cnt, and the LgLv _ cnt. Strategy 1 in table 1 is the result of directly mapping the logic expression into 6-LUT, and strategy 2 adopts algebraic optimization strategy, i.e. decomposition (decomposition) of logic netlist and extraction (organization) of common expression using algebraic model. Strategy 3 adds algebraic network reconstruction (re-composition) and re-extraction of common expression (re-factor) on the basis of strategy 2. Corresponding to table 1 is fig. 5, and as can be seen from fig. 5, the number of LUTs after integration is significantly reduced for strategy 2 and strategy 3 compared to strategy 1.

In order to test the effect of the Boolean type optimization strategy, a test case of combinational logic is selected, different numbers of Boolean spaces which can be optimized are injected, the Boolean spaces form different scales by different numbers of variables, and finally a group of new test case set 2, set 2 for short, is generated. For example, in test example 3 in table 2, 1 boolean space consisting of 9 variables was injected into the test example, and in test example 12, 6 boolean spaces were injected into the test example, which total 41 variables. The test cases are integrated under different strategies, the selected strategy is added with Boolean logic optimization besides algebraic optimization, and finally a better optimization strategy is found by utilizing the number comparison of the integrated LUTs. The test results are shown in table 2 and fig. 6.

TABLE 2 LUT numbers of different sizes of Boolean spaces injected into the same test case and synthesized under different strategies

Test example	B_cnt	Total number of Boolean space variables	Strategy	1	Strategy 2	Strategy 3	Strategy 4
								Set 2 test example 1	0	0	1021	823	595	474
Set 2 test example 2	1	3	1271	1291	637	615
							Set 2 test example 3	1	9	1381	1314	695	603
Set 2 test example 4	2	7	1557	2083	621	648
							Set 2 test example 5	2	12	1886	1992	728	703
Set 2 test example 6	3	13	6170	2595	1184	698
							Set 2 test example 7	3	17	6900	2872	1054	673
Set 2 test example 8	4	10	7978	5856	1285	819
							Test example 9 set 2	4	17	7986	5778	1442	664
Set 2 test example 10	5	17	10828	8375	2382	994
							Set 2 test example 11	5	22	10848	8132	2462	924
Set 2 test example 12	6	41	15504	12135	3837	773

Strategies 1 and 2 in table 2 are the same as those used in table 1. Strategy 3 and strategy 4 add a strategy of boolean logic optimization in addition to algebraic optimization. Strategy 4 differs from strategy 3 in that strategy 4 enhances the search and identification of boolean spaces, making it more efficient to find and optimize boolean spaces that can be optimized. Fig. 6 corresponds to table 2, and as can be seen from fig. 6, the optimization effect of policy 3 is significantly better than that of policy 1 and policy 2, and policy 4 can better identify boolean optimization and algebraic optimization, so that the optimization effect is better than that of policy 3. As can be seen from fig. 6, as the number B _ cnt of the injected boolean spaces increases, the number of variables constituting the boolean spaces increases, and the redundancy items are more and more generated, specifically, as the number of the injected boolean spaces increases and the number of variables constituting the boolean spaces increases, the number of LUTs after the integration of the strategy 1, the strategy 2, and the strategy 3 also increases, the curves in the diagram tend to increase, and correspondingly, the number of LUTs after the integration under the strategy 4 tends to be substantially stable. In this case, if there is no boolean optimization or the boolean optimization is not good, it will have a great influence on the overall result.

Based on the characteristic of large capacity of the FPGA, the test of a large-capacity test case is necessary, and algebraic optimization and Boolean optimization should exist at the same time to meet a better target. According to the method, a group of test cases with larger capacity is generated, the used PI _ cnt is 30, the used PO _ cnt is 15, and the used LgLv _ cnt is 7, pure combinational logic with larger area and different logics is randomly generated on the basis, Boolean spaces which can be optimized in various scales are added, the group of test cases are integrated under the combination optimization strategy of algebraic optimization and Boolean optimization, the number of LUTs after integration is compared, a more optimal combination optimization strategy can be selected, and a test set 3, which is called as a set 3 for short, is created accordingly. The test results are shown in table 3 and fig. 7.

TABLE 3 LUT Numbers of larger area combinational logic test cases after synthesis under different strategies

Test example	B_cnt	Total number of Boolean space variables	Strategy	1	Strategy 2	Strategy 3	Strategy 4
								Set 3 test example 1	1	3	18107	12355	3106	1387
Set 3 test example 2	1	9	17574	9486	4372	213
							Set 3 test example 3	2	13	17905	12125	5483	1331
Set 3 test example 4	3	28	19507	9914	2918	396
							Set 3 test example 5	5	24	13393	9622	1410	784
Set 3 test example 6	5	33	19631	9701	5057	720
							Set 3 test example 7	6	40	15504	12135	3837	773

The strategy in table 3 is the same as used in table 2. As can be seen from fig. 7, the trend of the comprehensive results of the test cases of the four policy test sets 3 is also similar to that of fig. 6, that is, the optimization effect of policy 3 is significantly better than that of policy 1 and policy 2, and the optimization effect of policy 4 is better than that of policy 3, that is, the generated large-capacity test case can meet the purpose of verifying the optimization policy effect, and the quality of the optimization policy can be determined accordingly.

The table and the figures show that the optimization effect is continuously improved in the process of continuously adjusting the optimization strategy, which shows that the method provided by the application can be used for effectively testing and judging the advantages and disadvantages of the optimization strategy in the development process of the FPGA comprehensive tool, can provide effective drive for the development of the logic optimization effect of the comprehensive tool, and assists in improving the quality of the FPGA design tool.

Claims

1. A test case automatic generation method for optimizing FPGA comprehensive effect is characterized by comprising the following steps:

if m<LgLv _ cnt, then R of the m-th layer_mOptional addition of logical expressions to the mth layerUpdating the variable list to obtain an optional variable list of the m +1 th layer, making m equal to m +1 and executing the step of selecting the N of the m th layer from the optional variable list of the m th layer again_mA step of selecting a candidate variable;

and constructing a test case based on the generated combinational logic block.

2. The method of claim 1, wherein the selecting is based on N of mth layer_mGenerating R of mth layer based on Boolean logic according to predetermined rule by using candidate variables_mA logical expression including 1 ≦ R ≦ R in generating the mth logical expression of the mth layer_m：

N based on selected mth layer_mCandidate variable generation

Each logic and item is obtained by carrying out logic and operation on a plurality of candidate variables, and each candidate variable is in a positive phase or a reverse phase;

to pair

And carrying out logical OR operation on the logical AND items to generate an r-th logical expression of the m-th layer.

3. The method of claim 2, wherein at least two logical expressions at the mth level contain different numbers of logical AND terms, or all of R_mEach logic expression comprises the same number of logic and terms; at least two logic and items exist in each logic expression and are obtained by carrying out logic and operation on a plurality of different candidate variables, or K logic and items are obtained by carrying out logic and operation on a plurality of same candidate variables.

4. The method of claim 1, wherein R is generated except for the LgLv _ cnt layer_{LgLv_cnt}Except for the PO _ cnt logic expressions, the number of the logic expressions in the remaining layers is equal, or the number of the logic expressions in at least two layers is not equal.

5. The method of claim 2, further comprising:

if the r logic expression of the m layer does not contain redundant items, generating

After a logical AND item, directly pair

Carrying out logical OR operation on the logical AND items to generate an r-th logical expression of the m-th layer;

if the r logic expression of the m layer contains redundant items, based on the generated

And constructing at least one group of Boolean space-optimized logical AND terms by the logical AND terms, and carrying out logical OR operation on all the logical AND terms to generate the r-th logical expression of the m-th layer.

6. The method of claim 5, wherein the generating is based on

The logic AND item constructs at least one group of logic AND items which can be optimized by Boolean space, and the method comprises the following steps:

selecting T input variables for at least one logic and item, and performing logic and operation on the selected T input variables and the corresponding logic and item according to a plurality of different positive phase and reverse phase combination modes to construct a group of logic and items capable of being optimized in Boolean space.

7. The method of claim 6, further comprising:

and re-executing the step of selecting the T input variables for at least one logic and item until the B _ cnt group of logic and items which can be optimized in the Boolean space are constructed.

8. The method according to any one of claims 1-7, further comprising:

detecting whether there is an unused input variable that is an input variable that is not used when generating a logic expression of an LgLv _ cnt-level logic hierarchy when m is LgLv _ cnt;

if there is no unused input variable, then R is set_mThe logic expressions are correspondingly output to PO _ cnt output variables;

if there are unused input variables, the unused input variables are added to the logical expression of the LgLv _ cnt-th layer.

9. The method of claim 8, wherein adding unused input variables to the logic expression at level L comprises:

generating a plurality of logic and terms by all the unused input variables, wherein each logic and term is obtained by performing logic and operation on the plurality of unused input variables, and each unused input variable is taken as a positive phase or a negative phase;

and adding the logical AND terms generated by all the unused input variables into any one or more logical expressions of the L-th layer.

10. The method according to any one of claims 1 to 7,

selecting N of mth layer from selectable variable list of mth layer_mAnd all the candidate variables do not reach the corresponding highest fan-out number.

11. The method according to any one of claims 1-7, further comprising:

and respectively adding registers before and after the input and the output of the generated combinational logic block, or adding registers in the generated combinational logic block and constructing a test case added with sequential logic.

12. The method according to any of claims 1-7, wherein constructing a test case based on the generated combinational logic block comprises:

and forming a statement execution block by the generated combinational logic block and other execution blocks, forming and constructing a test case by the statement execution block, wherein the other execution blocks comprise at least one of a preset statement block and other functional modules.

13. The method of claim 12,

the other functional modules comprise arithmetic operation units.