CN113394106A - Anti-punch-through doping method of FinFET structure - Google Patents
Anti-punch-through doping method of FinFET structure Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 57
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 57
- 239000010703 silicon Substances 0.000 claims abstract description 57
- 239000000758 substrate Substances 0.000 claims abstract description 55
- 238000005530 etching Methods 0.000 claims abstract description 24
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 13
- 239000011574 phosphorus Substances 0.000 claims abstract description 13
- 238000000151 deposition Methods 0.000 claims abstract description 11
- 238000003475 lamination Methods 0.000 claims abstract description 11
- 238000000137 annealing Methods 0.000 claims abstract description 6
- 239000000463 material Substances 0.000 claims description 9
- 239000005360 phosphosilicate glass Substances 0.000 description 19
- 238000010586 diagram Methods 0.000 description 17
- 230000035515 penetration Effects 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 230000000717 retained effect Effects 0.000 description 4
- 239000005368 silicate glass Substances 0.000 description 4
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 210000000746 body region Anatomy 0.000 description 2
- 239000004327 boric acid Substances 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- KGBXLFKZBHKPEV-UHFFFAOYSA-N boric acid Chemical compound OB(O)O KGBXLFKZBHKPEV-UHFFFAOYSA-N 0.000 description 1
- 125000005619 boric acid group Chemical group 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
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Abstract
The invention provides a punch-through resistant doping method of a FinFET structure.A plurality of laminated layers comprising a Fin structure, a buffer layer and a hard mask layer are formed on a silicon substrate; the lamination is divided into a first structure and a second structure; forming a first side wall on the side wall of the lamination; depositing an organic distribution layer; etching to expose the side wall part of the Fin structure; so that it wraps part of the Fin structure; forming second sidewalls to expose sidewall portions of the Fin structure in direct contact with the organic distribution layer; covering the BSG layer on the first and second structures and the silicon substrate; removing the BSG layer on the second structure; covering the second structure with a PSG layer; annealing to enable silicon in the BSG layer on the side wall of the Fin structure in the first structure and phosphorus in the PSG layer on the side wall of the Fin structure in the second structure to respectively laterally diffuse towards the inside of the Fin structure; diffusing silicon in the BSG layer and phosphorus in the PSG layer on the silicon substrate into the silicon substrate; covering the oxide layer and etching to expose the hard mask layer on the first and second structures; and etching the oxide layer, the BSG layer and the PSG layer to expose the upper end of the diffused part in the Fin structure.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a punch-through resistant doping method of a FinFET structure.
Background
With the continuous expansion of MOS scale, FinFET (FIN transistor) devices have become further technological development of CMOS, and the main advantage of FinFET structure is its superior electrostatic integrity, which depends largely on the channel morphology, fig. 1a shows a schematic diagram of a FinFET structure in the prior art, where FIN (FIN part) is wrapped by a Metal Gate (MG) below the depth H of FIN top, and there is a greater risk of penetration below FIN, especially when the source and drain channel is deeper and the doping concentration is higher.
After APT (anti-punch-through) doping injection at present, the damage problem exists, the doping concentration at the top of the FIN is extremely low, the mobility of a current carrier is high, and the performance of the FIN device is good; the FIN structure has a high bottom doping, and the dopant has a poor ability to diffuse upward to the channel, which is not good for improving the carrier mobility.
As shown in fig. 1b and fig. 1c, fig. 1b is a schematic diagram illustrating the anti-punch-through (APT) doping profile in the FIN structure body region in the prior art; fig. 1c shows a diagram of FIN bottom APT doping profile, from which it can be seen that FIN Height (HFIN) and Width (WFIN), parameters of APT doping peak position and tail are critical for the study.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a punchthrough doping method for a FinFET structure, which is used to solve the problem in the prior art that the high mobility in the channel at the bottom of FIN and the risk of penetration at the bottom of FIN cannot be satisfied simultaneously in the process of the FinFET structure.
To achieve the above and other related objects, the present invention provides a method for punch-through doping of a FinFET structure, comprising:
providing a substrate, and etching the substrate to form a plurality of Fin structures, wherein buffer layers are formed on the Fin structures; a hard mask layer is formed on the buffer layer; the Fin structure, the buffer layer and the hard mask layer form a laminated layer, wherein the laminated layer used as the NMOS is a first structure; the stack used as PMOS is a second structure;
step two, forming a first side wall on the side wall of the lamination;
depositing an organic distribution layer covering the laminated layer, the first side wall and the upper surface of the silicon substrate; etching the organic distribution layer and the first side wall along the side wall of the laminated layer until the side wall part of the Fin structure is exposed; a part of the first side wall is still reserved at the bottom of the Fin structure; the organic distribution layer remains on the silicon substrate;
step four, continuously depositing an organic distribution layer on the rest organic distribution layer to wrap part of the Fin structure; forming second side walls on the Fin structure part above the organic distribution layer, the buffer layer and the side walls of the hard mask layer;
step five, removing all the organic distribution layer, and exposing the side wall part of the Fin structure in direct contact with the organic distribution layer;
sixthly, covering a BSG layer on the first structure, the second structure and the upper surface of the silicon substrate;
seventhly, removing the BSG layer on the second structure, and reserving the BSG layer on the first structure; then covering a PSG layer on the second structure;
step eight, annealing is carried out, so that silicon in the BSG layer on the side wall of the Fin structure in the first structure and phosphorus in the PSG layer on the side wall of the Fin structure in the second structure are respectively diffused towards the inside of the Fin structure in the lateral direction; simultaneously, silicon in the BSG layer on the upper surface of the silicon substrate and phosphorus in the PSG layer are respectively diffused into the silicon substrate below the upper surface of the silicon substrate;
covering an oxide layer on the first structure and the second structure to fill the space between the first structure and the second structure, and etching the oxide layer to expose the tops of the hard mask layers on the first structure and the second structure;
tenth, etching the oxide layer, the BSG layer and the PSG layer, completely exposing the part which is not diffused in the Fin structure, and simultaneously exposing the upper end of the diffused part in the Fin structure.
Preferably, the method for forming the first sidewall on the sidewall of the stack in the second step includes: depositing a first material on the silicon substrate covering the stack; and etching the first material to expose the top of the hard mask layer in the lamination, exposing the upper surface of the silicon substrate, and reserving the first material on the side wall of the lamination to form the first side wall.
Preferably, the BSG layer in the sixth step covers the upper surface of the silicon substrate, the first sidewalls of the first and second structures, the exposed sidewall portions of the Fin structure, the second sidewalls, and the sidewalls and the top of the hard mask layer.
Preferably, in the seventh step, the BSG layer on the upper surface of the silicon substrate on both sides of the second structure is removed at the same time as the BSG layer on the second structure is removed.
Preferably, in the seventh step, the BSG layer on the silicon substrate on both sides of the first structure is retained while the BSG layer on the first structure is retained.
Preferably, in the seventh step, the PSG layer covers the second structure, and the upper surfaces of the silicon substrates on both sides of the second structure are also covered with the PSG layer.
Preferably, in the ninth step, the oxide layer is covered on the first and second structures by using FVCD method.
As described above, the anti-punch-through doping method of the FinFET structure of the present invention has the following beneficial effects: according to the invention, different types of penetration-resistant doping are respectively carried out on the Fin structures of NMOS and PMOS, and the doped regions in the Fin structures are effectively controlled by using the boric acid silicate glass and the phosphoric acid silicate glass, so that the damage to the Fin structures after doping injection can be prevented, the penetration resistance of the injection is improved, doped ions can be effectively diffused in the Fin structures, the distribution of phosphorus and boron in the Fin structures is improved, the mobility of carriers is improved, and the performance of devices is improved.
Drawings
FIG. 1a shows a schematic diagram of a prior art FinFET structure;
FIG. 1b is a schematic diagram of a prior art anti-punch-through (APT) doping profile in the FIN structure body region;
FIG. 1c is a schematic diagram of a prior art FIN bottom APT doping profile;
FIG. 2 is a schematic diagram of a structure for forming a plurality of stacked layers on a substrate according to the present invention;
FIG. 3 is a schematic structural diagram of the stacked sidewalls after forming a first sidewall spacer according to the present invention;
FIG. 4 is a schematic structural diagram of the organic distribution layer and the first sidewall after etching;
fig. 5 is a schematic structural diagram of the Fin structure after forming a second sidewall spacer thereon according to the present invention;
FIG. 6 is a schematic view showing the present invention after removing the organic distribution layer to expose a portion of the sidewall of the Fin structure;
FIG. 7 is a schematic structural view of the first and second structures covered with a BSG layer according to the present invention;
FIG. 8 is a schematic diagram of a second structure covered with a PSG layer according to the present invention;
FIG. 9 is a schematic diagram of the annealed first and second structures of the present invention;
FIG. 10 is a schematic structural view of the first and second structures covered with an oxide layer according to the present invention;
FIG. 11 is a schematic structural diagram of the Fin structure after removing part of the oxide layer to expose the upper end of the diffused portion in the Fin structure according to the present invention;
fig. 12 is a flow chart of a method of anti-punch-through doping of a FinFET structure in the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 2 to 12. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The present invention provides a method for anti-punch-through doping of a FinFET structure, as shown in fig. 12, where fig. 12 is a flow chart of the method for anti-punch-through doping of a FinFET structure of the present invention, the method at least comprising the steps of:
providing a substrate, and etching the substrate to form a plurality of Fin structures, wherein buffer layers are formed on the Fin structures; a hard mask layer is formed on the buffer layer; the Fin structure, the buffer layer and the hard mask layer form a laminated layer, wherein the laminated layer used as the NMOS is a first structure; the stack used as PMOS is a second structure; as shown in fig. 2, fig. 2 is a schematic structural diagram illustrating a plurality of stacked layers formed on a substrate according to the present invention. Etching the substrate 01 to form a plurality of Fin structures 02, wherein buffer layers 03 are formed on the Fin structures; a hard mask layer 04 is formed on the buffer layer 03; the Fin structure 02, the buffer layer 03 and the hard mask layer 04 form a laminated layer, wherein the laminated layer used as an NMOS is a first structure; the stack used as PMOS is a second structure. In fig. 2 it is exemplarily shown that one of said stacks located on the left is a first structure and two of said stacks located in the middle and on the right are a second structure.
Step two, forming a first side wall on the side wall of the lamination; as shown in fig. 3, fig. 3 is a schematic structural diagram of the stacked sidewalls after the first sidewalls are formed thereon. In this second step, the first sidewall 05 is formed on the sidewall of the stack.
Further, in the second step of this embodiment, the method for forming the first sidewall on the sidewall of the stack includes: depositing a first material on the silicon substrate 01 covering the stack; and then etching the first material to expose the top of the hard mask layer 04 in the lamination, and exposing the upper surface of the silicon substrate 01, and retaining the first material on the side wall of the lamination to form the first side wall 05.
Depositing an organic distribution layer covering the laminated layer, the first side wall and the upper surface of the silicon substrate; etching the organic distribution layer and the first side wall along the side wall of the laminated layer until the side wall part of the Fin structure is exposed; a part of the first side wall is still reserved at the bottom of the Fin structure; the organic distribution layer remains on the silicon substrate; as shown in fig. 4, fig. 4 is a schematic structural diagram of the organic distribution layer and the first sidewall spacers after etching. Depositing an organic distribution layer 06 covering the stack and the first sidewall 05 thereon and the upper surface of the silicon substrate 01; etching the organic distribution layer 06 and the first side wall 05 along the side wall of the laminated layer until the side wall part of the Fin structure 02 is exposed; a part of the first side wall is still reserved at the bottom of the Fin structure; the organic distribution layer 06 remains on the silicon substrate 01. That is, after etching the organic distribution layer and the first sidewall, the upper portions of the Fin structures of the first and second structures are exposed, and the bottoms of the Fin structures are still wrapped by the first sidewall and the organic distribution layer.
Step four, continuously depositing an organic distribution layer on the rest organic distribution layer to wrap part of the Fin structure; forming second side walls on the Fin structure part above the organic distribution layer, the buffer layer and the side walls of the hard mask layer; as shown in fig. 5, fig. 5 is a schematic structural view of the Fin structure after forming the second sidewall. In the fourth step, an organic distribution layer is continuously deposited on the rest of the organic distribution layer 06, so that the organic distribution layer wraps part of the Fin structure (as shown in fig. 5, the wrapped part is positioned on the first side wall, and the upper part of the Fin structure which is not wrapped by the organic distribution layer is wrapped by the second side wall); second sidewalls 07 are then formed on the portions of the Fin structure 02 above the organic distribution layer, the buffer layer 03, and the sidewalls of the hard mask layer 04.
Step five, removing all the organic distribution layer, and exposing the side wall part of the Fin structure in direct contact with the organic distribution layer; as shown in fig. 6, fig. 6 is a schematic view illustrating the sidewall of the Fin structure exposed after the organic distribution layer is removed in the present invention. This step five will remove all of the organic distribution layer 06 in fig. 5, and the sidewall portions of the Fin structure in direct contact with the organic distribution layer 06 (the sidewalls of the Fin structure directly wrapped by the organic distribution layer) are exposed.
Sixthly, covering a BSG layer on the first structure, the second structure and the upper surface of the silicon substrate; as shown in fig. 7, fig. 7 is a schematic structural view of the first and second structures covered with the BSG layer according to the present invention. In the sixth step, a BSG layer 08 covers the first and second structures and the upper surface of the silicon substrate.
Further, the BSG layer 08 in step six of this embodiment covers the top surface of the silicon substrate 01, the first sidewalls 05 of the first and second structures, the exposed sidewall portions of the Fin structure, the second sidewalls 07, and the sidewalls and the top of the hard mask layer 04.
Seventhly, removing the BSG layer on the second structure, and reserving the BSG layer on the first structure; then covering a PSG layer on the second structure; as shown in fig. 8, fig. 8 is a schematic structural view of the second structure covered with a PSG layer according to the present invention. This step seven removes the BSG layers on the second structure (the stack on the middle and right in fig. 8), leaving the BSG layer 08 on the first structure (the stack on the left in fig. 8); the second structure is then covered with a PSG layer 09. Wherein the BSG layer is boric acid silicate glass, and the PSG layer is phosphoric acid silicate glass.
As shown in fig. 8, in the seventh step of this embodiment, the BSG layer on the upper surface of the silicon substrate on both sides of the second structure is removed at the same time as the BSG layer on the second structure is removed.
Further, in the seventh step of the present embodiment, while the BSG layer on the first structure is retained, the BSG layers on the silicon substrates on both sides of the first structure are also retained.
Further, in the seventh step of this embodiment, the PSG layer covers the second structure, and the PSG layer covers the upper surface of the silicon substrate on both sides of the second structure.
Step eight, annealing is carried out, so that silicon in the BSG layer on the side wall of the Fin structure in the first structure and phosphorus in the PSG layer on the side wall of the Fin structure in the second structure are respectively diffused towards the inside of the Fin structure in the lateral direction; simultaneously, silicon in the BSG layer on the upper surface of the silicon substrate and phosphorus in the PSG layer are respectively diffused into the silicon substrate below the upper surface of the silicon substrate; as shown in fig. 9, fig. 9 is a schematic structural view of the first and second structures after annealing in the present invention. After the annealing is carried out in the eighth step, the silicon in the BSG layer 08 on the side wall of the Fin structure in the first structure and the phosphorus in the PSG layer 09 on the side wall of the Fin structure in the second structure are respectively diffused laterally into the Fin structure (the Fin structure part 11 after the silicon is diffused and the Fin structure part 10 after the phosphorus is diffused); and simultaneously, the silicon in the BSG layer on the upper surface of the silicon substrate and the phosphorus in the PSG layer are respectively diffused into the silicon substrate below the upper surface of the silicon substrate.
Covering an oxide layer on the first structure and the second structure to fill the space between the first structure and the second structure, and etching the oxide layer to expose the tops of the hard mask layers on the first structure and the second structure; as shown in fig. 10, fig. 10 is a schematic structural view of the first and second structures covered with the oxide layer according to the present invention. Covering an oxide layer 12 on the first and second structures to fill the space between the first and second structures, and etching the oxide layer to expose the tops of the hard mask layers on the first and second structures.
Further, in the ninth step of this embodiment, the oxide layer is covered on the first and second structures by using FVCD method.
Tenth, etching the oxide layer, the BSG layer and the PSG layer, completely exposing the part which is not diffused in the Fin structure, and simultaneously exposing the upper end of the diffused part in the Fin structure. As shown in fig. 11, fig. 11 is a schematic structural diagram of the Fin structure after removing a portion of the oxide layer to expose the upper end of the diffused portion in the Fin structure.
In summary, the invention respectively carries out different types of anti-penetration doping on the Fin structures of NMOS and PMOS, and utilizes the borosilicate glass and the phosphosilicate glass to effectively control the doping area in the Fin structure, thereby preventing the Fin structure from being damaged after doping implantation, improving the penetration resistance of implantation, effectively diffusing doping ions in the Fin structure, improving the distribution of phosphorus and boron in the Fin structure, improving the mobility of carriers and improving the performance of devices. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (7)
1. A method of anti-punch-through doping of a FinFET structure, comprising:
providing a substrate, and etching the substrate to form a plurality of Fin structures, wherein buffer layers are formed on the Fin structures; a hard mask layer is formed on the buffer layer; the Fin structure, the buffer layer and the hard mask layer form a laminated layer, wherein the laminated layer used as the NMOS is a first structure; the stack used as PMOS is a second structure;
step two, forming a first side wall on the side wall of the lamination;
depositing an organic distribution layer covering the laminated layer, the first side wall and the upper surface of the silicon substrate; etching the organic distribution layer and the first side wall along the side wall of the laminated layer until the side wall part of the Fin structure is exposed; a part of the first side wall is still reserved at the bottom of the Fin structure; the organic distribution layer remains on the silicon substrate;
step four, continuously depositing an organic distribution layer on the rest organic distribution layer to wrap part of the Fin structure; forming second side walls on the Fin structure part above the organic distribution layer, the buffer layer and the side walls of the hard mask layer;
step five, removing all the organic distribution layer, and exposing the side wall part of the Fin structure in direct contact with the organic distribution layer;
sixthly, covering a BSG layer on the first structure, the second structure and the upper surface of the silicon substrate;
seventhly, removing the BSG layer on the second structure, and reserving the BSG layer on the first structure; then covering a PSG layer on the second structure;
step eight, annealing is carried out, so that silicon in the BSG layer on the side wall of the Fin structure in the first structure and phosphorus in the PSG layer on the side wall of the Fin structure in the second structure are respectively diffused towards the inside of the Fin structure in the lateral direction; simultaneously, silicon in the BSG layer on the upper surface of the silicon substrate and phosphorus in the PSG layer are respectively diffused into the silicon substrate below the upper surface of the silicon substrate;
covering an oxide layer on the first structure and the second structure to fill the space between the first structure and the second structure, and etching the oxide layer to expose the tops of the hard mask layers on the first structure and the second structure;
tenth, etching the oxide layer, the BSG layer and the PSG layer, completely exposing the part which is not diffused in the Fin structure, and simultaneously exposing the upper end of the diffused part in the Fin structure.
2. The method of punchthrough-resistant doping of a FinFET structure of claim 1, wherein: in the second step, the method for forming the first side wall on the side wall of the laminated layer comprises the following steps: depositing a first material on the silicon substrate covering the stack; and etching the first material to expose the top of the hard mask layer in the lamination, exposing the upper surface of the silicon substrate, and reserving the first material on the side wall of the lamination to form the first side wall.
3. The method of punchthrough-resistant doping of a FinFET structure of claim 1, wherein: and the BSG layer in the sixth step covers the upper surface of the silicon substrate, the first side walls in the first and second structures, the exposed side wall parts of the Fin structure, the second side walls and the top of the hard mask layer.
4. The method of punchthrough-resistant doping of a FinFET structure of claim 1, wherein: and seventhly, removing the BSG layer on the second structure, and simultaneously removing the BSG layer on the upper surface of the silicon substrate on two sides of the second structure.
5. The method of punchthrough-resistant doping of a FinFET structure of claim 1, wherein: and step seven, retaining the BSG layer on the first structure, and retaining the BSG layer on the silicon substrate on two sides of the first structure.
6. The method of punchthrough-resistant doping of a FinFET structure of claim 1, wherein: in the seventh step, the PSG layer covers the second structure, and the PSG layer covers the upper surface of the silicon substrate on both sides of the second structure.
7. The method of punchthrough-resistant doping of a FinFET structure of claim 1, wherein: and step nine, covering the oxide layer on the first structure and the second structure by using an FVCD method.
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| US20220384193A1 (en) * | 2021-05-31 | 2022-12-01 | Shanghai Huali Integrated Circuit Corporation | Method for forming finfet super well |
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