CN112201692A - Fully-enclosed grid fin field effect transistor and manufacturing method thereof - Google Patents

Fully-enclosed grid fin field effect transistor and manufacturing method thereof Download PDF

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CN112201692A
CN112201692A CN202011056656.7A CN202011056656A CN112201692A CN 112201692 A CN112201692 A CN 112201692A CN 202011056656 A CN202011056656 A CN 202011056656A CN 112201692 A CN112201692 A CN 112201692A
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fully
layer
fin
gate
epitaxial layer
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黄秋铭
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The invention discloses a fully-enclosed gate fin field effect transistor, which comprises: the semiconductor device comprises a fin body, a plurality of semiconductor chips and a plurality of semiconductor chips, wherein an active region, a drain region and a plurality of fully-enclosed channel structures are formed on the fin body; a first groove formed after the fin body is removed is formed between the source drain region and the drain region; the fully-enclosed channel structures are formed in the first groove, spacing regions are arranged among the fully-enclosed channel structures, and the fully-enclosed channel structures and the spacing regions are alternately arranged in the longitudinal direction; each fully-enclosed channel structure consists of a first material epitaxial layer, and the spacing region is formed by performing self-aligned etching on a second material epitaxial layer; before the self-aligned etching, the first and second material epitaxial layers with different etching rates are longitudinally and alternately arranged in the first groove, and the gate structure fully covers the surface of each fully-enclosed channel structure. The invention also discloses a manufacturing method of the all-around gate fin field effect transistor. The invention can form a plurality of fully-enclosed channel structures on the fin body, thereby improving the performance of the device.

Description

Fully-enclosed grid fin field effect transistor and manufacturing method thereof
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a multi-channel all-around gate fin field effect transistor (FinFET). The invention also relates to a manufacturing method of the all-around gate fin field effect transistor.
Background
With the development of integrated circuits, the device size is smaller and higher, and with the continuous reduction of the feature size of semiconductor devices, the conventional planar semiconductor manufacturing technology cannot be used, and non-planar semiconductor devices are produced, such as silicon-on-insulator, dual-gate, multi-gate, and other new processes. At present, fin field effect transistors are widely used in the field of small size, and semiconductor devices having a gate-all-around structure are sought in the semiconductor industry due to their device performance and special performance of effectively suppressing short channel effect (short channel effect). Because the channel of the device is surrounded by the grid, the influence of the leakage field of the device is eliminated, and the problems of leakage and punch-through of the device are effectively inhibited. Because the fully-wrapped-around gate is suspended above the bottom substrate, the manufacturing process of the fully-wrapped-around gate device is complicated.
Disclosure of Invention
The invention aims to provide a full-surrounding gate Fin type field effect transistor, which can form a plurality of full-surrounding channel structures on a Fin body (Fin), so that the performance of a device can be improved. Therefore, the invention also provides a manufacturing method of the all-around gate fin field effect transistor.
To solve the above technical problem, the present invention provides a fully-wrapped-gate fin field-effect transistor, including:
the semiconductor device comprises a fin body formed on a semiconductor substrate, and an active region, a drain region and a plurality of fully-enclosed channel structures are formed on the fin body.
And a first groove formed after the fin body is removed is arranged between the source region and the drain region.
The fully-enclosed channel structures are formed in the first groove, space regions are arranged between the fully-enclosed channel structures, and the fully-enclosed channel structures and the space regions are alternately arranged in the longitudinal direction from the bottom surface to the top surface of the fin body.
Each fully-enclosed channel structure consists of a first material epitaxial layer, and the spacing region is formed by performing self-aligned etching on a second material epitaxial layer; before the self-aligned etching, the first material epitaxial layers and the second material epitaxial layers are longitudinally and alternately arranged in the first grooves, and the first material epitaxial layers and the second material epitaxial layers have different etching rates.
The gate structure fully covers the surface of each fully-enclosed channel structure.
In a further refinement, the semiconductor substrate comprises a silicon substrate.
In a further improvement, the fin body is formed by etching the semiconductor substrate.
In a further improvement, the width of the fin body at the positions of the source region and the drain region is larger than the width of the fin body at the corresponding position of the fully-enclosed channel structure.
In a further improvement, an embedded epitaxial layer is also formed in the source region and the drain region.
In a further refinement, the material of the epitaxial layer of the first material comprises silicon.
The material of the second material epitaxial layer comprises silicon germanium.
In a further improvement, in the same first groove, the number of the fully-enclosed channel structures is more than 2.
In a further improvement, the gate structure comprises a gate dielectric layer and a gate conductive material layer.
The further improvement is that the gate dielectric layer is made of silicon oxide, and the gate conductive material layer is a polysilicon gate.
Or, the gate dielectric layer is made of a high dielectric constant layer, and the gate conductive material layer is a metal gate.
In order to solve the technical problem, the method for manufacturing the fully-wrapped-gate fin field effect transistor provided by the invention comprises the following steps:
providing a semiconductor substrate with a fin field effect transistor base body, wherein the fin field effect transistor base body comprises a source region, a drain region and a fin channel structure; the source region and the drain region are both formed on a fin body, and the fin channel structure is composed of the fin body located between the source region and the drain region.
And covering a first mask layer on the top surface of the fin field effect transistor substrate.
And secondly, forming a second covering layer on the surface of the semiconductor substrate outside the fin field effect transistor substrate, wherein the top surface of the second covering layer is level to the top surface of the first mask layer.
And step three, removing the first mask layer on the surface of the fin channel structure to open the top surface of the fin channel structure.
And fourthly, etching the fin type channel structure with partial thickness to form a first groove.
Fifthly, sequentially forming a second material epitaxial layer and a first material epitaxial layer in the first groove along the longitudinal direction; the first material epitaxial layer and the second material epitaxial layer have different etch rates.
And sixthly, etching the top surface of the second covering layer to be below the bottom surface of the second material epitaxial layer positioned at the bottommost layer so as to expose the side surfaces of each first material epitaxial layer and each second material epitaxial layer.
Seventhly, etching the second material epitaxial layer to form a spacing region in a self-alignment mode between the first material epitaxial layers; and forming a fully-enclosed channel structure by each epitaxial layer of the first material, wherein the fully-enclosed channel structure and each interval region are alternately arranged in the longitudinal direction from the bottom surface to the top surface of the fin body.
And step eight, forming a gate structure which fully covers the surface of each fully-surrounded channel structure.
In a further refinement, the semiconductor substrate comprises a silicon substrate.
In a further improvement, the fin body is formed by etching the semiconductor substrate.
In a further improvement, the width of the fin body at the positions of the source region and the drain region is larger than the width of the fin body at the corresponding position of the fully-enclosed channel structure.
In a further refinement, the material of the epitaxial layer of the first material comprises silicon.
The material of the second material epitaxial layer comprises silicon germanium.
In a further improvement, in the same first groove, the number of the fully-enclosed channel structures is more than 2.
The further improvement is that the first mask layer is a silicon nitride layer or a silicon oxide layer or a superposed layer of silicon nitride and silicon oxide.
In a further refinement, the material of the second capping layer comprises silicon oxide.
In a further improvement, the gate structure comprises a gate dielectric layer and a gate conductive material layer.
The invention can form a plurality of fully-enclosed channel structures on the fin body, thereby effectively inhibiting the short-channel effect of the device, eliminating the influence of the drain electric field of the device on the channel, and effectively inhibiting the problems of electric leakage and punch-through of the device, so the invention can well improve the performance of the device.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
fig. 1A is a perspective view of a fully wrapped-gate finfet in accordance with an embodiment of the present invention;
FIG. 1B is a corresponding cross-sectional view taken along dashed line 101 in FIG. 1A;
fig. 2A-2F are schematic device structures at various steps of a method for fabricating a fully-wrapped-gate finfet in accordance with an embodiment of the invention.
Detailed Description
Fig. 1A is a perspective view of a fully wrapped-gate finfet in accordance with an embodiment of the present invention; as shown in fig. 1B, which is a cross-sectional view taken along the dashed line 101 in fig. 1A; the all-around gate fin field effect transistor of the embodiment of the invention comprises:
the semiconductor device comprises a fin body formed on a semiconductor substrate 1, wherein an active region 2, a drain region 3 and a plurality of fully-enclosed channel structures 4 are formed on the fin body.
In the embodiment of the present invention, the semiconductor substrate 1 includes a silicon substrate.
The fin body is formed by etching the semiconductor substrate 1.
The width of the fin body at the positions of the source region 2 and the drain region 3 is larger than that of the fin body at the corresponding position of the fully-enclosed channel structure 4.
An embedded epitaxial layer is also formed in the source region 2 and the drain region 3.
A first groove 203 formed after the fin body is removed is arranged between the source region 2 and the drain region 3. The fin between the source region 2 and the drain region 3 in fig. 1B is denoted by reference numeral 4a, and the first recess 203 is shown with reference to fig. 2C. The fin 4a shown in fig. 1B is the portion remaining after the first recess 203 is formed, and a second capping layer 201 is also shown in fig. 1B.
The fully surrounding channel structures 4 are formed in the first groove 203, a spacing region is formed between each fully surrounding channel structure 4, and the fully surrounding channel structures 4 and the spacing regions are alternately arranged in the longitudinal direction from the bottom surface to the top surface of the fin body.
In the same first groove 203, the number of the fully-enclosed channel structures 4 is more than 2.
Each fully-enclosed channel structure 4 is composed of a first material epitaxial layer 4, and the spacing region is formed by performing self-aligned etching on a second material epitaxial layer 204; before the self-aligned etching, the first material epitaxial layers 4 and the second material epitaxial layers 204 are longitudinally and alternately arranged in the first grooves 203, and the first material epitaxial layers 4 and the second material epitaxial layers 204 have different etching rates. Referring to fig. 2D, the second material epitaxial layer 204 is also denoted by reference numeral 4.
In the embodiment of the present invention, the material of the epitaxial layer 4 of the first material is silicon. The second material epitaxial layer 204 is made of silicon germanium. In other embodiments, the materials of the first material epitaxial layer 4 and the second material epitaxial layer 204 can be selected as desired.
The gate structure covers the surface of each of the fully wrapped-around channel structures 4.
The gate structure comprises a gate dielectric layer 5 and a gate conductive material layer 6. In the embodiment of the present invention, the gate dielectric layer 5 is made of a high dielectric constant layer, and the gate conductive material layer 6 is a metal gate. In other embodiments can also be: the gate dielectric layer 5 is made of silicon oxide, and the gate conductive material layer 6 is a polysilicon gate.
According to the embodiment of the invention, the plurality of fully-enclosed channel structures 4 can be formed on the fin body, so that the short-channel effect of the device can be effectively inhibited, the influence of the drain electric field of the device on the channel can be eliminated, and the problems of electric leakage and punch-through of the device can be effectively inhibited, so that the performance of the device can be well improved.
Fig. 2A to 2F are schematic device structures in steps of a method for manufacturing a fully-wrapped-gate finfet in accordance with an embodiment of the present invention; fig. 2A is a perspective view corresponding to step one, and fig. 2A-2F are cross-sectional views of the first embodiment, the cross-sectional view being shown by a dashed box 101 in fig. 1A; the manufacturing method of the all-around gate fin field effect transistor comprises the following steps:
step one, as shown in fig. 2A, providing a semiconductor substrate 1 formed with a fin field effect transistor substrate, wherein the fin field effect transistor substrate comprises a source region 2, a drain region 3 and a fin channel structure; the source region 2 and the drain region 3 are both formed on a fin body, and the fin channel structure is composed of the fin body located between the source region 2 and the drain region 3.
A first mask layer 202 is formed overlying the top surface of the finfet body.
In the method of the embodiment of the present invention, the semiconductor substrate 1 includes a silicon substrate.
The fin body is formed by etching the semiconductor substrate 1.
The width of the fin body at the positions of the source region 2 and the drain region 3 is larger than that of the fin body at the corresponding position of the fully-enclosed channel structure 4.
An embedded epitaxial layer is also formed in the source region 2 and the drain region 3.
The first mask layer 202 is a silicon nitride layer or a silicon oxide layer or a stacked layer of silicon nitride and silicon oxide.
Step two, as shown in fig. 2B, a second capping layer 201 is formed on the surface of the semiconductor substrate 1 outside the finfet substrate, and a top surface of the second capping layer 201 is flush with a top surface of the first mask layer 202.
In the method according to the embodiment of the present invention, the material of the second capping layer 201 includes silicon oxide.
Step three, as shown in fig. 2C, the first mask layer 202 on the surface of the fin channel structure is removed to open the top surface of the fin channel structure.
Step four, as shown in fig. 2C, etching the fin channel structure with a part of thickness to form a first groove 203.
Step five, as shown in fig. 2D, sequentially forming a second material epitaxial layer 204 and a first material epitaxial layer 4 in the first groove 203 along the longitudinal direction; the first material epitaxial layer 4 and the second material epitaxial layer 204 have different etch rates.
In the method according to the embodiment of the present invention, the epitaxial layer 4 made of the first material is silicon. The second material epitaxial layer 204 is made of silicon germanium. In other embodiments, the materials of the first material epitaxial layer 4 and the second material epitaxial layer 204 can be selected as desired.
Sixthly, as shown in fig. 2E, etching the top surface of the second covering layer 201 to be below the bottom surface of the second material epitaxial layer 204 located at the bottommost layer to expose the side surfaces of each first material epitaxial layer 4 and each second material epitaxial layer 204.
Seventhly, as shown in fig. 2F, etching the second material epitaxial layer 204 to form a spacing region in self-alignment between the first material epitaxial layers 4; the fully surrounding channel structures 4 are formed by epitaxial layers 4 of the first material, and the fully surrounding channel structures 4 and the spaced regions are alternately arranged in the longitudinal direction from the bottom surface to the top surface of the fin body.
In the same first groove 203, the number of the fully-enclosed channel structures 4 is more than 2.
Step eight, as shown in fig. 1B, a gate structure is formed to fully cover the surface of each of the fully-enclosed channel structures 4.
The gate structure comprises a gate dielectric layer 5 and a gate conductive material layer 6. In the method of the embodiment of the invention, the gate dielectric layer 5 is made of a high dielectric constant layer, and the gate conductive material layer 6 is a metal gate. In other embodiments the method can also be: the gate dielectric layer 5 is made of silicon oxide, and the gate conductive material layer 6 is a polysilicon gate.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (18)

1. A fully wrapped-gate FinFET, comprising:
the semiconductor device comprises a fin body formed on a semiconductor substrate, wherein an active region, a drain region and a plurality of fully-enclosed channel structures are formed on the fin body;
a first groove formed after the fin body is removed is formed between the source region and the drain region;
the fully-enclosed channel structures are formed in the first groove, space regions are arranged between the fully-enclosed channel structures, and the fully-enclosed channel structures and the space regions are alternately arranged in the longitudinal direction from the bottom surface to the top surface of the fin body;
each fully-enclosed channel structure consists of a first material epitaxial layer, and the spacing region is formed by performing self-aligned etching on a second material epitaxial layer; before self-aligned etching, the first material epitaxial layers and the second material epitaxial layers are longitudinally and alternately arranged in the first grooves, and the first material epitaxial layers and the second material epitaxial layers have different etching rates;
the gate structure fully covers the surface of each fully-enclosed channel structure.
2. The fully-wrapped-gate finfet of claim 1, wherein: the semiconductor substrate includes a silicon substrate.
3. The fully-wrapped-gate finfet of claim 2, wherein: the fin body is formed by etching the semiconductor substrate.
4. The fully-wrapped-gate finfet of claim 3, wherein: the width of the fin body at the positions of the source region and the drain region is larger than that of the fin body at the corresponding position of the fully-enclosed channel structure.
5. The fully-wrapped-gate finfet of claim 4, wherein: and embedded epitaxial layers are also formed in the source region and the drain region.
6. The fully-wrapped-gate finfet of claim 2, wherein: the material of the first material epitaxial layer comprises silicon;
the material of the second material epitaxial layer comprises silicon germanium.
7. The fully-wrapped-gate finfet of claim 6, wherein: in the same first groove, the number of the fully-enclosed channel structures is more than 2.
8. The fully-wrapped-gate finfet of claim 1, wherein: the grid structure comprises a grid dielectric layer and a grid conductive material layer.
9. The fully-wrapped-gate finfet of claim 8, wherein: the gate dielectric layer is made of silicon oxide, and the gate conductive material layer is a polysilicon gate;
or, the gate dielectric layer is made of a high dielectric constant layer, and the gate conductive material layer is a metal gate.
10. A method for manufacturing a fully-wrapped-gate fin field effect transistor is characterized by comprising the following steps:
providing a semiconductor substrate with a fin field effect transistor base body, wherein the fin field effect transistor base body comprises a source region, a drain region and a fin channel structure; the source region and the drain region are both formed on a fin body, and the fin channel structure is composed of the fin body located between the source region and the drain region;
covering a first mask layer on the top surface of the fin field effect transistor substrate;
forming a second covering layer on the surface of the semiconductor substrate outside the fin field effect transistor substrate, wherein the top surface of the second covering layer is level to the top surface of the first mask layer;
removing the first mask layer on the surface of the fin channel structure to open the top surface of the fin channel structure;
etching the fin type channel structure with partial thickness to form a first groove;
fifthly, sequentially forming a second material epitaxial layer and a first material epitaxial layer in the first groove along the longitudinal direction; the first material epitaxial layer and the second material epitaxial layer have different etching rates;
sixthly, etching the top surface of the second covering layer to be below the bottom surface of the second material epitaxial layer positioned at the bottommost layer so as to expose the side surfaces of each first material epitaxial layer and each second material epitaxial layer;
seventhly, etching the second material epitaxial layer to form a spacing region in a self-alignment mode between the first material epitaxial layers; forming a fully-enclosed channel structure by each epitaxial layer of the first material, wherein the fully-enclosed channel structure and each interval region are alternately arranged in the longitudinal direction from the bottom surface to the top surface of the fin body;
and step eight, forming a gate structure which fully covers the surface of each fully-surrounded channel structure.
11. The method of claim 10, wherein: the semiconductor substrate includes a silicon substrate.
12. The method of claim 11, wherein: the fin body is formed by etching the semiconductor substrate.
13. The method of claim 12, wherein: the width of the fin body at the positions of the source region and the drain region is larger than that of the fin body at the corresponding position of the fully-enclosed channel structure.
14. The method of claim 11, wherein: the material of the first material epitaxial layer comprises silicon;
the material of the second material epitaxial layer comprises silicon germanium.
15. The method of claim 14, wherein: in the same first groove, the number of the fully-enclosed channel structures is more than 2.
16. The method of claim 10, wherein: the first mask layer is a silicon nitride layer or a silicon oxide layer or a superposed layer of silicon nitride and silicon oxide.
17. The method of claim 16, wherein: the material of the second capping layer includes silicon oxide.
18. The method of claim 10, wherein: the grid structure comprises a grid dielectric layer and a grid conductive material layer.
CN202011056656.7A 2020-09-30 2020-09-30 Fully-enclosed grid fin field effect transistor and manufacturing method thereof Pending CN112201692A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112864251A (en) * 2021-02-04 2021-05-28 上海华力集成电路制造有限公司 Fin type transistor and manufacturing method thereof
CN113471213A (en) * 2021-07-02 2021-10-01 上海集成电路材料研究院有限公司 Multi-gate MOS device based on embedded cavity SOI substrate and preparation method thereof
WO2023000200A1 (en) * 2021-07-21 2023-01-26 华为技术有限公司 Field effect transistor, manufacturing method therefor, and integrated circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014018201A1 (en) * 2012-07-27 2014-01-30 Intel Corporation Nanowire transistor devices and forming techniques
CN104011849A (en) * 2011-12-23 2014-08-27 英特尔公司 CMOS nanowire structure
CN106783615A (en) * 2016-11-22 2017-05-31 上海华力微电子有限公司 A kind of preparation method of all-around-gate pole fin-shaped semiconductor devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104011849A (en) * 2011-12-23 2014-08-27 英特尔公司 CMOS nanowire structure
WO2014018201A1 (en) * 2012-07-27 2014-01-30 Intel Corporation Nanowire transistor devices and forming techniques
CN106783615A (en) * 2016-11-22 2017-05-31 上海华力微电子有限公司 A kind of preparation method of all-around-gate pole fin-shaped semiconductor devices

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112864251A (en) * 2021-02-04 2021-05-28 上海华力集成电路制造有限公司 Fin type transistor and manufacturing method thereof
CN113471213A (en) * 2021-07-02 2021-10-01 上海集成电路材料研究院有限公司 Multi-gate MOS device based on embedded cavity SOI substrate and preparation method thereof
WO2023000200A1 (en) * 2021-07-21 2023-01-26 华为技术有限公司 Field effect transistor, manufacturing method therefor, and integrated circuit

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