CN113376508A

CN113376508A - Circuit board testing method, device and equipment

Info

Publication number: CN113376508A
Application number: CN202110633683.4A
Authority: CN
Inventors: 席雪华
Original assignee: Spreadtrum Communications Shanghai Co Ltd
Current assignee: Spreadtrum Communications Shanghai Co Ltd
Priority date: 2021-06-07
Filing date: 2021-06-07
Publication date: 2021-09-10

Abstract

The invention discloses a circuit board testing method, a device and a medium, wherein the method can be executed by a personal computer, and comprises the following steps: sending a first instruction to the tested device, wherein the first instruction is used for controlling a GPO on the tested device to output a first level; and sending a second instruction to the tested device, wherein the second instruction is used for indicating a GPIO on the tested device to report first information, the GPO is connected with the GPIO, an output signal of the GPO is used as an input signal of the GPIO, the first information reported by the tested device is received, the first information comprises a second level, and when the first level is consistent with the second level, the GPO is determined to be normal in function. The method can accurately detect whether the function of the GPO is normal.

Description

Circuit board testing method, device and equipment

Technical Field

The present invention relates to the field of integrated circuits, and in particular, to a method, an apparatus, and a device for testing a circuit board.

Background

Most electronic equipment is provided with a human-computer interaction interface, such as a key interface, a display screen interface, a camera interface and the like, and many peripherals of the electronic equipment are generally controlled by General-purpose output (GPO), so that the GPO needs to be tested in the circuit board generation process. The current testing method mainly depends on manual testing, so that the possibility of misjudgment exists. At present, testing of GPOs is also implemented by adding peripherals (such as field-programmable gate arrays (FPGAs)), but this causes a problem of high testing cost.

Disclosure of Invention

The embodiment of the invention provides a circuit board testing method, a device and equipment, which are used for accurately detecting whether the function of a GPO is normal or not under the condition of not using other equipment.

In a first aspect, the present invention provides a circuit board testing method, which may be performed by a PC including a terminal under test, wherein the method includes the steps of:

the PC sends a first instruction to the tested device, and the first instruction is used for controlling a general output GPO on the tested device to output a first level. And the PC also sends a second instruction to the tested device, wherein the second instruction is used for indicating a general purpose input/output (GPIO) on the tested device to report the first information, the GPO is connected with the GPIO, and an output signal of the GPO is used as an input signal of the GPIO. The PC receives first information reported by the tested equipment, wherein the first information comprises a second level; when the first level coincides with the second level, it is determined that the GPO functions normally. When the first level is not consistent with the second level, it is determined that the GPO is malfunctioning.

In the embodiment, the GPO is connected with the GPIO, so that the GPIO can acquire the output level of the GPO, whether the GPO function is abnormal or not can be judged by comparing the consistency between the output level acquired by the GPIO and the preset input level, whether the GPO function is normal or not can be accurately detected by the method without other equipment, the test cost can be saved, and the accuracy of the test result is improved.

In one possible design, the first level and the second level are both high; before determining that the GPO functions normally, the method further comprises: the PC sends a third instruction to the tested device, and the third instruction is used for controlling a GPO on the tested device to output a low level; the PC sends a fourth instruction to the tested device, wherein the fourth instruction is used for indicating a GPIO on the tested device to report second information, a GPO is connected with the GPIO, and an output signal of the GPO is used as an input signal of the GPIO; and the PC receives second information reported by the tested equipment, and determines that the GPO function is normal when the first level is consistent with the second level and the second information comprises a low level.

In this embodiment, the PC detects the output results of the high level and the low level of the GPO by using the two levels of the high level and the low level, and can comprehensively evaluate whether the function of the GPO is normal.

In a possible design, the invention also comprises the following step of connecting a GPIO and a GPO in pairs through the ejector pins of the jig in advance.

In one possible design, the upper computer and the device to be tested are connected through a data line.

In a second aspect, embodiments of the present application further provide a circuit board testing apparatus, which includes a module/unit for performing any one of the possible design methods of the first aspect. These modules/units may be implemented by hardware, or by hardware executing corresponding software.

In a third aspect, an embodiment of the present application provides an electronic device, which includes a processor and a memory. Wherein the memory is used to store one or more computer programs; the one or more computer programs stored in the memory, when executed by the processor, enable the terminal device to implement the method of any of the possible designs of the second aspect described above.

In a fourth aspect, this embodiment also provides a computer-readable storage medium, where the computer-readable storage medium includes a computer program, and when the computer program is run on an electronic device, the electronic device is caused to perform any one of the possible design methods of the foregoing aspects.

In a fifth aspect, the present application further provides a computer program product, which when run on a terminal, causes the electronic device to execute any one of the possible design methods of any one of the above aspects.

As for the advantageous effects of the above third to fifth aspects, reference may be made to the description in the above first aspect.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic diagram of a circuit board according to an embodiment of the present disclosure;

fig. 2 is a schematic diagram of a circuit board testing system according to an embodiment of the present disclosure;

fig. 3 is a schematic flow chart of a circuit board testing method according to an embodiment of the present disclosure;

fig. 4 is a schematic flow chart of another circuit board testing method according to an embodiment of the present disclosure;

fig. 5 is a schematic diagram of a circuit board testing apparatus according to an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

In order to make the technical solutions in the embodiments of the present invention better understood and make the above objects, features and advantages of the embodiments of the present invention more comprehensible, the following description of the prior art and the technical solutions in the embodiments of the present invention with reference to the accompanying drawings is provided.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The circuit board testing method in the embodiment of the present application can be applied to test module to module (M2M). M2M refers to a form of mounting, and M2M refers to a mounted communication module mounted on a Printed Circuit Board (PCB). In this embodiment, the M2M communication module may be a cellular communication module, a wireless fidelity (WiFi) module, a Long Term Evolution (LTE) module, a narrowband internet of things (NB-IoT) module, or the like. As shown in fig. 1, the M2M communication module includes a plurality of PIN PINs, and the PIN PINs may be used as General Purpose Inputs (GPIs), General Purpose Outputs (GPOs), or General Purpose Inputs and Outputs (GPIOs), in this embodiment, the M2M communication module includes General purpose-input/output (GPIO) interfaces and General purpose-output (GPIO) interfaces, and the number of the GPIO interfaces is at least two. In embedded systems, external devices or circuits are often controlled using GPIO interfaces, which may also provide input signals to the CPU, and GPO interfaces.

In this embodiment, in order to test whether the GPO functions are normal or not without using hardware devices such as an FPBA or a single chip microcomputer, a circuit board testing method is provided, in which the GPO and the GPIO are connected, a GPIO and a GPO are connected in pairs by using tool pins, and the mutually connected GPIO and GPO form a group of interfaces. As shown in FIG. 1, GPOA is connected to GPIO C and GPO B is connected to GPIO D. Therefore, the output of the GPO is obtained by the GPIO, the output signal of the GPO is used as the input signal of the GPIO, and then a Personal Computer (PC) judges whether the function of the GPO of the circuit board is normal or not by comparing the consistency of the levels.

Referring to fig. 2, a circuit board testing system is shown for the present application, which includes a PC10 and a terminal under test 20, wherein the terminal under test is located on a test fixture 30, the test fixture 30 is connected to a PC10 via a data line (e.g., a Universal Serial Bus (USB)), and the PC and the terminal under test 20 can interact via AT signaling.

Referring to fig. 3, a schematic flow chart of a circuit board testing method shown in the present application, which can be applied to the PC, includes the following steps.

S301, the PC sends a first instruction to the tested terminal, and the first instruction is used for controlling the GPO on the tested device to output a first level.

S302, the PC sends a second instruction to the tested device, and the second instruction is used for indicating a GPIO on the tested device to report the first information.

And S303, the PC receives first information reported by the tested device, wherein the first information comprises a second level.

S304, when the first level is consistent with the second level, the PC determines that the GPO function is normal, and when the first level is inconsistent with the second level, the PC determines that the GPO function is abnormal.

Referring to fig. 2, the PC10 includes a PC tool, for example, PC tools, which are connected to the test fixture 30 through a USB, the PC tools receive a first operation of a developer, and send a first instruction to the terminal to be tested in the test fixture in response to the first operation, where the first instruction is used to control a GPO a of the terminal to be tested to output a high level, and the GPIO C can obtain an output result of the GPO a because the GPO a is connected to the GPIO C. The PC tools receive a second operation of the developer, and send a second instruction to the terminal to be tested in the test fixture in response to the second operation, for example, the second instruction is used to control the GPIO C of the terminal to be tested to report the first information. And after receiving the second instruction, the GPIO C of the terminal to be tested reports the first information, the PC receives the first information, and if the first information is also high level, the output of the GPO is normal, so that the function of the GPO is normal. If the first information is low, it indicates that the output of the GPO is abnormal. Similarly, the first command is also used for controlling the GPOA of the terminal to be tested to output a low level, the PC receives the first information, if the first information is also a low level, the output of the GPO is normal, otherwise, the output of the GPO is abnormal. By analogy, the PC can test the GPO in each group of interfaces according to the method to obtain a test result.

In order to describe the above circuit board testing method more systematically, the present application provides a method flowchart as shown in fig. 4, including the following steps.

S401, the PC sends a first instruction to the tested device, and the first instruction is used for controlling the GPO on the tested device to be set at a high level.

S402, the PC sends a second instruction to the tested device, and the second instruction is used for indicating the GPIO on the tested device to report the first information.

And S403, the PC receives the first information reported by the tested device.

S404, the PC determines whether the first information is at a high level, if so, performs S405, otherwise, performs S409.

S405, when the first information is at a high level, the PC sends a third instruction to the tested device, and the third instruction is used for controlling the GPO on the tested device to be placed at a low level.

And S406, the PC sends a fourth instruction to the tested device, wherein the fourth instruction is used for indicating the GPIO on the tested device to report second information.

In S407, the PC determines whether the second information is at a high level, if so, performs S408, otherwise, performs S409.

S408, whether the second information is low, the PC determines that the GPO function is normal.

S409, the PC determines that the GPO function is abnormal.

Therefore, the GPO test method can finish the GPO test by connecting the GPO of the tested terminal with the GPIO and evaluating the output result of the GPIO level without adding a peripheral (for example, without a peripheral singlechip). The scheme has the advantages of low cost, high efficiency and strong universality. The embodiment has obvious detection advantages particularly for internet of things (IOT) modules.

Based on the foregoing circuit board testing method, in some embodiments of the present application, an embodiment of the present application discloses a circuit board testing apparatus, as shown in fig. 5, the apparatus 500 is configured to implement the method described in the foregoing method embodiments, and includes: a transmitting unit 501, a receiving unit 502 and a processing unit 503.

The sending unit 501 is configured to send a first instruction to a device under test, where the first instruction is used to control a general purpose output GPO on the device under test to output a first level, and the sending unit 501 is further configured to send a second instruction to the device under test, where the second instruction is used to instruct a general purpose input/output GPIO on the device under test to report first information, where the GPO is connected to the GPIO, and an output signal of the GPO is used as an input signal of the GPIO. A receiving unit 502, configured to receive first information reported by the device under test, where the first information includes a second level; a processing unit 503, configured to determine that the GPO function is normal when the first level is consistent with the second level. Optionally, the processing unit 503 is configured to determine that the GPO function is abnormal when the first level is not consistent with the second level. All relevant contents of each step related to the above method embodiment may be referred to the functional description of the corresponding functional module, and are not described herein again.

In other embodiments of the present application, embodiments of the present application disclose an apparatus, as shown in fig. 6, the apparatus 600 may include: one or more processors 601; a memory 602; a display 603; one or more application programs (not shown); and one or more computer programs 604, which may be connected via one or more communication buses 605. The device 600 may be a PC as described above. Wherein the one or more computer programs 604 are stored in the memory 602 and configured to be executed by the one or more processors 601, the one or more computer programs 604 comprising instructions.

Through the above description of the embodiments, it is clear to those skilled in the art that, for convenience and simplicity of description, the foregoing division of the functional modules is merely used as an example, and in practical applications, the above function distribution may be completed by different functional modules according to needs, that is, the internal structure of the device may be divided into different functional modules to complete all or part of the above described functions. For the specific working processes of the system, the apparatus and the unit described above, reference may be made to the corresponding processes in the foregoing method embodiments, and details are not described here again.

Each functional unit in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application may be essentially implemented or make a contribution to the prior art, or all or part of the technical solutions may be implemented in the form of a software product stored in a storage medium and including several instructions for causing a computer device (which may be a personal computer, a server, or a network device) or a processor to execute all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: flash memory, removable hard drive, read only memory, random access memory, magnetic or optical disk, and the like.

The above description is only a specific implementation of the embodiments of the present application, but the scope of the embodiments of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the embodiments of the present application should be covered by the scope of the embodiments of the present application. Therefore, the protection scope of the embodiments of the present application shall be subject to the protection scope of the claims.

Claims

1. A circuit board testing method is applied to a Personal Computer (PC), and is characterized by comprising the following steps:

sending a first instruction to a tested device, wherein the first instruction is used for controlling a general purpose output GPO on the tested device to output a first level;

sending a second instruction to the device to be tested, wherein the second instruction is used for instructing a general purpose input/output (GPIO) on the device to be tested to report first information, the GPO is connected with the GPIO, and an output signal of the GPO is used as an input signal of the GPIO;

receiving first information reported by the tested equipment, wherein the first information comprises a second level;

determining that the GPO is functioning properly when the first level is consistent with the second level.

2. The method of claim 1, further comprising:

determining that the GPO is malfunctioning when the first level is not consistent with the second level.

3. The method of claim 1, wherein the first level and the second level are both high levels;

before determining that the GPO is functioning properly, the method further comprises:

sending a third instruction to the tested device, wherein the third instruction is used for controlling a GPO on the tested device to output a low level;

sending a fourth instruction to the device to be tested, wherein the fourth instruction is used for instructing a GPIO on the device to be tested to report second information, the GPO is connected with the GPIO, and an output signal of the GPO is used as an input signal of the GPIO;

receiving second information reported by the tested equipment;

determining that the GPO is functioning properly, including:

determining that the GPO is functioning properly when the first level is consistent with the second level and when the second information comprises a low level.

4. The method according to any one of claims 1 to 3, wherein the GPIO and the GPO are connected in pairs by tool thimbles.

5. The method according to any one of claims 1 to 3, wherein the upper computer and the device under test are connected through a data line.

6. A circuit board testing apparatus, the apparatus comprising:

the device comprises a sending unit, a receiving unit and a processing unit, wherein the sending unit is used for sending a first instruction to a tested device, and the first instruction is used for controlling a general purpose output GPO on the tested device to output a first level;

the sending unit is configured to send a second instruction to the device under test, where the second instruction is used to instruct a general purpose input/output (GPIO) on the device under test to report first information, the GPO is connected to the GPIO, and an output signal of the GPO is used as an input signal of the GPIO;

the receiving unit is used for receiving first information reported by the tested equipment, and the first information comprises a second level;

and the processing unit is used for determining that the GPO is normal when the first level is consistent with the second level.

7. The apparatus of claim 6, wherein the processing unit is further configured to:

8. The apparatus of claim 6, wherein the first level and the second level are both high;

the sending unit is further configured to send a third instruction to the device under test, where the third instruction is used to control a GPO on the device under test to output a low level; sending a fourth instruction to the device to be tested, wherein the fourth instruction is used for instructing a GPIO on the device to be tested to report second information, the GPO is connected with the GPIO, and an output signal of the GPO is used as an input signal of the GPIO;

the receiving unit is further configured to receive second information reported by the device under test;

the processing unit is specifically configured to: determining that the GPO is functioning properly when the first level is consistent with the second level and when the second information comprises a low level.

9. The device as claimed in any one of claims 5 to 8, wherein said one GPIO and said one GPO are connected two by a jig thimble.

10. The device according to any one of claims 5 to 8, wherein the upper computer and the device under test are connected through a data line.

11. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the method of any one of claims 1 to 5.