CN113345836A - TSV electroplating process - Google Patents
TSV electroplating process Download PDFInfo
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- CN113345836A CN113345836A CN202110607718.7A CN202110607718A CN113345836A CN 113345836 A CN113345836 A CN 113345836A CN 202110607718 A CN202110607718 A CN 202110607718A CN 113345836 A CN113345836 A CN 113345836A
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- tsv
- silicon wafer
- passivation layer
- copper
- tsv hole
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- 238000000034 method Methods 0.000 title claims abstract description 42
- 238000009713 electroplating Methods 0.000 title claims abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 49
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 49
- 239000010703 silicon Substances 0.000 claims abstract description 49
- 238000002161 passivation Methods 0.000 claims abstract description 36
- 229910052802 copper Inorganic materials 0.000 claims abstract description 33
- 239000010949 copper Substances 0.000 claims abstract description 33
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 27
- 238000005530 etching Methods 0.000 claims abstract description 13
- 230000003647 oxidation Effects 0.000 claims abstract description 11
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 11
- 238000004381 surface treatment Methods 0.000 claims abstract description 10
- 230000000737 periodic effect Effects 0.000 claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 230000000694 effects Effects 0.000 claims abstract description 5
- 239000000463 material Substances 0.000 claims abstract description 5
- 239000002253 acid Substances 0.000 claims abstract description 4
- 230000007797 corrosion Effects 0.000 claims abstract description 4
- 238000005260 corrosion Methods 0.000 claims abstract description 4
- 238000009499 grossing Methods 0.000 claims abstract description 4
- 238000004519 manufacturing process Methods 0.000 claims abstract description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 238000000280 densification Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000007747 plating Methods 0.000 claims 6
- 238000010586 diagram Methods 0.000 description 4
- 239000002904 solvent Substances 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000009623 Bosch process Methods 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052716 thallium Inorganic materials 0.000 description 1
- BKVIYDNLLOSFOA-UHFFFAOYSA-N thallium Chemical compound [Tl] BKVIYDNLLOSFOA-UHFFFAOYSA-N 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
Images
Classifications
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/12—Semiconductors
- C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D3/00—Electroplating: Baths therefor
- C25D3/02—Electroplating: Baths therefor from solutions
- C25D3/38—Electroplating: Baths therefor from solutions of copper
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/48—After-treatment of electroplated surfaces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
Abstract
The invention provides a TSV electroplating process, which comprises the following steps: step S1, etching a TSV hole on the surface of the silicon wafer through a Bosch etching process, wherein a periodic step undulating pattern is formed on the side wall of the TSV hole; then forming a first passivation layer on the inner wall of the TSV hole and the surface of the silicon wafer through a thermal oxidation process; step S2, carrying out surface treatment on the silicon wafer by using acid with a corrosion effect, removing a first passivation layer material formed on the surface of the silicon wafer and on the inner wall of the TSV hole, and simultaneously smoothing the surface of the silicon wafer and the side wall of the TSV hole; step S3, manufacturing a second passivation layer on the surface of the silicon wafer and the inner wall of the TSV hole, and depositing a seed layer on the second passivation layer; step S4, electroplating copper on the surface of the silicon wafer to fill the TSV hole with the copper metal; and removing the copper on the surface of the silicon wafer by using a copper CMP process, and leaving the copper filled in the TSV hole to form the TSV conductive column. The invention can avoid the stepped fluctuation pattern on the inner wall of the TSV hole.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a TSV electroplating process.
Background
The TSV structure is a main structure for performing a vertical interconnection function in future three-dimensional packaging, and the main implementation process of the TSV structure comprises the processes of dry etching of a Bosch process, passivation layer deposition, seed layer covering, non-porous electroplating of TSV and the like. The Bosch etching process is completed through the steps of periodic etching and protection, a periodic shell-shaped pattern is formed on the side wall of the TSV, the formed outline can cause that a follow-up passivation layer, whether PECVD, ALD or thermal oxidation process is deposited, also presents a periodic step fluctuation shape, a seed layer metal exists in an area where the passivation layer steps upwards, and no seed layer metal exists in an area where the steps downwards, so that the seed layer is discontinuous, and the following TSV electroplating effect is influenced.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, and provides a TSV electroplating process which can avoid a step fluctuation pattern on the inner wall of a TSV hole and is beneficial to subsequent seed layer covering and TSV electroplating processes. In order to achieve the technical purpose, the embodiment of the invention adopts the technical scheme that:
in a first aspect, an embodiment of the present invention provides a TSV electroplating process, including:
step S1, etching a TSV hole on the surface of the silicon wafer through a Bosch etching process, wherein a periodic step undulating pattern is formed on the side wall of the TSV hole; then forming a first passivation layer on the inner wall of the TSV hole and the surface of the silicon wafer through a thermal oxidation process;
step S2, carrying out surface treatment on the silicon wafer by using acid with a corrosion effect, removing a first passivation layer material formed on the surface of the silicon wafer and on the inner wall of the TSV hole, and simultaneously smoothing the surface of the silicon wafer and the side wall of the TSV hole;
step S3, manufacturing a second passivation layer on the surface of the silicon wafer and the inner wall of the TSV hole, and depositing a seed layer on the second passivation layer;
step S4, electroplating copper on the surface of the silicon wafer to fill the TSV hole with the copper metal; and removing the copper on the surface of the silicon wafer by using a copper CMP process, and leaving the copper filled in the TSV hole to form the TSV conductive column.
Further, in step S1, the diameter of the TSV hole is in the range of 1 μm to 1000 μm, and the depth is in the range of 10 μm to 1000 μm; the thickness range of the first passivation layer is 10 nm-100 mu m.
Further, in step S2, the silicon wafer is subjected to a surface treatment with hydrofluoric acid.
Further, in step S2, the temperature during the surface treatment is 35 to 40 ℃, and the hydrofluoric acid concentration is 35 to 40%.
Further, in step S3, a second passivation layer is formed by depositing silicon oxide or silicon nitride on the surface of the silicon wafer and the inner wall of the TSV hole, or by direct thermal oxidation.
Further, the second passivation layer has a thickness ranging from 10nm to 100 μm.
Further, in step S4, after the TSV holes are filled with copper metal, densification is performed at 200 to 500 degrees to make the copper denser.
The technical scheme provided by the embodiment of the invention has the following beneficial effects: according to the process provided by the embodiment of the invention, a first passivation layer is formed on the inner wall of the TSV hole by using a thermal oxidation process, then the first passivation layer diffuses into silicon to form a smooth interface, and after silicon oxide is removed by using a wet process, the smooth silicon side wall of the TSV hole is obtained. And a second passivation layer is formed by PECVD, ALD or thermal oxidation process subsequently, so that a periodic step fluctuation pattern can be avoided, and the subsequent seed layer covering and TSV electroplating process are facilitated.
Drawings
Fig. 1 is a schematic diagram of etching a TSV hole by a bosch etching process in the embodiment of the present invention.
Fig. 2 is a schematic diagram illustrating a first passivation layer manufactured in the embodiment of the invention.
Fig. 3 is a schematic diagram illustrating a second passivation layer fabricated in an embodiment of the invention.
FIG. 4 is a schematic view of a deposited seed layer in an embodiment of the invention.
FIG. 5 is a schematic diagram of the electroplated copper and copper CMP processes of an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In a first aspect, an embodiment of the present invention provides a TSV electroplating process, including:
step S1, etching a TSV hole on the surface of the silicon wafer through a Bosch etching process, wherein a periodic step undulating pattern is formed on the side wall of the TSV hole; then forming a first passivation layer on the inner wall of the TSV hole and the surface of the silicon wafer through a thermal oxidation process; in particular, the amount of the solvent to be used,
as shown in fig. 1, first, a TSV hole 102 is etched on a surface of a silicon wafer 101 by a conventional bosch etching process, and a periodic step-and-valley pattern 103 is formed on a sidewall of the TSV hole 102;
the diameter range of the TSV hole 102 is 1-1000 mu m, and the depth is 10-1000 mu m;
as shown in fig. 2, the silicon wafer 101 is directly thermally oxidized, and a first passivation layer 104 is formed on the inner wall of the TSV hole 102 and the surface of the silicon wafer 101 through a thermal oxidation process; the thickness range of the first passivation layer 104 is 10 nm-100 μm;
step S2, carrying out surface treatment on the silicon wafer by using acid with a corrosion effect, removing a first passivation layer material formed on the surface of the silicon wafer and on the inner wall of the TSV hole, and simultaneously smoothing the surface of the silicon wafer and the side wall of the TSV hole; in particular, the amount of the solvent to be used,
performing surface treatment on the silicon wafer 101 by using hydrofluoric acid, and corroding and removing silicon oxide serving as a first passivation layer material formed on the surface of the silicon wafer 101 and on the inner wall of the TSV hole 102; meanwhile, the surface of the silicon wafer and the side wall of the TSV hole can be smooth;
in the step, the temperature of the silicon wafer 101 subjected to surface treatment by hydrofluoric acid is 35-40 ℃, and the concentration of the hydrofluoric acid is 35-40%;
step S3, manufacturing a second passivation layer on the surface of the silicon wafer and the inner wall of the TSV hole, and depositing a seed layer on the second passivation layer; in particular, the amount of the solvent to be used,
as shown in fig. 3, after the surface of the silicon wafer and the sidewalls of the TSV holes become smooth, silicon oxide or silicon nitride may be deposited on the surface of the silicon wafer 101 and the inner walls of the TSV holes 102, or a second passivation layer 104' may be formed by direct thermal oxidation; the thickness range of the second passivation layer 104' is 10 nm-100 μm;
as shown in fig. 4, a seed layer 105 is then deposited on the second passivation layer 104' by a physical sputtering, magnetron sputtering or evaporation process; the thickness of the seed layer 105 ranges from 1nm to 100 μm, and the seed layer may be one layer or multiple layers, and the metal material may be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel, etc.;
step S4, electroplating copper on the surface of the silicon wafer to fill the TSV hole with the copper metal; removing copper on the surface of the silicon wafer by a copper CMP process, and leaving copper filled in the TSV hole to form a TSV conductive column; in particular, the amount of the solvent to be used,
as shown in fig. 5, copper 106 is electroplated on the surface of the silicon wafer 101 to fill the TSV hole 102 with copper, and densification is performed at a temperature of 200 to 500 ℃ to make the copper denser;
the copper CMP process removes copper on the surface of the silicon wafer 101, leaves copper filled in the TSV hole 102, and forms a TSV conductive column.
Finally, it should be noted that the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting, and although the present invention has been described in detail with reference to examples, it should be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, which should be covered by the claims of the present invention.
Claims (7)
1. A TSV electroplating process is characterized by comprising the following steps:
step S1, etching a TSV hole on the surface of the silicon wafer through a Bosch etching process, wherein a periodic step undulating pattern is formed on the side wall of the TSV hole; then forming a first passivation layer on the inner wall of the TSV hole and the surface of the silicon wafer through a thermal oxidation process;
step S2, carrying out surface treatment on the silicon wafer by using acid with a corrosion effect, removing a first passivation layer material formed on the surface of the silicon wafer and on the inner wall of the TSV hole, and simultaneously smoothing the surface of the silicon wafer and the side wall of the TSV hole;
step S3, manufacturing a second passivation layer on the surface of the silicon wafer and the inner wall of the TSV hole, and depositing a seed layer on the second passivation layer;
step S4, electroplating copper on the surface of the silicon wafer to fill the TSV hole with the copper metal; and removing the copper on the surface of the silicon wafer by using a copper CMP process, and leaving the copper filled in the TSV hole to form the TSV conductive column.
2. The TSV plating process of claim 1,
in step S1, the diameter of the formed TSV hole ranges from 1 μm to 1000 μm, and the depth ranges from 10 μm to 1000 μm; the thickness range of the first passivation layer is 10 nm-100 mu m.
3. The TSV plating process of claim 1,
in step S2, the silicon wafer is subjected to surface treatment with hydrofluoric acid.
4. The TSV plating process of claim 3,
in step S2, the temperature during surface treatment is 35-40 ℃, and the concentration of hydrofluoric acid is 35-40%.
5. The TSV plating process of claim 1,
in step S3, a second passivation layer is formed by depositing silicon oxide or silicon nitride on the surface of the silicon wafer and the inner wall of the TSV hole, or by direct thermal oxidation.
6. The TSV plating process of claim 5,
the thickness range of the second passivation layer is 10 nm-100 mu m.
7. The TSV plating process of claim 1,
in step S4, after the TSV holes are filled with copper metal, densification is performed at 200 to 500 degrees to make the copper denser.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110607718.7A CN113345836A (en) | 2021-06-01 | 2021-06-01 | TSV electroplating process |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110607718.7A CN113345836A (en) | 2021-06-01 | 2021-06-01 | TSV electroplating process |
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Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102315157A (en) * | 2010-08-11 | 2012-01-11 | 上海集成电路研发中心有限公司 | Method for forming and correcting TSV (through silicon via) |
| US20120083128A1 (en) * | 2010-10-05 | 2012-04-05 | National Taiwan University Of Science And Technology | Method for etching high-aspect-ratio features |
| CN103715131A (en) * | 2012-09-29 | 2014-04-09 | 中国航天科技集团公司第九研究院第七七一研究所 | High depth width ratio TSV through hole step-by-step etching and side wall modification method |
| CN103794554A (en) * | 2014-02-27 | 2014-05-14 | 华进半导体封装先导技术研发中心有限公司 | Improved preparation method of through silicon via structure |
| CN103811416A (en) * | 2014-02-27 | 2014-05-21 | 华进半导体封装先导技术研发中心有限公司 | Method for flattening sidewall of through silicon via |
| CN104282619A (en) * | 2013-07-03 | 2015-01-14 | 中芯国际集成电路制造(上海)有限公司 | Silicon through hole forming method |
| CN104835776A (en) * | 2014-02-08 | 2015-08-12 | 中芯国际集成电路制造(上海)有限公司 | TSV blind hole manufacturing method |
| CN110010546A (en) * | 2018-12-25 | 2019-07-12 | 杭州臻镭微波技术有限公司 | It is a kind of to erect the manufacture craft for placing the phase change radiator structure of radio-frequency module |
| CN111293079A (en) * | 2020-03-17 | 2020-06-16 | 浙江大学 | Manufacturing method of super-thick adapter plate |
| CN111952196A (en) * | 2020-08-24 | 2020-11-17 | 浙江集迈科微电子有限公司 | Groove chip embedding process |
| CN111952243A (en) * | 2020-08-24 | 2020-11-17 | 浙江集迈科微电子有限公司 | Groove chip embedding process |
-
2021
- 2021-06-01 CN CN202110607718.7A patent/CN113345836A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102315157A (en) * | 2010-08-11 | 2012-01-11 | 上海集成电路研发中心有限公司 | Method for forming and correcting TSV (through silicon via) |
| US20120083128A1 (en) * | 2010-10-05 | 2012-04-05 | National Taiwan University Of Science And Technology | Method for etching high-aspect-ratio features |
| CN103715131A (en) * | 2012-09-29 | 2014-04-09 | 中国航天科技集团公司第九研究院第七七一研究所 | High depth width ratio TSV through hole step-by-step etching and side wall modification method |
| CN104282619A (en) * | 2013-07-03 | 2015-01-14 | 中芯国际集成电路制造(上海)有限公司 | Silicon through hole forming method |
| CN104835776A (en) * | 2014-02-08 | 2015-08-12 | 中芯国际集成电路制造(上海)有限公司 | TSV blind hole manufacturing method |
| CN103794554A (en) * | 2014-02-27 | 2014-05-14 | 华进半导体封装先导技术研发中心有限公司 | Improved preparation method of through silicon via structure |
| CN103811416A (en) * | 2014-02-27 | 2014-05-21 | 华进半导体封装先导技术研发中心有限公司 | Method for flattening sidewall of through silicon via |
| CN110010546A (en) * | 2018-12-25 | 2019-07-12 | 杭州臻镭微波技术有限公司 | It is a kind of to erect the manufacture craft for placing the phase change radiator structure of radio-frequency module |
| CN111293079A (en) * | 2020-03-17 | 2020-06-16 | 浙江大学 | Manufacturing method of super-thick adapter plate |
| CN111952196A (en) * | 2020-08-24 | 2020-11-17 | 浙江集迈科微电子有限公司 | Groove chip embedding process |
| CN111952243A (en) * | 2020-08-24 | 2020-11-17 | 浙江集迈科微电子有限公司 | Groove chip embedding process |
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