CN104282619A - Silicon through hole forming method - Google Patents
Silicon through hole forming method Download PDFInfo
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- CN104282619A CN104282619A CN201310277620.5A CN201310277620A CN104282619A CN 104282619 A CN104282619 A CN 104282619A CN 201310277620 A CN201310277620 A CN 201310277620A CN 104282619 A CN104282619 A CN 104282619A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
Abstract
The invention provides a silicon through hole forming method. The silicon through hole forming method comprises the steps that a silicon substrate is provided; a through hole is formed in the silicon substrate through deep reactivity ion etching; a thermal oxidation layer is formed on the side wall of the through hole; the thermal oxidation layer is removed; insulation layers are formed on the side wall and the bottom of the through hole; conductive materials are formed on the insulation layers so that the through hole can be filled. According to the silicon through hole forming method, after the through hole is formed, the growth and removal processing of the thermal oxidation layer is conducted on the side wall of the through hole, a scallop-shaped protrusion on the side wall of the through hole is removed, and the through hole with the flat and smooth surface is obtained; thus, the subsequent insulation materials can be well deposited on the surface of the through hole to form the insulation layer uniform in thickness, the conductive materials in the silicon through hole can be well injected in the through hole, good electric insulation can be maintained between the conductive materials and the silicon substrate, the finally-formed silicon through hole can have the insulation performance with high breakdown voltage and without leakage or cracking, and the effective rate of a silicon through hole chip is improved.
Description
Technical field
The present invention relates to field of semiconductor technology, particularly relate to a kind of formation method of silicon through hole.
Background technology
At semiconductor applications, the tight demand of high speed, high density, small size and multifunction electronic device is driven and creates three dimension system encapsulation (3D-SiP) technology.Silicon through hole (TSV) interconnection due to have shorter interconnection distance and faster speed become a kind of important form of three dimension system encapsulation technology.Multi-chip module gathers into folds along chip thickness direction by silicon through hole, thus greatly reduces chip thickness, and has the minimized advantage of coefficient making the thermal expansion between tube core and interpolater (CTE) mismatch.
In silicon via process, relate to multiple step, comprise through hole formation, lateral wall insulation and filling through hole etc.At present, through hole forms the general method realization adopting deep reactive ion etch.But it is protruding that this method can make through-hole side wall produce scallop (scallop) shape usually.When these scallop shape projections can cause deposition insulating layer in lateral wall insulation step, insulating barrier covers bad to through-hole side wall, thus finally causes producing between silicon through hole and silicon substrate leaking electricity.Although by the thickness of insulating barrier when the etching condition of adjustment deep reactive ion etch or increase lateral wall insulation, can optimize between silicon through hole and substrate and leak electricity.But the etching condition of adjustment deep reactive ion etch still cannot avoid the formation of scallop shape projection.And the thickness increasing insulating barrier is when can make follow-up filling through hole, process window diminishes, and causes hole conductive material when filling vias, and filling effect is bad, and causes the poor performance of silicon through hole, finally causes chip easily to lose efficacy.Thus, the through-hole side wall how obtaining flat smooth is a bottleneck in silicon via process.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of silicon through hole, to obtain the silicon through hole of through-hole side wall flat smooth.
For solving the problem, the invention provides a kind of formation method of silicon through hole, comprising:
Silicon substrate is provided;
Dark reactive ion etching is adopted to form through hole in described silicon substrate;
Thermal oxide layer is formed at the sidewall of described through hole;
Remove described thermal oxide layer;
At sidewall and the bottom formation insulating barrier of described through hole;
Described insulating barrier forms electric conducting material to fill completely described through hole.
Optionally, furnace process is adopted to form described thermal oxide layer at the sidewall of described through hole and bottom.
Optionally, described furnace process is normal pressure furnace process, and described furnace process adopts dry-oxygen oxidation or wet-oxygen oxidation, and temperature range comprises 750 degrees Celsius ~ 1150 degrees Celsius, and the thickness of the thermal oxide layer that described furnace process generates is 500 dust ~ 1500 dusts.
Optionally, hydrofluoric acid clean is adopted to remove described thermal oxide layer.
Optionally, in described hydrofluoric acid, the mol ratio of hydrogen fluoride and water is 1:10 ~ 1:50, and the described hydrofluoric acid clean time is 5 minutes ~ 15 minutes.
Optionally, described formation method also comprises: after the described through hole of formation and before the described insulating barrier of formation, repeats one or many and forms described thermal oxide layer at the sidewall of described through hole and remove the step of described thermal oxide layer.
Optionally, after the described thermal oxide layer of removal, also comprise: adopt isopropyl alcohol to clean described through hole, and carry out drying.
Optionally, chemical vapour deposition technique insulating barrier described in the sidewall of described through hole and bottom deposit is adopted.
Optionally, at the described electric conducting material of formation with before filling completely described through hole, also comprise: form diffusion impervious layer at described surface of insulating layer.
Optionally, the material of described diffusion impervious layer is tantalum nitride, tantalum or their combination.
Optionally, described electric conducting material is copper, adopts galvanoplastic to form described electric conducting material.
Optionally, when the sidewall of described through hole forms described thermal oxide layer, described thermal oxide layer is formed in the bottom of described through hole simultaneously; Remove described thermal oxide layer to comprise: remove and be positioned at the sidewall of described through hole and the thermal oxide layer of bottom.
Compared with prior art, technical scheme of the present invention has the following advantages:
In the formation method of silicon through hole provided by the present invention, after through hole is formed, the sidewall of through hole is carried out to growth and the Transformatin of thermal oxide layer, the growth course of thermal oxide layer can make the scallop shape of through-hole side wall projection be oxidized to a part for thermal oxide layer, thus the Transformatin of thermal oxide layer can eliminate the scallop shape projection of through-hole side wall, reduce the roughness of through-hole side wall, thus obtain the through hole of surperficial flat-satin, therefore insulating material can be deposited on through-hole surfaces well and form the uniform insulating barrier of thickness, thus the filling effect of electric conducting material can either be made better, can prevent from again leaking electricity between electric conducting material and silicon substrate, the silicon through hole formed finally is made to have high-breakdown-voltage, No leakage and the insulation property without cracking, reduce the failure rate of silicon through hole chip.
Further, after the described through hole of formation and before the described insulating barrier of formation, repeat one or many to form described thermal oxide layer at the sidewall of described through hole and remove the step of described thermal oxide layer, the roughness reducing described through-hole surfaces can be continued, thus make through-hole surfaces flat-satin more.
Accompanying drawing explanation
The schematic diagram of formation method of Fig. 1 to Figure 10 for being the silicon through hole that the embodiment of the present invention provides.
Embodiment
In the formation method of existing silicon through hole, the sidewall surfaces of the through hole formed is uneven, has scallop shape protruding, easily causes the insulating barrier local complexity be positioned on through hole bad.And insulating barrier local complexity not good general cause silicon through hole operationally local field strength be excessively strong, and then cause insulating barrier easily breakdown, thus make silicon through hole leakage current excessive, cause chip failure.When even more serious, the uneven sidewall making insulating barrier cannot cover through hole completely of the sidewall of the through hole formed, causes the electric conducting material in silicon through hole and silicon substrate direct short-circuit, makes silicon through hole leakage current excessive equally, cause chip failure.
In addition, also easily there is streak shape defect in the bottom of the through hole formed, and there is the prerequisite of scallop shape projection at the sidewall of through hole under, these streak shape defects may cause insulating barrier easily breakdown further, cause chip failure.
The invention provides a kind of formation method of silicon through hole, after the via is formed, directly do not carry out the step forming insulating barrier, but thermal oxidation is carried out to through hole, thermal oxide layer is formed with the sidewall at through hole, then described thermal oxide layer is removed, scallop shape projection is oxidized to a part for thermal oxide layer in this process, by removing described thermal oxide layer, described scallop shape projection is also eliminated, thus make the sidewall of through hole become smooth planar, ensure that follow-up insulating barrier can cover on the sidewall of through hole preferably, thus electric conducting material is filled in through-holes preferably, electric conducting material and silicon substrate not easily leak electricity simultaneously, final raising silicon through hole chip efficient.
Further, when the sidewall of through hole forms thermal oxide layer, described thermal oxide layer is formed in the bottom of through hole simultaneously, namely now the streak shape defect of via bottoms also can be thermally oxidized into a part for thermal oxide layer, and along with the removal of thermal oxide layer, described streak shape defect is also eliminated, therefore thereupon, further increase the insulation property of insulating barrier, improve the efficient of silicon through hole chip further.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
The present embodiment provides a kind of formation method of silicon through hole, please refer to Fig. 1 to Figure 10.
Please refer to Fig. 1, first silicon substrate 100 is provided.
Although do not give display in Fig. 1, but silicon substrate that the present embodiment provides 100 can have the devices (device) such as transistor, diode, memory, inductance, electric capacity or resistance, one deck or multilayer dielectricity layer of covering these devices can also be had, and the metal interconnect structure of the compositions such as metal plug, plain conductor or metal pins can also be had between described device and described dielectric layer.
Please continue to refer to Fig. 1, described silicon substrate 100 forms the photoresist oxidant layer 200 of patterning.
The present embodiment can utilize photoetching technique well known in the art to carry out patterning photoresist oxidant layer 200, specifically comprise deposition photo anti-corrosion agent material, according to the patterned illumination photo anti-corrosion agent material of mask, then development removes a part of photo anti-corrosion agent material, obtains the photoresist oxidant layer 200 of patterning.
Incorporated by reference to referring to figs. 2 to Fig. 5, dark reactive ion etching is adopted to form through hole 130 in described silicon substrate 100.
Dark reactive ion etching comprises the dark reactive ion etching of Bosch (Bosch Deep Reactive Ion Etching; Bosch DRIE) and low temperature moldeed depth reactive ion etching (Cryogenic DRIE).The present embodiment uses Bosch dark reactive ion etching the forming process of through hole 130 to be described for example, the etching process of low temperature moldeed depth reactive ion etching and the etching process of the dark reactive ion etching of Bosch similar, do not repeat them here.
The concrete etching process of Bosch DRIE specifically comprises: first please refer to Fig. 2, introduces SF
6as the first gas (not shown), etch for mask with photoresist oxidant layer 200 to silicon substrate 100, this step is SF
6anisotropic etching effect, during longitudinal etch silicon substrate 100, first gas etch silicon substrate 100 to the first degree of depth, stop the first gas, now in silicon substrate 100, form the first groove 110a.After stopping first gas, introduce the second gas (not shown) rapidly, the present embodiment second gas selects C
4f
8, C
4f
8polymer linner can be formed to protect the surface of groove on the surface of the first groove 110a.As shown in Figure 3, the second gas forms the first polymer linner 111 on the surface of the first groove 110a, makes the first groove 110a be converted into the first groove 110b.After forming the first polymer linner 111 as shown in Figure 3, again introduce the first gas, the etching action of the first gas still retains the first polymer linner 111 being positioned at the first groove 110b sidewall, but etching removes in Fig. 3 the first polymer linner 111 be positioned at bottom the first groove 110b, and the bottom etching silicon substrate 100 continued along the first groove 110b, form the second groove 120a, as shown in Figure 4.After this, although do not illustrate, continue introducing second gas, to form the second polymer linner (not shown) on the second groove 120a surface.Like this, above-mentioned steps (i.e. rapid translating introduce the first gas carry out etching and introduce the processing step that the second gas carries out protecting) is constantly repeated, until obtain the through hole 130 of desired depth, as shown in Figure 5.After formation through hole 130, the photoresist oxidant layer 200 in Fig. 4 can be removed.
Can etch by above-mentioned Bosch DRIE the through hole 130 that through hole depth-to-width ratio (ratio of hole depth and bore dia width) is greater than more than 10, the degree of depth of through hole 130 can be greater than 50um usually.Simultaneously, from above description, the etching mode of Bosch DRIE determines that the sidewall of the through hole 130 formed is bound to produce scallop shape (scallop) protruding (non-label), and through measuring, now the sidewall roughness of through hole 130 is usually right at 500 dust ~ 1500 Izods.In addition, now also can there is streak shape defect (not shown) in the bottom of through hole 130, and due to the existence of streak shape defect, the roughness bottom through hole 130 is usually also right at 500 dust ~ 1500 Izods.
Because the technical process of Cryogenic DRIE and Bosch DRIE is similar, therefore, it is protruding that the through hole obtained by Cryogenic DRIE can produce scallop shape at sidewall equally, and produce streak shape defect in bottom, detailed process the present invention do not repeat them here.
Please refer to Fig. 6, after formation through hole 130, next the present embodiment forms thermal oxide layer 140 at the sidewall of through hole 130 and bottom.
The present embodiment adopts furnace process to form thermal oxide layer 140 at the sidewall of described through hole 130 and bottom.Described boiler tube can be rectilinear boiler tube, and described furnace process can be atmospheric pressure kiln plumber skill, and described furnace process can adopt dry-oxygen oxidation or wet-oxygen oxidation.In dry-oxygen oxidation process, make the sidewall of through hole 130 and bottom form thermal oxide layer 140 by passing into pure oxygen as oxide, and the mixture that wet-oxygen oxidation passes into water and oxygen make the sidewall of through hole 130 and bottom form thermal oxide layer 140 as oxide.
Because thermal oxide layer 140 is formed in silicon substrate 100, therefore its composition is silicon dioxide (SiO
2).In oxidizing process, oxidation rate is accelerated along with the rising of temperature, but the too high device that may cause containing in silicon substrate 100 of temperature is destroyed, the too low oxidation efficiency that can affect again of temperature even cannot realize oxidizing process, therefore temperature range controls at 750 degrees Celsius ~ 1150 degrees Celsius, and actual temp can be chosen as: 750 degrees Celsius, 800 degrees Celsius, 900 degrees Celsius, 1000 degrees Celsius, 1100 degrees Celsius or 1150 degrees Celsius.Because the sidewall roughness of through hole 130 is right at 500 dust ~ 1500 Izods; for making scallop shape projection oxidized as far as possible; the present embodiment controls the thickness range of the thermal oxide layer 140 generated at 500 dust ~ 1500 dusts, can be specifically 500 dusts, 600 dusts, 700 dusts, 800 dusts, 900 dusts, 1000 dusts, 1200 dusts or 1500 dusts etc. according to the thickness of the sidewall roughness control thermal oxide layer 140 of through hole 130.Specifically thermal oxidation time can be regulated according to factors such as the thickness of temperature, oxide concentration and thermal oxide layer 140.
In the thermal oxide layer 140 that the present embodiment is formed, the thermal oxide layer 140 of the protruding position of scallop shape is thicker.This is because the local specific area of scallop shape projection is large, large with the contact-making surface of oxygen, therefore the oxidation rate of scallop shape projection is fast.In addition, scallop shape convex curvature is larger, scallop shape projection is made to have higher surface energy (superficial layer atomic ratio interior atoms has more part energy), therefore scallop shape is protruding is more prone to oxygen reaction and enlivens, accelerate the oxidation rate of scallop shape projection further, finally make at the thermal oxide layer 140 of scallop shape raised position formation thicker.
It should be noted that, in other embodiments of the invention, only can form thermal oxide layer at the sidewall of through hole, now can eliminate scallop shape protruding, realize the smooth of through-hole side wall.
Please refer to Fig. 7, remove thermal oxide layer 140 as shown in Figure 6, obtain through hole 150a.
Composition due to thermal oxide layer 140 is silicon dioxide, and the character of silicon dioxide is extremely stable, and therefore, thermal oxide layer 140 is removed in the hydrofluoric acid (not shown) cleaning that the present embodiment adopts corrosivity extremely strong.Cleaning process can be carried out at normal temperatures, hydrogen fluoride (HF) and water (H in described hydrofluoric acid
2o) molar ratio range can at 1:10 ~ 1:50, such as 1:10,1:20,1:30,1:40 or 1:50, and scavenging period can be 5 minutes ~ 15 minutes.
It should be noted that, the present embodiment only utilizes the formation of a thermal oxide layer and removal step to eliminate the scallop shape projection of through-hole side wall.But, in other embodiments of the invention, can by repeatedly repeating to form thermal oxide layer at the sidewall of through hole and remove the step of thermal oxide layer, with the thickness making the thickness of thermal oxide layer be more than or equal to scallop shape projection, and make through-hole surfaces flat-satin more by removing described thermal oxide layer, and then advantageously cover through-hole surfaces equably with follow-up insulating barrier.
After use hydrofluoric acid clean removes thermal oxide layer 140, the present embodiment can adopt isopropyl alcohol to clean through hole 150a, and carries out drying.Adopt isopropyl alcohol cleaning through hole 150a can remove residual hydrofluoric acid, and carry out drying and can remove isopropyl alcohol on the one hand, prevent isopropyl alcohol from having an impact to silicon through hole and silicon substrate, another aspect can accelerate corresponding processing step.
Comparison diagram 7 and Fig. 5 known, after the generation that have passed through thermal oxide layer 140 and removal step, the through hole 130 in Fig. 5 is transformed to through hole 150a, and the surperficial flat-satin of through hole 150a.Because through hole 130 surface in Fig. 5 has scallop shape projection, therefore through hole 130 sidewall roughness in Fig. 5 is usually right at 500 dust ~ 1500 Izods, and the through hole 150a in Fig. 7 is after the generation that have passed through thermal oxide layer 140 and removal step, its surface roughness is usually below 50 dusts.Therefore through hole 150a has the uniform deposition utilizing follow-up insulating barrier.
Comparison diagram 7 and Fig. 5 can also know, after the generation that have passed through thermal oxide layer 140 and removal step, in Fig. 7, the diameter of through hole 150a is greater than the diameter of through hole 130 in Fig. 5, and the filling of subsequent conductive material is more prone to.
It should be noted that, the streak shape defect existed bottom through hole 130 also can be eliminated by the formation of above-mentioned thermal oxide layer 140 and removal step, concrete, thermal oxide layer 140 can be formed in the bottom of through hole 130 simultaneously, that is the streak shape defect bottom through hole 130 also can be thermally oxidized into a part for thermal oxide layer 140, and described streak shape defect can be eliminated along with the removal of thermal oxide layer 140, thus the bottom of the through hole 150a formed is made also to become smooth planar.
Please refer to Fig. 8, insulating barrier 160 (Insulation Layer) is formed on the sidewall of through hole 150a and bottom in the figure 7, and insulating barrier 160 covers sidewall and the bottom of through hole 150a, makes through hole 150a become through hole 150b.
Insulating barrier 160 is for electrically isolated silicon substrate 100 and the follow-up electric conducting material be filled in through hole 150b.The material of insulating barrier 160 can be nitride (such as silicon nitride) or oxide, its thickness range can be 1000 dusts to 10000 dusts, to ensure that insulating barrier plays good insulating effect, ensure again that the diameter of follow-up through hole meets simultaneously and fill requirement.In the present embodiment, the material of insulating barrier 160 is silica.The method forming insulating barrier 160 can be aumospheric pressure cvd (AP-CVD) method, plasma enhanced chemical vapor deposition (PE-CVD) method, low-pressure chemical vapor deposition (LP-CVD) method or furnace process method.The present embodiment adopts aumospheric pressure cvd method to form insulating barrier 160, aumospheric pressure cvd method has good filling capacity and higher deposition efficiency, formed insulating barrier 160 thickness can be made homogeneous and cover bottom and the sidewall of through hole 150a comprehensively, now through hole 150a is converted into through hole 150b.
Please refer to Fig. 9, form diffusion impervious layer 170 on described insulating barrier 160 surface, diffusion impervious layer 170 is formed in bottom through hole 150b and sidewall, makes through hole 150b be converted into through hole 150c.
Diffusion impervious layer 170 diffuses into silicon substrate 100 for preventing the follow-up electric conducting material be filled in through hole 150c.The material of the present embodiment diffusion impervious layer 170 can be tantalum nitride, tantalum or their combination, its thickness range can be 500 dusts to 3000 dusts, thus both guaranteed to play enough barrier effects, and be unlikely to again to affect other structure.Chemical vapour deposition technique, physical vaporous deposition or atomic layer deposition method can be adopted to form diffusion impervious layer 170.
It should be noted that, when the electric conducting material diffusivity of follow-up filling is not strong, or when insulating barrier 160 inherently has enough non-proliferation abilities, also diffusion impervious layer 170 can not be set.
Please refer to Figure 10, form the through hole 150c shown in electric conducting material 180 blank map 9.Electric conducting material 180 can be aluminium (Al), copper (Cu), tungsten (W) or molybdenum (Mo) etc.Wherein, copper has excellent conductive rate and good filling capacity, and the present embodiment adopts copper as electric conducting material 180, and adopts electro-coppering (Copper Electroplating) process filling through hole 150c.Electro-coppering can not only filling vias 150c preferably, and space (void) not easily appears in the electric conducting material 180 of filling.
The present embodiment is after above-mentioned steps, chemico-mechanical polishing can also be adopted to remove unnecessary electric conducting material 180, again chemico-mechanical polishing is carried out to the back side of silicon substrate 100, make silicon substrate 100 thinning, until expose electric conducting material 180 lower surface, and electric conducting material 180 can be utilized to be connected with the semiconductor device electricity on other chip by the semiconductor device be positioned on silicon substrate 100.
The present embodiment is in silicon forming process of through hole, after forming through hole 130 as shown in Figure 5, through hole 130 is carried out to growth and the Transformatin of thermal oxide layer 140, the scallop shape eliminating through hole 130 sidewall is protruding, obtain the through hole 150a of surperficial flat-satin as shown in Figure 7, therefore the through hole 150a surface that follow-up insulating material can be deposited on as shown in Figure 7 well forms the uniform insulating barrier 160 of thickness, and the electric conducting material 180 in silicon through hole can be filled in through hole 150c as shown in Figure 9 preferably, and can prevent from leaking electricity between electric conducting material 180 and silicon substrate 100, the silicon through hole formed finally is made to have high-breakdown-voltage, No leakage and the insulation property without cracking (cracking), improve the efficient of silicon through hole chip.
The present embodiment is in silicon forming process of through hole, after forming through hole 130 as shown in Figure 5, the streak shape defect existed bottom through hole 130, described streak shape defect also can be thermally oxidized into a part for thermal oxide layer 140, and described streak shape defect can be eliminated along with the removal of thermal oxide layer 140, thus make the bottom of the through hole 150a formed also become smooth planar, therefore follow-up insulating material can be deposited on the bottom of through hole 150a as shown in Figure 7 better, the insulation property of further raising insulating barrier 160, finally improve the efficient of silicon through hole chip further.
In addition, the present embodiment in the process forming silicon through hole, comparison diagram 7 and Fig. 5 known, after the generation that have passed through thermal oxide layer 140 and removal step, in Fig. 7, the diameter of through hole 150a is greater than the diameter of through hole 130 in Fig. 5, and the filling of electric conducting material 180 is more prone to.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (12)
1. a formation method for silicon through hole, is characterized in that, comprising:
Silicon substrate is provided;
Dark reactive ion etching is adopted to form through hole in described silicon substrate;
Thermal oxide layer is formed at the sidewall of described through hole;
Remove described thermal oxide layer;
At sidewall and the bottom formation insulating barrier of described through hole;
Described insulating barrier forms electric conducting material to fill completely described through hole.
2. form method as claimed in claim 1, it is characterized in that, adopt furnace process to form described thermal oxide layer at the sidewall of described through hole and bottom.
3. form method as claimed in claim 2, it is characterized in that, described furnace process is normal pressure furnace process, described furnace process adopts dry-oxygen oxidation or wet-oxygen oxidation, temperature range comprises 750 degrees Celsius ~ 1150 degrees Celsius, and the thickness of the thermal oxide layer that described furnace process generates is 500 dust ~ 1500 dusts.
4. form method as claimed in claim 1, it is characterized in that, adopt hydrofluoric acid clean to remove described thermal oxide layer.
5. form method as claimed in claim 4, it is characterized in that, in described hydrofluoric acid, the mol ratio of hydrogen fluoride and water is 1:10 ~ 1:50, and the described hydrofluoric acid clean time is 5 minutes ~ 15 minutes.
6. form method as claimed in claim 1, it is characterized in that, described formation method also comprises: after the described through hole of formation and before the described insulating barrier of formation, repeats one or many and forms described thermal oxide layer at the sidewall of described through hole and remove the step of described thermal oxide layer.
7. form method as claimed in claim 1, it is characterized in that, after the described thermal oxide layer of removal, also comprise: adopt isopropyl alcohol to clean described through hole, and carry out drying.
8. form method as claimed in claim 1, it is characterized in that, adopt chemical vapour deposition technique insulating barrier described in the sidewall of described through hole and bottom deposit.
9. form method as claimed in claim 1, it is characterized in that, at the described electric conducting material of formation with before filling completely described through hole, also comprise: form diffusion impervious layer at described surface of insulating layer.
10. form method as claimed in claim 9, it is characterized in that, the material of described diffusion impervious layer is tantalum nitride, tantalum or their combination.
11. form method as claimed in claim 1, it is characterized in that, described electric conducting material is copper, adopt galvanoplastic to form described electric conducting material.
12. form method as claimed in claim 1, it is characterized in that, when the sidewall of described through hole forms described thermal oxide layer, described thermal oxide layer is formed in the bottom of described through hole simultaneously; Remove described thermal oxide layer to comprise: remove and be positioned at the sidewall of described through hole and the thermal oxide layer of bottom.
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| CN101958244A (en) * | 2009-07-21 | 2011-01-26 | 中微半导体设备(上海)有限公司 | Deep reactive ion etching method and gas flow control device thereof |
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