CN113300694B - Ultra-wideband low-loss high-isolation radio frequency switch with fully differential structure - Google Patents

Ultra-wideband low-loss high-isolation radio frequency switch with fully differential structure Download PDF

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CN113300694B
CN113300694B CN202110614004.9A CN202110614004A CN113300694B CN 113300694 B CN113300694 B CN 113300694B CN 202110614004 A CN202110614004 A CN 202110614004A CN 113300694 B CN113300694 B CN 113300694B
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gate
transmission gate
cmos transmission
resistor
nmos transistor
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CN113300694A (en
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高志强
王蒙
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Harbin Institute of Technology
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Harbin Institute of Technology
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/689—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit

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Abstract

The invention discloses an ultra-wideband low-loss high-isolation fully differential structure radio frequency switch, which consists of four CMOS transmission GATEs, namely a first CMOS transmission GATE TR _ GATE1, a second CMOS transmission GATE TR _ GATE2, a third CMOS transmission GATE TR _ GATE3 and a fourth CMOS transmission GATE TR _ GATE4, wherein: the first CMOS transmission GATE TR _ GATE1 and the fourth CMOS transmission GATE TR _ GATE4 form a main transmission path, and the second CMOS transmission GATE TR _ GATE2 and the third CMOS transmission GATE TR _ GATE3 form a cross transmission path. The radio frequency switch of the invention realizes large working bandwidth, low insertion loss, high isolation, short conversion time, high linearity and strong power processing capability.

Description

Ultra-wideband low-loss high-isolation radio frequency switch with fully differential structure
Technical Field
The invention belongs to the field of electronic information, and relates to a differential structure radio frequency switch circuit with an ultra-wide working band, low loss and high isolation.
Background
With the continuous development of mobile communication, the demand of radio frequency Front End Modules (FEMs) is increasing continuously, and as the smart phone needs to receive radio frequency signals of more frequency bands, the number of radio frequency switches in the mobile intelligent terminal needs to be increased continuously to meet the demands for receiving and transmitting signals of different frequency bands, so that the switch meeting the radio frequency demand is the module with the largest demand in the radio frequency system module, and the performance of the switch directly determines the performance of the whole radio frequency transceiver. The indexes describing the performance of the radio frequency switch mainly comprise insertion loss, isolation, return loss and high linear power processing capacity.
Over the years, discrete devices such as PIN diodes and III-V MESFETs are mainly adopted in the radio frequency switch, and along with the development trend of integrated circuits and systems, the integrated radio frequency switch gradually becomes the mainstream. Today, the implementation of radio frequency integrated circuits by integrated circuit technology is widely used.
Disclosure of Invention
The invention provides an ultra-wideband low-loss high-isolation fully-differential structure radio frequency switch based on an integrated circuit process, the switch circuit can be used for integrated radio frequency switch devices in the field of electronic information, and a working frequency band has the advantages of ultra-wideband, very low insertion loss and very high isolation.
The purpose of the invention is realized by the following technical scheme:
a CMOS transmission gate comprising an NMOS transmission path and a PMOS transmission path, wherein:
the NMOS transmission path consists of a first NMOS transistor, a second NMOS transistor, a first NMOS transistor gate resistor Rgn1, a second NMOS transistor gate resistor Rgn2, a first substrate resistor Rbn1 and a second substrate resistor Rbn 2;
the PMOS transmission path consists of a first PMOS transistor, a second PMOS transistor, a first PMOS gate resistor Rgp1, a second PMOS gate resistor Rgp2, a first substrate resistor Rbp1 and a second substrate resistor Rbp 2;
an input end Vin of the CMOS transmission gate is connected with a source electrode of a first NMOS transistor, a drain electrode of the first NMOS transistor is connected with a drain electrode of a second NMOS transistor, one end of a gate resistor Rgn1 of the first NMOS transistor is connected with a gate electrode of the first NMOS transistor, the other end of a gate resistor Rgn1 of the first NMOS transistor is connected with one end of a gate resistor Rgn2 of the second NMOS transistor, a gate resistor Rgn1 of the first NMOS transistor and a gate resistor Rgn2 of the second NMOS transistor are commonly connected with a control voltage Vgn, the other end of a gate resistor Rgn2 of the second NMOS transistor is connected with a gate electrode of the second NMOS transistor, a substrate end of the first NMOS transistor is connected with one end of a substrate resistor Rbn1 of the first NMOS transistor, the other end of the substrate resistor Rbn1 of the first NMOS transistor is connected with GND, the substrate end of the second NMOS transistor is connected with one end of a substrate resistor Rbn2 of the second NMOS transistor, and the other end of the substrate resistor Rbn2 of the second NMOS transistor is connected with GND, the source of the second NMOS transistor is connected to the output terminal Vout of the transmission gate, so that the NMOS transmission path connection is completed;
an input end Vin of the CMOS transmission gate is connected with a source electrode of a first PMOS transistor, a drain electrode of the first PMOS transistor is connected with a drain electrode of a second PMOS transistor, one end of a gate resistor Rgp1 of the first PMOS transistor is connected with a gate electrode of the first PMOS transistor, the other end of a gate resistor Rgp1 of the first PMOS transistor is connected with one end of a gate resistor Rgp2 of the second PMOS transistor, the gate resistor Rgp1 of the first PMOS transistor and the gate resistor Rgp2 of the second PMOS transistor are commonly connected with a control voltage Vgp, the other end of a gate resistor Rgp2 of the second PMOS transistor is connected with a gate electrode of the second PMOS transistor, a substrate end of the first PMOS transistor is connected with one end of a substrate resistor Rbp1 of the first PMOS transistor, the other end of a substrate resistor Rbn1 of the first PMOS transistor is connected with a power supply end VDD, a substrate end of the second PMOS transistor is connected with one end of a substrate resistor Rbp2 of the second PMOS transistor, and the other end of a substrate resistor Rbp2 of the second PMOS transistor is connected with a power supply end VDD, the source of the second PMOS transistor is connected to the output terminal Vout of the transmission gate, so that the PMOS transmission path connection is completed;
and the drain electrode of the first NMOS transistor is connected with the drain electrode of the first PMOS transistor to form the whole CMOS transmission gate.
Compared with the traditional CMOS transmission gate, the CMOS transmission gate provided by the invention can effectively increase the isolation degree by using a mode of connecting two NMOS transistors in series. The CMOS transmission gate has six pins including an input pin Vin, an output pin Vout, a power supply pin VDD, a ground pin GND, an NMOS transmission path control pin Vgn, and a PMOS transmission path control pin Vgp. When the Vgn voltage is 1 and the Vgp voltage is 0, the transmission gate is turned on, and the Vout output signal is consistent with the Vin input signal. On the contrary, when the Vgn voltage is 0 and the Vgp voltage is 1, the transmission gate is closed, and the Vout does not output a signal, thereby realizing the controlled transmission of the signal.
An ultra-wideband low-loss high-isolation fully differential structure radio frequency switch is composed of four CMOS transmission GATEs, namely a first CMOS transmission GATE TR _ GATE1, a second CMOS transmission GATE TR _ GATE2, a third CMOS transmission GATE TR _ GATE3 and a fourth CMOS transmission GATE TR _ GATE4, wherein:
the first CMOS transmission GATE TR _ GATE1 and the fourth CMOS transmission GATE TR _ GATE4 form a main transmission path, and the second CMOS transmission GATE TR _ GATE2 and the third CMOS transmission GATE TR _ GATE3 form a cross transmission path;
the Vin end of the first CMOS transmission GATE TR _ GATE1 is connected with the Vin end of the second transmission GATE TR _ GATE2 to serve as a Vip pin of the fully differential switch; the Vout end of the first CMOS transmission GATE TR _ GATE1 is connected with the Vout end of the third CMOS transmission GATE TR _ GATE3 to serve as a Vop pin of the fully differential switch; the Vin end of the third CMOS transmission GATE TR _ GATE3 is connected with the Vin end of the fourth CMOS transmission GATE TR _ GATE4 to serve as a Vin pin of the fully differential switch; the Vout end of the second CMOS transmission GATE TR _ GATE2 is connected with the Vout end of the fourth CMOS transmission GATE TR _ GATE4 to serve as a Von pin of the fully differential switch;
an NMOS transmission path control pin of the first CMOS transmission GATE TR _ GATE1 is connected with an NMOS transmission path control pin of the fourth CMOS transmission GATE TR _ GATE4 and is connected to a main path control pin Vcnm, and a PMOS transmission path control pin of the first CMOS transmission GATE TR _ GATE1 is connected with a PMOS transmission path control pin of the fourth CMOS transmission GATE TR _ GATE4 and is connected to a main path control pin Vcpm; an NMOS transmission path control pin of the second CMOS transmission GATE TR _ GATE2 is connected with an NMOS transmission path control pin of the third CMOS transmission GATE TR _ GATE3 and is connected to a main path control pin Vcnx, and a PMOS transmission path control pin of the second CMOS transmission GATE TR _ GATE2 is connected with a PMOS transmission path control pin of the third CMOS transmission GATE TR _ GATE3 and is connected to the main path control pin Vcpx;
the power supply pins of the four CMOS transmission GATEs of the first CMOS transmission GATE TR _ GATE1, the second CMOS transmission GATE TR _ GATE2, the third CMOS transmission GATE TR _ GATE3 and the fourth CMOS transmission GATE TR _ GATE4 are connected with a power supply voltage VDD, and the grounding pin is connected with 0-potential GND.
Compared with the prior art, the invention has the following advantages:
1. the radio frequency switch is based on an integrated circuit process, is convenient to integrate compared with the traditional discrete device radio frequency switch, and better accords with the mainstream trend of the development of integrated circuits and systems.
2. The radio frequency switch of the present invention is intended for use in the fully differential radio frequency signal path of the front end of a radio frequency transceiver. High isolation between the input and output of the switch off state is achieved by compensation for parasitic radio frequency signal coupling, for which an inverted radio frequency signal is added to the parasitic signal coupled to the first and fourth CMOS transmission GATEs TR _ GATE1 and TR _ GATE4 through the second and third CMOS transmission GATEs TR _ GATE2 and TR _ GATE 3. The compensation aims at eliminating feed-through and achieving high isolation between input and output radio frequency signals.
3. The rf switch of the present invention is bi-directionally conductive and therefore effective when an rf signal is applied to either side of the switch.
4. The radio frequency switch can enable the phase of a radio frequency signal to shift 180 seconds after passing through the switch by configuring the states of the transistors of the main transmission path and the cross transmission path, and can also be used as a balun, which is beneficial to 180 phase conversion across the switch, so that the radio frequency switch has wide application in the field of electronic information.
5. The radio frequency switch of the invention has an ultra-wideband (including low-frequency to ultrahigh-frequency signals) working frequency band, has low insertion loss when the switch is closed, has ultrahigh isolation when the switch is opened, and has excellent power processing characteristics.
6. The switching time of the on-off of the radio frequency switch is very short, the switching time is fast, and the switching time can be controlled by a high-speed control signal.
7. Through verification, the radio frequency switch can be applied to fully differential signal paths in the field of circuits and systems, and has a wide application prospect.
Drawings
Fig. 1 is a circuit configuration diagram of a CMOS transfer gate.
Fig. 2 is a schematic diagram of a transmission gate.
Fig. 3 is a schematic diagram of the switching principle.
Fig. 4 is a schematic diagram of the switch operation mode.
Fig. 5 is a simulation diagram of the insertion loss of the switch.
Fig. 6 is a simulation diagram of the isolation of the switch.
Fig. 7 is a diagram of simulation of the 1dB compression point of the switch.
Fig. 8 is a simulation diagram of switching transition time.
Detailed Description
The technical solution of the present invention is further described below with reference to the accompanying drawings, but not limited thereto, and any modification or equivalent replacement of the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention shall be covered by the protection scope of the present invention.
The invention provides an ultra-wideband low-loss high-isolation fully differential structure radio frequency switch, which consists of four CMOS transmission gates with the same structure, as shown in figure 1, wherein each CMOS transmission gate comprises an NMOS transmission path and a PMOS transmission path, wherein:
the NMOS transmission path is composed of a first NMOS transistor, a second NMOS transistor, a first NMOS transistor gate resistor Rgn1, a second NMOS transistor gate resistor Rgn2, a first NMOS transistor substrate resistor Rbn1, and a second NMOS transistor substrate resistor Rbn 2.
The PMOS transmission path is composed of a first PMOS transistor, a second PMOS transistor, a first PMOS transistor gate resistor Rgp1, a second PMOS transistor gate resistor Rgp2, a first PMOS transistor substrate resistor Rbp1 and a second PMOS transistor substrate resistor Rbp 2.
An input end Vin of the transmission gate is connected with a source electrode of the first NMOS transistor, a drain electrode of the first NMOS transistor is connected with a drain electrode of the second NMOS transistor, one end of a gate resistor Rgn1 of the first NMOS transistor is connected with a gate electrode of the first NMOS transistor, the other end of a gate resistor Rgn1 of the first NMOS transistor is connected with one end of a gate resistor Rgn2 of the second NMOS transistor, a gate resistor Rgn1 of the first NMOS transistor and a gate resistor Rgn2 of the second NMOS transistor are commonly connected with a control voltage Vgn, the other end of a gate resistor Rgn2 of the second NMOS transistor is connected with a gate electrode of the second NMOS transistor, a substrate end of the first NMOS transistor is connected with one end of a substrate resistor Rbn1 of the first NMOS transistor, the other end of the substrate resistor Rbn1 of the first NMOS transistor is connected with GND, the substrate end of the second NMOS transistor is connected with one end of a substrate resistor Rbn2 of the second NMOS transistor, and the other end of the substrate resistor Rbn2 of the second NMOS transistor is connected with GND, the source of the second NMOS transistor is connected to the output terminal Vout of the transmission gate, and thus, the NMOS transmission path connection is completed.
The PMOS transmission path is similar to the NMOS transmission path, the input end Vin of the transmission gate is connected with the source electrode of a first PMOS transistor, the drain electrode of the first PMOS transistor is connected with the drain electrode of a second PMOS transistor, one end of a gate resistor Rgp1 of the first PMOS transistor is connected with the gate electrode of the first PMOS transistor, the other end of a gate resistor Rgp1 of the first PMOS transistor is connected with one end of a gate resistor Rgp2 of the second PMOS transistor, the gate resistor Rgp1 of the first PMOS transistor and the gate resistor Rgp2 of the second PMOS transistor are jointly connected with a control voltage Vgp, the other end of a gate resistor Rgp2 of the second PMOS transistor is connected with the gate electrode of the second PMOS transistor, the substrate end of the first PMOS transistor is connected with one end of a substrate resistor Rbp1 of the first PMOS transistor, the other end of the substrate resistor Rbn1 of the first PMOS transistor is connected with a power supply terminal VDD, the substrate end of the second PMOS transistor is connected with one end of a substrate resistor Rbp2 of the second PMOS transistor, the other end of the second PMOS transistor substrate resistor Rbp2 is connected to the power supply terminal VDD, and the source of the second PMOS transistor is connected to the output terminal Vout of the transmission gate, so that the PMOS transmission path connection is completed.
And finally, the drain electrode of the first NMOS transistor is connected with the drain electrode of the first PMOS transistor to form the whole CMOS transmission gate.
In the present invention, the working principle diagram of the CMOS transmission gate is shown in fig. 2, and the working principle can be simply summarized as follows: when the power supply pin and the grounding pin are respectively connected with a power supply voltage and a ground, the power supply pin and the grounding pin are connected with the control pins Vgn and Vgp through a group of reverse-phase voltages, the Vgn is at a high level, when the Vgp is at a low level, the transmission gate is conducted, otherwise, the Vgn is at a low level, and when the Vgp is at a high level, the transmission gate is not conducted.
In the invention, the substrate end of the NMOS transistor is connected with the high-resistance resistor and then grounded to GND, and the substrate end of the PMOS transistor is connected with the high-resistance resistor and then connected with a power supply VDD, so that the insertion loss can be greatly reduced at high frequency.
In the invention, the grid electrode of the NMOS transistor is connected with a high-resistance resistor and then connected with a control pin Vgn, and the grid electrode of the PMOS transistor is connected with a high-resistance resistor and then connected with a control pin Vgp. The large grid resistance can prevent the radio-frequency signal from passing through the parasitic capacitance and flowing to the control end, ensure the stable bias of the control signal at high and low levels, and greatly reduce the insertion loss, so that the radio-frequency signal can be completely transmitted to the output end as far as possible.
In the invention, the transmission gate adopts a form of cascading two transmission gate units, so that the power compression limitation can be improved, the large signal compression limit is further increased, and the signal power processing capability is improved.
In the invention, the radio frequency switch differential input and differential output are composed of two paths of a main transmission path and a cross transmission path, and the schematic diagram of the principle is shown in fig. 3. The main transmission path is composed of a first CMOS transmission GATE TR _ GATE1 and a fourth CMOS transmission GATE TR _ GATE4 and mainly serves as a transmission path of differential signals. The cross transmission path is composed of a second CMOS transmission GATE TR _ GATE2 and a third CMOS transmission GATE TR _ GATE3, substrate capacitive coupling is mainly reduced, and isolation is improved. Wherein:
the Vin end of the first CMOS transmission GATE TR _ GATE1 is connected with the Vin end of the second transmission GATE TR _ GATE2 to serve as a Vip pin of the fully differential switch; the Vout end of the first CMOS transmission GATE TR _ GATE1 is connected with the Vout end of the third CMOS transmission GATE TR _ GATE3 to serve as a Vop pin of the fully differential switch; the Vin end of the third CMOS transmission GATE TR _ GATE3 is connected with the Vin end of the fourth CMOS transmission GATE TR _ GATE4 to serve as a Vin pin of the fully differential switch; the Vout end of the second CMOS transmission GATE TR _ GATE2 is connected with the Vout end of the fourth CMOS transmission GATE TR _ GATE4 to serve as a Von pin of the fully differential switch;
an NMOS transmission path control pin of the first CMOS transmission GATE TR _ GATE1 is connected with an NMOS transmission path control pin of the fourth CMOS transmission GATE TR _ GATE4 and is connected to a main path control pin Vcnm, and a PMOS transmission path control pin of the first CMOS transmission GATE TR _ GATE1 is connected with a PMOS transmission path control pin of the fourth CMOS transmission GATE TR _ GATE4 and is connected to a main path control pin Vcpm; an NMOS transmission path control pin of the second CMOS transmission GATE TR _ GATE2 is connected with an NMOS transmission path control pin of the third CMOS transmission GATE TR _ GATE3 and is connected to a main path control pin Vcnx, and a PMOS transmission path control pin of the second CMOS transmission GATE TR _ GATE2 is connected with a PMOS transmission path control pin of the third CMOS transmission GATE TR _ GATE3 and is connected to the main path control pin Vcpx;
the power supply pins of the four CMOS transmission GATEs of the first CMOS transmission GATE TR _ GATE1, the second CMOS transmission GATE TR _ GATE2, the third CMOS transmission GATE TR _ GATE3 and the fourth CMOS transmission GATE TR _ GATE4 are connected with a power supply voltage VDD, and the grounding pin is connected with 0-potential GND, so that the fully differential radio frequency switch is formed.
Generally, the isolation of the radio frequency switch is not good because the transmission gate has substrate parasitic capacitance, when the transmission gate is turned off, a radio frequency signal can still pass through the substrate capacitive coupling to the output end, and as the frequency increases, the substrate coupling is enhanced, and the isolation is poor. In addition, in order to reduce the insertion loss, the aspect ratio is increased, and as the aspect ratio is increased, the substrate parasitic capacitance is increased, resulting in increased substrate coupling and poor isolation. Therefore, the prior radio frequency switch needs to make a balance between insertion loss and isolation, but the substrate coupling is greatly offset by introducing the cross transmission path, so that the balance between the insertion loss and the isolation is relaxed, and the insertion loss can be reduced by a larger width-to-length ratio.
In the invention, under the working state of the radio frequency switch, the second transmission GATE TR _ GATE2 and the third transmission GATE TR _ GATE3 are turned off, namely Vcnx is connected with a low level, and Vcpx is connected with a high level. The control pin Vcnm and the control pin Vcpm are connected with a reverse control signal, when the Vcnm is at a high level, namely the Vcpm is at a low level, the radio frequency switch is closed, and differential signals are transmitted through the switch; on the contrary, when Vcnm is at a low level, that is, Vcpm is at a high level, the radio frequency switch is turned on, and the differential signal cannot pass through. Thus, single-pole single-throw is realized, and the on and off of the switch are controlled by one control signal.
Fig. 4 shows three states of the rf switch of the present invention. In the switch closed state, the main transmission path is opened, and the cross transmission path is closed. The rf input signal is passed through the switch to the output and vice versa because the switch is bilateral. In the off state of the switch, the main transmission path and the cross transmission path are closed, all the MOS tubes are in the closed state, the amplitudes of the coupling signals passing through the four paths are equal, and the phases of the coupling signals are opposite, so that the in-phase RF signals of each port are eliminated by the anti-phase RF signals, and the isolation degree of the switch is greatly improved.
Another advantage of the rf switch of the present invention is that by configuring the transistor states of the main transmission path and the cross transmission path, the rf signal can be phase shifted by 180 after passing through the switch◦. The main transmission path is closed, the cross transmission path is opened, namely the first transmission gate and the fourth transmission gate are closed, and the signal passes through the second transmission gate and the third transmission gate, so that the signal phase deviation 180 can be realized◦。
Fig. 5, 6, 7, and 8 are diagrams illustrating insertion loss, isolation, 1dB compression point, and switching transition time, respectively, of the rf switch of the present invention. It can be seen from the figure that the radio frequency switch of the invention realizes large working bandwidth, low insertion loss, high isolation, short conversion time, high linearity and strong power processing capability.

Claims (2)

1. An ultra-wideband low-loss high-isolation fully differential structure radio frequency switch comprising a CMOS transmission gate, characterized in that the CMOS transmission gate comprises an NMOS transmission path and a PMOS transmission path, wherein:
the NMOS transmission path consists of a first NMOS transistor, a second NMOS transistor, a first NMOS transistor gate resistor Rgn1, a second NMOS transistor gate resistor Rgn2, a first NMOS transistor substrate resistor Rbn1 and a second NMOS transistor substrate resistor Rbn 2;
the PMOS transmission path consists of a first PMOS transistor, a second PMOS transistor, a first PMOS transistor gate resistor Rgp1, a second PMOS transistor gate resistor Rgp2, a first PMOS transistor substrate resistor Rbp1 and a second PMOS transistor substrate resistor Rbp 2;
an input end Vin of the CMOS transmission gate is connected with a source electrode of a first NMOS transistor, a drain electrode of the first NMOS transistor is connected with a drain electrode of a second NMOS transistor, one end of a gate resistor Rgn1 of the first NMOS transistor is connected with a gate electrode of the first NMOS transistor, the other end of a gate resistor Rgn1 of the first NMOS transistor is connected with one end of a gate resistor Rgn2 of the second NMOS transistor, a gate resistor Rgn1 of the first NMOS transistor and a gate resistor Rgn2 of the second NMOS transistor are commonly connected with a control voltage Vgn, the other end of a gate resistor Rgn2 of the second NMOS transistor is connected with a gate electrode of the second NMOS transistor, a substrate end of the first NMOS transistor is connected with one end of a substrate resistor Rbn1 of the first NMOS transistor, the other end of the substrate resistor Rbn1 of the first NMOS transistor is connected with GND, the substrate end of the second NMOS transistor is connected with one end of a substrate resistor Rbn2 of the second NMOS transistor, and the other end of the substrate resistor Rbn2 of the second NMOS transistor is connected with GND, the source of the second NMOS transistor is connected to the output terminal Vout of the transmission gate, so that the NMOS transmission path connection is completed;
an input end Vin of the CMOS transmission gate is connected with a source electrode of a first PMOS transistor, a drain electrode of the first PMOS transistor is connected with a drain electrode of a second PMOS transistor, one end of a gate resistor Rgp1 of the first PMOS transistor is connected with a gate electrode of the first PMOS transistor, the other end of a gate resistor Rgp1 of the first PMOS transistor is connected with one end of a gate resistor Rgp2 of the second PMOS transistor, the gate resistor Rgp1 of the first PMOS transistor and the gate resistor Rgp2 of the second PMOS transistor are commonly connected with a control voltage Vgp, the other end of a gate resistor Rgp2 of the second PMOS transistor is connected with a gate electrode of the second PMOS transistor, a substrate end of the first PMOS transistor is connected with one end of a substrate resistor Rbp1 of the first PMOS transistor, the other end of a substrate resistor Rbn1 of the first PMOS transistor is connected with a power supply end VDD, a substrate end of the second PMOS transistor is connected with one end of a substrate resistor Rbp2 of the second PMOS transistor, and the other end of a substrate resistor Rbp2 of the second PMOS transistor is connected with a power supply end VDD, the source of the second PMOS transistor is connected to the output terminal Vout of the transmission gate, so that the PMOS transmission path connection is completed;
and the drain electrode of the first NMOS transistor is connected with the drain electrode of the first PMOS transistor to form the whole CMOS transmission gate.
2. An ultra-wideband low-loss high-isolation fully-differential structure radio-frequency switch, characterized in that the fully-differential structure radio-frequency switch is composed of four of a first CMOS transmission GATE TR _ GATE1, a second CMOS transmission GATE TR _ GATE2, a third CMOS transmission GATE TR _ GATE3 and a fourth CMOS transmission GATE TR _ GATE4 with the CMOS transmission GATE of claim 1, wherein:
the first CMOS transmission GATE TR _ GATE1 and the fourth CMOS transmission GATE TR _ GATE4 form a main transmission path, and the second CMOS transmission GATE TR _ GATE2 and the third CMOS transmission GATE TR _ GATE3 form a cross transmission path;
the Vin end of the first CMOS transmission GATE TR _ GATE1 is connected with the Vin end of the second transmission GATE TR _ GATE2 to serve as a Vip pin of the fully differential switch; the Vout end of the first CMOS transmission GATE TR _ GATE1 is connected with the Vout end of the third CMOS transmission GATE TR _ GATE3 to serve as a Vop pin of the fully differential switch; the Vin end of the third CMOS transmission GATE TR _ GATE3 is connected with the Vin end of the fourth CMOS transmission GATE TR _ GATE4 to serve as a Vin pin of the fully differential switch; the Vout end of the second CMOS transmission GATE TR _ GATE2 is connected with the Vout end of the fourth CMOS transmission GATE TR _ GATE4 to serve as a Von pin of the fully differential switch;
an NMOS transmission path control pin of the first CMOS transmission GATE TR _ GATE1 is connected with an NMOS transmission path control pin of the fourth CMOS transmission GATE TR _ GATE4 and is connected to a main path control pin Vcnm, and a PMOS transmission path control pin of the first CMOS transmission GATE TR _ GATE1 is connected with a PMOS transmission path control pin of the fourth CMOS transmission GATE TR _ GATE4 and is connected to a main path control pin Vcpm; an NMOS transmission path control pin of the second CMOS transmission GATE TR _ GATE2 is connected with an NMOS transmission path control pin of the third CMOS transmission GATE TR _ GATE3 and is connected to a main path control pin Vcnx, and a PMOS transmission path control pin of the second CMOS transmission GATE TR _ GATE2 is connected with a PMOS transmission path control pin of the third CMOS transmission GATE TR _ GATE3 and is connected to the main path control pin Vcpx;
the power supply pins of the four CMOS transmission GATEs of the first CMOS transmission GATE TR _ GATE1, the second CMOS transmission GATE TR _ GATE2, the third CMOS transmission GATE TR _ GATE3 and the fourth CMOS transmission GATE TR _ GATE4 are connected with a power supply voltage VDD, and the grounding pin is connected with 0-potential GND.
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JPH0595266A (en) * 1991-09-30 1993-04-16 Rohm Co Ltd Transmission gate
KR0146082B1 (en) * 1995-09-22 1998-12-01 문정환 Programmable analog switch
CN112838852A (en) * 2020-12-31 2021-05-25 重庆百瑞互联电子技术有限公司 Fully differential single-pole single-throw switch with high isolation and low insertion loss

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